Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22120

1

T2

1

T3

142

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3670

1

T1

1

T2

1

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19575

1

T2

2

T3

142

T4

20

auto[1]

6215

1

T1

1

T5

26

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	65	1			T166	15		T289	37		T311	13
values[0]	69	1			T50	1		T150	10		T284	3
values[1]	730	1			T2	1		T44	19		T141	13
values[2]	3017	1			T7	23		T11	24		T12	11
values[3]	588	1			T5	2		T12	8		T45	11
values[4]	617	1			T1	1		T7	16		T10	1
values[5]	742	1			T8	3		T10	1		T27	1
values[6]	839	1			T5	12		T8	14		T14	1
values[7]	754	1			T25	1		T144	13		T146	11
values[8]	700	1			T5	14		T10	1		T118	29
values[9]	1058	1			T2	1		T6	15		T14	2
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1032	1			T2	1		T7	23		T44	19
values[1]	2885	1			T11	24		T12	19		T36	22
values[2]	560	1			T1	1		T5	2		T7	16
values[3]	668	1			T10	1		T44	2		T37	5
values[4]	810	1			T5	12		T8	3		T14	1
values[5]	886	1			T8	14		T25	15		T144	13
values[6]	693	1			T25	1		T118	29		T148	9
values[7]	732	1			T5	14		T10	1		T31	5
values[8]	768	1			T2	1		T6	14		T14	2
values[9]	142	1			T6	1		T149	4		T164	21
minimum	16614	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	1		T191	1		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T7	12		T44	10		T14	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1627	1			T11	24		T36	2		T87	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	12		T141	13		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	2		T45	11		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T7	14		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T44	1		T141	3		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	1		T37	3		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	12		T8	3		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	1		T25	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T25	1		T144	1		T143	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T8	14		T118	16		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T78	9		T226	15		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T25	1		T118	20		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	14		T10	1		T31	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T142	13		T164	10		T83	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	7		T14	1		T27	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T2	1		T118	7		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T149	1		T218	1		T282	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T6	1		T164	11		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16467	1			T3	142		T4	20		T6	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T191	5		T145	10		T150	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	11		T44	9		T14	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T36	20		T87	13		T188	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T12	7		T265	9		T229	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T226	2		T271	12		T227	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T7	2		T50	9		T150	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T44	1		T15	3		T230	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T37	2		T143	13		T149	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T31	11		T37	3		T225	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T25	12		T148	14		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T25	14		T144	12		T143	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T118	16		T142	10		T101	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T226	12		T154	12		T167	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T118	9		T148	8		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T31	2		T224	11		T154	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T142	13		T164	10		T101	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	7		T14	1		T220	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T118	5		T39	2		T225	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T149	3		T302	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T164	10		T312	8		T313	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	2		T44	1		T45	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T166	8		T289	20		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T311	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T50	1		T150	1		T284	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T314	5		T315	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T145	1		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T44	10		T141	13		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T11	24		T36	2		T87	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	12		T12	7		T14	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	2		T45	11		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	5		T148	1		T50	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T44	1		T141	3		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	1		T7	14		T10	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	3		T37	5		T141	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	1		T27	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T5	12		T25	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T8	14		T14	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T144	1		T175	1		T78	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T25	1		T146	11		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	14		T10	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T118	20		T142	13		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	7		T14	1		T27	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	392	1			T2	1		T6	1		T118	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T166	7		T289	17		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T311	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T150	9		T284	1		T285	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T314	13		T315	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T145	10		T221	1		T166	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T44	9		T151	10		T101	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1084	1			T36	20		T87	13		T188	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	11		T12	4		T14	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	3		T100	9		T228	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T12	3		T50	9		T270	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T44	1		T95	4		T193	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	2		T37	2		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T37	3		T225	14		T151	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T148	14		T39	2		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T25	14		T31	11		T143	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T25	12		T118	16		T142	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T144	12		T175	4		T15	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T220	11		T235	1		T283	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T220	12		T224	11		T154	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T118	9		T142	13		T148	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T6	7		T14	1		T31	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T118	5		T39	2		T225	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T2	1		T191	6		T145	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	12		T44	10		T14	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T11	2		T36	22		T87	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T12	12		T141	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T45	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	1		T7	3		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T44	2		T141	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T10	1		T37	5		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T5	1		T8	1		T31	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	1		T25	13		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T25	15		T144	13		T143	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T8	1		T118	17		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T78	1		T226	13		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T25	1		T118	10		T148	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T10	1		T31	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T142	14		T164	11		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	9		T14	2		T27	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	1		T118	6		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T149	4		T218	1		T282	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T6	1		T164	11		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16613	1			T3	142		T4	20		T6	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T221	3		T166	7		T17	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T7	11		T44	9		T14	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T11	22		T260	11		T177	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T12	7		T141	12		T239	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T45	10		T152	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	13		T50	11		T241	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T141	2		T15	3		T152	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T143	11		T40	3		T242	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	11		T8	2		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T221	4		T224	10		T19	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T143	12		T15	6		T223	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	13		T118	15		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T78	8		T226	14		T167	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T118	19		T235	1		T165	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	13		T31	2		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T142	12		T164	9		T83	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	5		T164	12		T226	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T118	6		T39	1		T225	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T282	1		T302	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T164	10		T312	7		T313	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T284	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T166	8		T289	18		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T311	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T50	1		T150	10		T284	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T314	14		T315	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	1		T145	11		T221	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T44	10		T141	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1433	1			T11	2		T36	22		T87	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	12		T12	7		T14	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	1		T45	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T12	5		T148	1		T50	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T44	2		T141	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	1		T7	3		T10	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	1		T37	6		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T10	1		T27	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T25	15		T31	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	1		T14	1		T25	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T144	13		T175	5		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T25	1		T146	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	1		T10	1		T220	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T118	10		T142	14		T148	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T6	9		T14	2		T27	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T2	1		T6	1		T118	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T166	7		T289	19		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T311	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T284	1		T285	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T314	4		T315	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T166	7		T17	9		T228	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T44	9		T141	12		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T11	22		T260	11		T177	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	11		T12	4		T14	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	1		T45	10		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T12	3		T50	11		T167	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T141	2		T152	17		T193	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	13		T143	11		T159	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	2		T37	2		T141	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T40	3		T224	10		T242	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	11		T146	6		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	13		T118	15		T142	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T78	8		T15	6		T226	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T146	10		T235	1		T283	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	13		T224	11		T259	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T118	19		T142	12		T83	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	5		T31	2		T164	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T118	6		T39	1		T225	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24