Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22591

1

T1

1

T3

142

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3199

1

T2

2

T5

28

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19528

1

T2

2

T3

139

T4

20

auto[1]

6262

1

T1

1

T3

3

T5

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	532	1			T3	3		T6	10		T8	3
values[0]	29	1			T298	3		T299	1		T303	11
values[1]	849	1			T10	1		T118	32		T141	7
values[2]	3032	1			T2	1		T11	24		T12	8
values[3]	668	1			T5	14		T7	23		T10	1
values[4]	614	1			T1	1		T14	5		T144	13
values[5]	619	1			T2	1		T6	14		T14	1
values[6]	751	1			T5	2		T10	1		T12	11
values[7]	821	1			T7	16		T118	29		T143	29
values[8]	547	1			T8	14		T27	1		T31	5
values[9]	1096	1			T5	12		T6	1		T27	1
minimum	16232	1			T3	139		T4	20		T6	105

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	783	1			T10	1		T31	12		T118	44
values[1]	2950	1			T2	1		T7	23		T11	24
values[2]	811	1			T5	14		T10	1		T44	21
values[3]	533	1			T1	1		T6	14		T14	6
values[4]	609	1			T2	1		T25	14		T27	1
values[5]	797	1			T5	2		T7	16		T10	1
values[6]	670	1			T118	29		T143	29		T279	1
values[7]	736	1			T5	12		T8	14		T27	1
values[8]	927	1			T6	1		T8	3		T27	1
values[9]	78	1			T14	2		T150	10		T253	15
minimum	16896	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T31	1		T118	7		T141	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	1		T118	16		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T7	12		T11	24		T12	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	1		T141	13		T148	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T10	1		T44	10		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	14		T44	1		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	1		T14	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	7		T14	3		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T25	2		T27	1		T45	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T198	1		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T37	3		T40	10		T316	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	2		T7	14		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T143	13		T83	3		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T118	20		T279	1		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T8	14		T31	3		T141	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	12		T27	1		T221	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T8	3		T27	1		T142	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	1		T146	7		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T110	5		T267	1		T310	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T14	1		T150	1		T253	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16547	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T220	1		T228	5		T193	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T31	11		T118	5		T149	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T118	16		T151	9		T100	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T7	11		T12	3		T36	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T148	22		T50	9		T221	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T44	9		T39	2		T164	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T44	1		T151	10		T101	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T225	2		T219	9		T167	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T6	7		T14	2		T144	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T25	12		T142	13		T175	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T253	10		T95	4		T170	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T37	2		T40	1		T242	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	2		T12	4		T221	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T143	16		T113	14		T97	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T118	9		T166	1		T154	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T31	2		T143	13		T226	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T221	3		T225	9		T220	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T142	10		T149	11		T164	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	15		T301	4		T231	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T14	1		T150	9		T253	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	2		T44	1		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T220	11		T228	6		T193	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	443	1			T3	3		T6	10		T8	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T14	1		T150	1		T301	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T298	2		T303	11		T305	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T141	7		T145	1		T146	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	1		T118	16		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T11	24		T12	5		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T141	13		T148	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T7	12		T10	1		T44	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T5	14		T44	1		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	1		T142	1		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	3		T144	1		T164	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	1		T25	2		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	1		T6	7		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T37	3		T148	1		T39	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	2		T10	1		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T143	13		T83	3		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	14		T118	20		T221	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	14		T31	3		T141	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T27	1		T146	7		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T27	1		T142	11		T164	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T5	12		T6	1		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16086	1			T3	139		T4	20		T6	105
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T149	11		T170	16		T317	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T14	1		T150	9		T301	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T298	1		T305	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T145	10		T149	3		T39	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T118	16		T220	11		T100	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T12	3		T36	20		T87	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T148	22		T50	9		T221	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	11		T44	9		T191	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T44	1		T151	10		T101	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T39	2		T164	19		T219	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	2		T144	12		T164	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T25	12		T142	13		T175	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T6	7		T95	4		T170	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T37	2		T40	1		T242	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	4		T151	18		T15	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T143	16		T228	20		T270	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	2		T118	9		T221	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T31	2		T143	13		T166	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T220	12		T41	3		T228	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T142	10		T164	10		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T221	3		T225	9		T16	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T31	12		T118	6		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	1		T118	17		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T7	12		T11	2		T12	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T141	1		T148	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T10	1		T44	10		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	1		T44	2		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T14	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	9		T14	3		T144	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T25	14		T27	1		T45	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T2	1		T198	1		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T37	5		T40	8		T316	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	1		T7	3		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T143	17		T83	1		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T118	10		T279	1		T166	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	1		T31	3		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	1		T27	1		T221	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T8	1		T27	1		T142	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	1		T146	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T110	5		T267	1		T310	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T14	2		T150	10		T253	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16680	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T220	12		T228	7		T193	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T118	6		T141	6		T146	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T118	15		T152	17		T240	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T7	11		T11	22		T12	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T141	12		T50	11		T225	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T44	9		T164	12		T226	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	13		T239	10		T224	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T219	16		T167	12		T230	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	5		T14	2		T164	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T45	10		T142	12		T39	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T243	7		T170	14		T250	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T40	3		T242	3		T166	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T7	13		T12	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T143	12		T83	2		T167	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T118	19		T229	9		T227	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	13		T31	2		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	11		T221	3		T225	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T8	2		T142	10		T164	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T146	6		T239	10		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T310	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T318	1		T308	7		T309	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T83	2		T264	17		T319	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T228	4		T193	10		T284	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	437	1			T3	3		T6	10		T8	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T14	2		T150	10		T301	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T298	2		T303	1		T305	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T141	1		T145	11		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	1		T118	17		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T11	2		T12	5		T36	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	1		T141	1		T148	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T7	12		T10	1		T44	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	1		T44	2		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	1		T142	1		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	3		T144	13		T164	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	1		T25	14		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T2	1		T6	9		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T37	5		T148	1		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	1		T10	1		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T143	17		T83	1		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	3		T118	10		T221	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	1		T31	3		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T27	1		T146	1		T220	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T27	1		T142	11		T164	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	1		T6	1		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16232	1			T3	139		T4	20		T6	105
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T8	2		T78	8		T170	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T320	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T298	1		T303	10		T305	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T141	6		T146	10		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T118	15		T240	10		T228	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T11	22		T12	3		T118	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T141	12		T50	11		T225	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	11		T44	9		T226	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T5	13		T224	10		T248	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T164	12		T219	16		T230	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	2		T164	9		T15	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T45	10		T142	12		T167	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	5		T170	14		T250	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	12		T40	3		T242	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	1		T12	4		T15	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T143	12		T83	2		T228	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	13		T118	19		T221	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	13		T31	2		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T146	6		T41	3		T228	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T142	10		T164	10		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	11		T221	3		T225	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24