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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.14


Total test records in report: 916
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T798 /workspace/coverage/default/1.adc_ctrl_filters_wakeup.4200352654 Aug 05 06:10:28 PM PDT 24 Aug 05 06:26:23 PM PDT 24 384582351003 ps
T799 /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3356800501 Aug 05 06:10:28 PM PDT 24 Aug 05 06:16:58 PM PDT 24 193348761187 ps
T800 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.909389293 Aug 05 06:10:21 PM PDT 24 Aug 05 06:10:22 PM PDT 24 373038704 ps
T54 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3879923571 Aug 05 06:09:38 PM PDT 24 Aug 05 06:09:42 PM PDT 24 4543040406 ps
T57 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1212245535 Aug 05 06:10:11 PM PDT 24 Aug 05 06:10:12 PM PDT 24 538106749 ps
T51 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2650707346 Aug 05 06:09:57 PM PDT 24 Aug 05 06:12:55 PM PDT 24 51767492152 ps
T52 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3614945598 Aug 05 06:09:54 PM PDT 24 Aug 05 06:10:46 PM PDT 24 23077721288 ps
T58 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4101287389 Aug 05 06:10:08 PM PDT 24 Aug 05 06:10:09 PM PDT 24 903561951 ps
T55 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3769844736 Aug 05 06:10:05 PM PDT 24 Aug 05 06:10:15 PM PDT 24 4439652241 ps
T138 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2143968286 Aug 05 06:10:17 PM PDT 24 Aug 05 06:10:19 PM PDT 24 522075798 ps
T119 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3227564178 Aug 05 06:09:51 PM PDT 24 Aug 05 06:09:54 PM PDT 24 929044537 ps
T801 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2459765129 Aug 05 06:10:23 PM PDT 24 Aug 05 06:10:25 PM PDT 24 348058871 ps
T802 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1874414444 Aug 05 06:09:48 PM PDT 24 Aug 05 06:09:49 PM PDT 24 320353263 ps
T803 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3558793678 Aug 05 06:10:20 PM PDT 24 Aug 05 06:10:21 PM PDT 24 447762151 ps
T53 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4091995726 Aug 05 06:09:53 PM PDT 24 Aug 05 06:10:11 PM PDT 24 3702771253 ps
T63 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2994789535 Aug 05 06:10:25 PM PDT 24 Aug 05 06:10:27 PM PDT 24 551311770 ps
T804 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2865344791 Aug 05 06:10:04 PM PDT 24 Aug 05 06:10:06 PM PDT 24 448691046 ps
T64 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3970134134 Aug 05 06:10:27 PM PDT 24 Aug 05 06:10:35 PM PDT 24 835297916 ps
T805 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.836743796 Aug 05 06:10:15 PM PDT 24 Aug 05 06:10:17 PM PDT 24 372391777 ps
T120 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3098500653 Aug 05 06:09:47 PM PDT 24 Aug 05 06:10:19 PM PDT 24 29001788302 ps
T56 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.145898766 Aug 05 06:10:01 PM PDT 24 Aug 05 06:10:17 PM PDT 24 8059147684 ps
T139 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2606020223 Aug 05 06:09:58 PM PDT 24 Aug 05 06:11:03 PM PDT 24 53748138809 ps
T67 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2740666013 Aug 05 06:09:57 PM PDT 24 Aug 05 06:10:10 PM PDT 24 4596432633 ps
T59 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.427400620 Aug 05 06:09:54 PM PDT 24 Aug 05 06:09:59 PM PDT 24 7815001854 ps
T121 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.38460035 Aug 05 06:10:10 PM PDT 24 Aug 05 06:10:12 PM PDT 24 386822418 ps
T806 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1688947451 Aug 05 06:10:04 PM PDT 24 Aug 05 06:10:05 PM PDT 24 550265431 ps
T807 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3293804589 Aug 05 06:10:06 PM PDT 24 Aug 05 06:10:08 PM PDT 24 494426173 ps
T75 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4168324388 Aug 05 06:10:02 PM PDT 24 Aug 05 06:10:08 PM PDT 24 4070968550 ps
T122 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2821533976 Aug 05 06:10:26 PM PDT 24 Aug 05 06:10:27 PM PDT 24 533447701 ps
T89 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.957084739 Aug 05 06:10:21 PM PDT 24 Aug 05 06:10:23 PM PDT 24 370338179 ps
T132 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.860042744 Aug 05 06:10:12 PM PDT 24 Aug 05 06:10:14 PM PDT 24 4391576130 ps
T71 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.398527674 Aug 05 06:10:20 PM PDT 24 Aug 05 06:10:32 PM PDT 24 4350021706 ps
T90 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1549688314 Aug 05 06:10:36 PM PDT 24 Aug 05 06:10:39 PM PDT 24 492024368 ps
T808 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4257036317 Aug 05 06:10:18 PM PDT 24 Aug 05 06:10:19 PM PDT 24 540825281 ps
T140 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2530343690 Aug 05 06:10:24 PM PDT 24 Aug 05 06:10:26 PM PDT 24 323683449 ps
T809 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2304954702 Aug 05 06:10:24 PM PDT 24 Aug 05 06:10:24 PM PDT 24 631319088 ps
T70 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3271612615 Aug 05 06:09:59 PM PDT 24 Aug 05 06:10:01 PM PDT 24 509630006 ps
T68 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.4104958015 Aug 05 06:10:14 PM PDT 24 Aug 05 06:10:17 PM PDT 24 422337362 ps
T810 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3857924945 Aug 05 06:09:54 PM PDT 24 Aug 05 06:09:56 PM PDT 24 410719869 ps
T811 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3904988698 Aug 05 06:09:51 PM PDT 24 Aug 05 06:09:52 PM PDT 24 400083339 ps
T65 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2373555326 Aug 05 06:10:01 PM PDT 24 Aug 05 06:10:04 PM PDT 24 344597256 ps
T812 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3946990897 Aug 05 06:10:16 PM PDT 24 Aug 05 06:10:18 PM PDT 24 436609843 ps
T813 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3461582656 Aug 05 06:10:10 PM PDT 24 Aug 05 06:10:12 PM PDT 24 315495728 ps
T133 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.586746999 Aug 05 06:10:01 PM PDT 24 Aug 05 06:10:21 PM PDT 24 4848499806 ps
T123 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2205625419 Aug 05 06:10:09 PM PDT 24 Aug 05 06:10:10 PM PDT 24 513717556 ps
T814 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1681970328 Aug 05 06:10:03 PM PDT 24 Aug 05 06:10:05 PM PDT 24 525023496 ps
T815 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1435158622 Aug 05 06:10:25 PM PDT 24 Aug 05 06:10:27 PM PDT 24 278777873 ps
T816 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3746309835 Aug 05 06:10:01 PM PDT 24 Aug 05 06:10:13 PM PDT 24 4732790081 ps
T817 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3839680631 Aug 05 06:10:17 PM PDT 24 Aug 05 06:10:18 PM PDT 24 321031750 ps
T124 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2685242315 Aug 05 06:09:55 PM PDT 24 Aug 05 06:09:57 PM PDT 24 1345463899 ps
T818 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.56885725 Aug 05 06:09:53 PM PDT 24 Aug 05 06:09:54 PM PDT 24 313066683 ps
T819 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.664846512 Aug 05 06:10:18 PM PDT 24 Aug 05 06:10:20 PM PDT 24 434030047 ps
T820 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4198188307 Aug 05 06:10:10 PM PDT 24 Aug 05 06:10:11 PM PDT 24 325526867 ps
T134 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1526829066 Aug 05 06:10:01 PM PDT 24 Aug 05 06:10:16 PM PDT 24 4065794431 ps
T821 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3953277149 Aug 05 06:10:20 PM PDT 24 Aug 05 06:10:21 PM PDT 24 453824305 ps
T72 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2007682229 Aug 05 06:10:03 PM PDT 24 Aug 05 06:10:11 PM PDT 24 9026309772 ps
T822 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4152896899 Aug 05 06:10:18 PM PDT 24 Aug 05 06:10:20 PM PDT 24 432186202 ps
T135 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4255404861 Aug 05 06:10:18 PM PDT 24 Aug 05 06:10:22 PM PDT 24 2107523949 ps
T66 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.742186976 Aug 05 06:09:55 PM PDT 24 Aug 05 06:09:58 PM PDT 24 1109355932 ps
T823 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.731492735 Aug 05 06:10:24 PM PDT 24 Aug 05 06:10:25 PM PDT 24 609500733 ps
T824 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1021831047 Aug 05 06:10:25 PM PDT 24 Aug 05 06:10:26 PM PDT 24 440788784 ps
T825 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2173597416 Aug 05 06:10:02 PM PDT 24 Aug 05 06:10:04 PM PDT 24 499054191 ps
T69 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2927794174 Aug 05 06:09:47 PM PDT 24 Aug 05 06:09:49 PM PDT 24 459072444 ps
T73 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1495048320 Aug 05 06:10:06 PM PDT 24 Aug 05 06:10:08 PM PDT 24 503206344 ps
T74 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2117619908 Aug 05 06:09:54 PM PDT 24 Aug 05 06:09:56 PM PDT 24 474139183 ps
T136 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2567806069 Aug 05 06:10:01 PM PDT 24 Aug 05 06:10:04 PM PDT 24 4902996690 ps
T826 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1156848075 Aug 05 06:10:04 PM PDT 24 Aug 05 06:10:06 PM PDT 24 299966866 ps
T827 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3325758219 Aug 05 06:10:07 PM PDT 24 Aug 05 06:10:08 PM PDT 24 305089921 ps
T350 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1966615659 Aug 05 06:10:06 PM PDT 24 Aug 05 06:10:26 PM PDT 24 8674255701 ps
T828 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3205711071 Aug 05 06:10:14 PM PDT 24 Aug 05 06:10:15 PM PDT 24 417716441 ps
T829 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1379398623 Aug 05 06:10:06 PM PDT 24 Aug 05 06:10:30 PM PDT 24 8816874293 ps
T830 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3326706546 Aug 05 06:09:48 PM PDT 24 Aug 05 06:09:50 PM PDT 24 594626672 ps
T831 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3658589507 Aug 05 06:10:05 PM PDT 24 Aug 05 06:10:06 PM PDT 24 506677449 ps
T137 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1908146209 Aug 05 06:10:11 PM PDT 24 Aug 05 06:10:13 PM PDT 24 424124124 ps
T832 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1235651169 Aug 05 06:09:38 PM PDT 24 Aug 05 06:09:44 PM PDT 24 8638054874 ps
T833 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3241444661 Aug 05 06:10:00 PM PDT 24 Aug 05 06:10:04 PM PDT 24 450741981 ps
T834 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1415547946 Aug 05 06:10:21 PM PDT 24 Aug 05 06:10:22 PM PDT 24 497559328 ps
T835 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.808234401 Aug 05 06:10:21 PM PDT 24 Aug 05 06:10:22 PM PDT 24 593981573 ps
T836 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2917869863 Aug 05 06:09:52 PM PDT 24 Aug 05 06:09:58 PM PDT 24 1960413198 ps
T837 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1136026340 Aug 05 06:10:09 PM PDT 24 Aug 05 06:10:28 PM PDT 24 7973120619 ps
T125 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2733238410 Aug 05 06:09:48 PM PDT 24 Aug 05 06:09:54 PM PDT 24 1002486539 ps
T838 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3831241932 Aug 05 06:09:49 PM PDT 24 Aug 05 06:09:50 PM PDT 24 572960546 ps
T839 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.344823188 Aug 05 06:10:05 PM PDT 24 Aug 05 06:10:11 PM PDT 24 3939133699 ps
T840 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1747070374 Aug 05 06:09:54 PM PDT 24 Aug 05 06:10:04 PM PDT 24 3925836412 ps
T841 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3720356371 Aug 05 06:10:14 PM PDT 24 Aug 05 06:10:33 PM PDT 24 8005518538 ps
T842 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.962566386 Aug 05 06:10:12 PM PDT 24 Aug 05 06:10:15 PM PDT 24 725195553 ps
T843 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.858258875 Aug 05 06:10:16 PM PDT 24 Aug 05 06:10:17 PM PDT 24 370197872 ps
T844 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3617265666 Aug 05 06:10:04 PM PDT 24 Aug 05 06:10:05 PM PDT 24 341775427 ps
T845 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4126120777 Aug 05 06:10:12 PM PDT 24 Aug 05 06:10:13 PM PDT 24 319123357 ps
T846 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3147696317 Aug 05 06:10:21 PM PDT 24 Aug 05 06:10:24 PM PDT 24 551081846 ps
T126 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3443730773 Aug 05 06:09:48 PM PDT 24 Aug 05 06:09:49 PM PDT 24 410454817 ps
T847 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.928611522 Aug 05 06:10:25 PM PDT 24 Aug 05 06:10:28 PM PDT 24 418389042 ps
T848 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3545195574 Aug 05 06:09:59 PM PDT 24 Aug 05 06:10:05 PM PDT 24 8423792981 ps
T849 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.737088533 Aug 05 06:10:05 PM PDT 24 Aug 05 06:10:06 PM PDT 24 346612790 ps
T850 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4242217695 Aug 05 06:10:09 PM PDT 24 Aug 05 06:10:10 PM PDT 24 462449648 ps
T851 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2618809930 Aug 05 06:09:49 PM PDT 24 Aug 05 06:09:55 PM PDT 24 549425849 ps
T852 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.979364022 Aug 05 06:09:58 PM PDT 24 Aug 05 06:10:02 PM PDT 24 637037881 ps
T853 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.757936118 Aug 05 06:09:58 PM PDT 24 Aug 05 06:09:59 PM PDT 24 618230706 ps
T854 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.122186067 Aug 05 06:10:03 PM PDT 24 Aug 05 06:10:05 PM PDT 24 569907783 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1199999889 Aug 05 06:09:53 PM PDT 24 Aug 05 06:10:06 PM PDT 24 4405832204 ps
T856 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1754288024 Aug 05 06:10:17 PM PDT 24 Aug 05 06:10:18 PM PDT 24 331227039 ps
T857 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2843900231 Aug 05 06:10:04 PM PDT 24 Aug 05 06:10:06 PM PDT 24 529495587 ps
T858 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.681043486 Aug 05 06:10:02 PM PDT 24 Aug 05 06:10:15 PM PDT 24 8475395375 ps
T859 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2050748046 Aug 05 06:10:08 PM PDT 24 Aug 05 06:10:15 PM PDT 24 5262246289 ps
T860 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1306815679 Aug 05 06:10:04 PM PDT 24 Aug 05 06:10:23 PM PDT 24 8201079673 ps
T861 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3658343703 Aug 05 06:10:09 PM PDT 24 Aug 05 06:10:11 PM PDT 24 528481407 ps
T862 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1794638969 Aug 05 06:09:59 PM PDT 24 Aug 05 06:10:02 PM PDT 24 477179862 ps
T863 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.894943585 Aug 05 06:10:26 PM PDT 24 Aug 05 06:10:27 PM PDT 24 370860772 ps
T864 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1346424405 Aug 05 06:10:23 PM PDT 24 Aug 05 06:10:28 PM PDT 24 4452514379 ps
T865 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1598435675 Aug 05 06:10:16 PM PDT 24 Aug 05 06:10:17 PM PDT 24 478383318 ps
T866 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3034543449 Aug 05 06:09:55 PM PDT 24 Aug 05 06:09:57 PM PDT 24 337238463 ps
T867 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.702873296 Aug 05 06:09:57 PM PDT 24 Aug 05 06:09:58 PM PDT 24 2375552570 ps
T868 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3142292851 Aug 05 06:10:20 PM PDT 24 Aug 05 06:10:23 PM PDT 24 5162214212 ps
T869 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3687443836 Aug 05 06:10:18 PM PDT 24 Aug 05 06:10:20 PM PDT 24 375702129 ps
T870 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2496405087 Aug 05 06:09:36 PM PDT 24 Aug 05 06:09:37 PM PDT 24 1342625112 ps
T871 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1977388258 Aug 05 06:10:18 PM PDT 24 Aug 05 06:10:22 PM PDT 24 4456539880 ps
T127 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3450563704 Aug 05 06:10:02 PM PDT 24 Aug 05 06:10:03 PM PDT 24 549033402 ps
T872 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1207513513 Aug 05 06:10:07 PM PDT 24 Aug 05 06:10:08 PM PDT 24 453349019 ps
T128 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3584115926 Aug 05 06:09:58 PM PDT 24 Aug 05 06:10:01 PM PDT 24 711695069 ps
T873 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3349994930 Aug 05 06:10:05 PM PDT 24 Aug 05 06:10:06 PM PDT 24 413285241 ps
T874 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1924298052 Aug 05 06:10:24 PM PDT 24 Aug 05 06:10:26 PM PDT 24 309446261 ps
T875 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1647017040 Aug 05 06:09:43 PM PDT 24 Aug 05 06:10:00 PM PDT 24 4367069245 ps
T876 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1957959116 Aug 05 06:09:55 PM PDT 24 Aug 05 06:10:00 PM PDT 24 910754551 ps
T877 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.406428121 Aug 05 06:10:03 PM PDT 24 Aug 05 06:10:05 PM PDT 24 461263446 ps
T878 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3061536875 Aug 05 06:09:52 PM PDT 24 Aug 05 06:09:55 PM PDT 24 1052684205 ps
T129 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.844210697 Aug 05 06:09:57 PM PDT 24 Aug 05 06:10:06 PM PDT 24 8131143902 ps
T879 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2477438044 Aug 05 06:10:03 PM PDT 24 Aug 05 06:10:05 PM PDT 24 509944269 ps
T880 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4250059138 Aug 05 06:10:15 PM PDT 24 Aug 05 06:10:18 PM PDT 24 626920532 ps
T881 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.595454698 Aug 05 06:10:08 PM PDT 24 Aug 05 06:10:09 PM PDT 24 493279299 ps
T882 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.269984332 Aug 05 06:10:01 PM PDT 24 Aug 05 06:10:04 PM PDT 24 5214165904 ps
T883 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1501092004 Aug 05 06:10:25 PM PDT 24 Aug 05 06:10:26 PM PDT 24 288241866 ps
T884 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3949149144 Aug 05 06:10:11 PM PDT 24 Aug 05 06:10:32 PM PDT 24 8388401802 ps
T885 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.81977747 Aug 05 06:09:52 PM PDT 24 Aug 05 06:09:55 PM PDT 24 1284966836 ps
T886 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3250496991 Aug 05 06:10:10 PM PDT 24 Aug 05 06:10:13 PM PDT 24 461868574 ps
T887 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.970734493 Aug 05 06:09:54 PM PDT 24 Aug 05 06:09:55 PM PDT 24 418536715 ps
T888 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2761040344 Aug 05 06:10:09 PM PDT 24 Aug 05 06:10:12 PM PDT 24 683155198 ps
T889 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.4231379865 Aug 05 06:10:15 PM PDT 24 Aug 05 06:10:16 PM PDT 24 402137035 ps
T890 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2907298505 Aug 05 06:09:43 PM PDT 24 Aug 05 06:09:45 PM PDT 24 622028154 ps
T891 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3178566769 Aug 05 06:10:05 PM PDT 24 Aug 05 06:10:06 PM PDT 24 284199579 ps
T892 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3134116301 Aug 05 06:10:01 PM PDT 24 Aug 05 06:10:08 PM PDT 24 448256100 ps
T893 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4172419418 Aug 05 06:10:02 PM PDT 24 Aug 05 06:10:04 PM PDT 24 530452194 ps
T894 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1145565424 Aug 05 06:10:02 PM PDT 24 Aug 05 06:10:03 PM PDT 24 332147338 ps
T895 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.346859171 Aug 05 06:09:55 PM PDT 24 Aug 05 06:09:59 PM PDT 24 1225159957 ps
T896 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1021160481 Aug 05 06:10:05 PM PDT 24 Aug 05 06:10:06 PM PDT 24 471924019 ps
T897 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3978673847 Aug 05 06:10:20 PM PDT 24 Aug 05 06:10:29 PM PDT 24 4438197577 ps
T898 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.97777036 Aug 05 06:10:00 PM PDT 24 Aug 05 06:10:10 PM PDT 24 2683891408 ps
T899 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1040803793 Aug 05 06:09:47 PM PDT 24 Aug 05 06:09:48 PM PDT 24 385503090 ps
T900 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2166648996 Aug 05 06:10:04 PM PDT 24 Aug 05 06:10:05 PM PDT 24 757611621 ps
T901 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.447604737 Aug 05 06:10:21 PM PDT 24 Aug 05 06:10:22 PM PDT 24 415721623 ps
T130 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1135639962 Aug 05 06:10:00 PM PDT 24 Aug 05 06:10:02 PM PDT 24 411648616 ps
T902 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1870767523 Aug 05 06:10:05 PM PDT 24 Aug 05 06:10:07 PM PDT 24 422231801 ps
T903 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2348760978 Aug 05 06:10:03 PM PDT 24 Aug 05 06:10:04 PM PDT 24 582844099 ps
T904 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3850033859 Aug 05 06:10:01 PM PDT 24 Aug 05 06:10:02 PM PDT 24 497290736 ps
T905 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.435946688 Aug 05 06:09:59 PM PDT 24 Aug 05 06:10:01 PM PDT 24 539946155 ps
T131 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3478813384 Aug 05 06:10:03 PM PDT 24 Aug 05 06:10:06 PM PDT 24 792300458 ps
T906 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3329580549 Aug 05 06:10:02 PM PDT 24 Aug 05 06:10:03 PM PDT 24 557193019 ps
T907 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3685405666 Aug 05 06:10:04 PM PDT 24 Aug 05 06:10:05 PM PDT 24 351486603 ps
T908 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3576877071 Aug 05 06:10:06 PM PDT 24 Aug 05 06:10:07 PM PDT 24 487704568 ps
T909 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.477762836 Aug 05 06:10:13 PM PDT 24 Aug 05 06:10:14 PM PDT 24 510426588 ps
T910 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3258004066 Aug 05 06:10:03 PM PDT 24 Aug 05 06:10:05 PM PDT 24 365849906 ps
T911 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3414798161 Aug 05 06:10:10 PM PDT 24 Aug 05 06:10:11 PM PDT 24 586584787 ps
T912 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3031921413 Aug 05 06:10:02 PM PDT 24 Aug 05 06:10:09 PM PDT 24 4951577293 ps
T913 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2893399650 Aug 05 06:09:48 PM PDT 24 Aug 05 06:09:49 PM PDT 24 431634409 ps
T914 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2133073526 Aug 05 06:10:06 PM PDT 24 Aug 05 06:10:07 PM PDT 24 418312740 ps
T915 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2197294160 Aug 05 06:09:59 PM PDT 24 Aug 05 06:10:01 PM PDT 24 2070061036 ps
T916 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1142739136 Aug 05 06:10:26 PM PDT 24 Aug 05 06:10:32 PM PDT 24 449930081 ps

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2266552136
Short name T6
Test name
Test status
Simulation time 222355371312 ps
CPU time 244.19 seconds
Started Aug 05 06:10:43 PM PDT 24
Finished Aug 05 06:14:47 PM PDT 24
Peak memory 210488 kb
Host smart-33a07b2c-0326-44fc-bfa4-3e42b4ccb9f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266552136 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2266552136
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.297936574
Short name T5
Test name
Test status
Simulation time 603794891793 ps
CPU time 666.38 seconds
Started Aug 05 06:12:45 PM PDT 24
Finished Aug 05 06:23:52 PM PDT 24
Peak memory 201476 kb
Host smart-20f46f8d-1e62-43b2-8c42-502b9a45afcd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297936574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.297936574
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3848159540
Short name T50
Test name
Test status
Simulation time 645507657336 ps
CPU time 818.33 seconds
Started Aug 05 06:12:19 PM PDT 24
Finished Aug 05 06:25:57 PM PDT 24
Peak memory 210088 kb
Host smart-049c5560-68d5-4b00-903e-ccacf00779e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848159540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3848159540
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3279053762
Short name T15
Test name
Test status
Simulation time 444513103781 ps
CPU time 56.82 seconds
Started Aug 05 06:11:20 PM PDT 24
Finished Aug 05 06:12:17 PM PDT 24
Peak memory 209756 kb
Host smart-4ebaae98-53c0-40a3-a7cb-39b9af2ef5b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279053762 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3279053762
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2716716690
Short name T118
Test name
Test status
Simulation time 557087996979 ps
CPU time 107.56 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:12:43 PM PDT 24
Peak memory 201512 kb
Host smart-d29401ca-efed-4575-adbd-3232e42df12f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716716690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2716716690
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3431753243
Short name T166
Test name
Test status
Simulation time 768206759543 ps
CPU time 1280.74 seconds
Started Aug 05 06:11:44 PM PDT 24
Finished Aug 05 06:33:05 PM PDT 24
Peak memory 210020 kb
Host smart-d6c897af-45c9-451e-b0d1-cf915ed6643f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431753243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3431753243
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3512481364
Short name T47
Test name
Test status
Simulation time 104007737467 ps
CPU time 442.82 seconds
Started Aug 05 06:11:21 PM PDT 24
Finished Aug 05 06:18:44 PM PDT 24
Peak memory 201820 kb
Host smart-05be4435-e846-45d3-a8ce-e69e7e89229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512481364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3512481364
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2847905191
Short name T25
Test name
Test status
Simulation time 497891989523 ps
CPU time 1155.97 seconds
Started Aug 05 06:11:10 PM PDT 24
Finished Aug 05 06:30:26 PM PDT 24
Peak memory 201388 kb
Host smart-ccdf04f3-56df-4297-89a7-cdc9cf1ffd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847905191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2847905191
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3860218812
Short name T142
Test name
Test status
Simulation time 486329081803 ps
CPU time 616.39 seconds
Started Aug 05 06:13:04 PM PDT 24
Finished Aug 05 06:23:20 PM PDT 24
Peak memory 201460 kb
Host smart-7e48edbf-17d5-4601-8d37-4ec64815c345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860218812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3860218812
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.529527538
Short name T229
Test name
Test status
Simulation time 500269099337 ps
CPU time 350.92 seconds
Started Aug 05 06:11:37 PM PDT 24
Finished Aug 05 06:17:28 PM PDT 24
Peak memory 201460 kb
Host smart-1d238c3b-6a9b-4ce9-a03c-26c700426728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529527538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
529527538
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1495335314
Short name T143
Test name
Test status
Simulation time 366403406181 ps
CPU time 131.88 seconds
Started Aug 05 06:12:47 PM PDT 24
Finished Aug 05 06:14:59 PM PDT 24
Peak memory 201460 kb
Host smart-9c2eba45-f438-45b6-b5f3-4f95f080f989
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495335314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1495335314
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.961506385
Short name T60
Test name
Test status
Simulation time 7750389915 ps
CPU time 5.54 seconds
Started Aug 05 06:10:34 PM PDT 24
Finished Aug 05 06:10:40 PM PDT 24
Peak memory 218208 kb
Host smart-501284ca-af35-4b31-8660-70f730bc1c05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961506385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.961506385
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3970134134
Short name T64
Test name
Test status
Simulation time 835297916 ps
CPU time 2.57 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:10:35 PM PDT 24
Peak memory 201600 kb
Host smart-5dbc962b-4c15-4749-8728-420296a0ef76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970134134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3970134134
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.4200205557
Short name T7
Test name
Test status
Simulation time 345649355936 ps
CPU time 198.61 seconds
Started Aug 05 06:11:38 PM PDT 24
Finished Aug 05 06:14:56 PM PDT 24
Peak memory 201468 kb
Host smart-ac0eb0a9-d24d-4d84-bf5e-0d6d50d0a9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200205557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.4200205557
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2148174134
Short name T225
Test name
Test status
Simulation time 531763417444 ps
CPU time 317.09 seconds
Started Aug 05 06:12:45 PM PDT 24
Finished Aug 05 06:18:02 PM PDT 24
Peak memory 201336 kb
Host smart-8648bd86-6ae3-4226-b2f1-986e79f7d90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148174134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2148174134
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3824343444
Short name T221
Test name
Test status
Simulation time 601584802819 ps
CPU time 1031.23 seconds
Started Aug 05 06:11:09 PM PDT 24
Finished Aug 05 06:28:20 PM PDT 24
Peak memory 201592 kb
Host smart-a331bec4-2a7f-45ee-b2b8-bdd99c48ff99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824343444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3824343444
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3098500653
Short name T120
Test name
Test status
Simulation time 29001788302 ps
CPU time 32.5 seconds
Started Aug 05 06:09:47 PM PDT 24
Finished Aug 05 06:10:19 PM PDT 24
Peak memory 201476 kb
Host smart-73d296c8-4283-45cd-bab5-5c65e2285942
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098500653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3098500653
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1622555378
Short name T39
Test name
Test status
Simulation time 332967531209 ps
CPU time 420.08 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:17:57 PM PDT 24
Peak memory 218204 kb
Host smart-c28ca41f-ada2-4f3e-a02b-997ea78970b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622555378 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1622555378
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3733424520
Short name T164
Test name
Test status
Simulation time 532024129205 ps
CPU time 341.8 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:16:57 PM PDT 24
Peak memory 201464 kb
Host smart-71ffce94-1ebb-4191-b2b6-a6acb7f8b395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733424520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3733424520
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2838572331
Short name T150
Test name
Test status
Simulation time 331381597233 ps
CPU time 63.55 seconds
Started Aug 05 06:13:30 PM PDT 24
Finished Aug 05 06:14:33 PM PDT 24
Peak memory 201480 kb
Host smart-2bfcf964-ca95-4ee2-b20f-0e1da38dc1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838572331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2838572331
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3927990977
Short name T193
Test name
Test status
Simulation time 572402142124 ps
CPU time 102.59 seconds
Started Aug 05 06:12:13 PM PDT 24
Finished Aug 05 06:13:55 PM PDT 24
Peak memory 201460 kb
Host smart-6c6d82e7-c309-49da-91f3-ee699c3bdef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927990977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3927990977
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2917052662
Short name T36
Test name
Test status
Simulation time 331991540392 ps
CPU time 770.35 seconds
Started Aug 05 06:11:37 PM PDT 24
Finished Aug 05 06:24:27 PM PDT 24
Peak memory 201460 kb
Host smart-1ffe204b-4e4f-4064-b0ef-5b012c2f0a7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917052662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2917052662
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1438805645
Short name T285
Test name
Test status
Simulation time 385080905742 ps
CPU time 891.09 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:25:18 PM PDT 24
Peak memory 201448 kb
Host smart-1bbf0b39-2716-4797-9393-487ca96d5baf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438805645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1438805645
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.4180221466
Short name T250
Test name
Test status
Simulation time 559155632057 ps
CPU time 1149.16 seconds
Started Aug 05 06:11:50 PM PDT 24
Finished Aug 05 06:31:00 PM PDT 24
Peak memory 201436 kb
Host smart-548f0f05-0ac8-409a-a88a-4aad7815087c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180221466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.4180221466
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.381057359
Short name T246
Test name
Test status
Simulation time 590534335703 ps
CPU time 1166.03 seconds
Started Aug 05 06:13:45 PM PDT 24
Finished Aug 05 06:33:11 PM PDT 24
Peak memory 211652 kb
Host smart-9f2d3e18-6ca1-4957-8794-a066aac978e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381057359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
381057359
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.671298369
Short name T224
Test name
Test status
Simulation time 353234337826 ps
CPU time 394.19 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:17:51 PM PDT 24
Peak memory 201436 kb
Host smart-07f44a1b-eb5e-450a-9a52-a083f4704c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671298369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.671298369
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2185718581
Short name T269
Test name
Test status
Simulation time 506010126092 ps
CPU time 1193.56 seconds
Started Aug 05 06:11:30 PM PDT 24
Finished Aug 05 06:31:24 PM PDT 24
Peak memory 201456 kb
Host smart-1cd0df7b-6e71-4def-b81d-94c383a641c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185718581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2185718581
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2807832148
Short name T230
Test name
Test status
Simulation time 703323630142 ps
CPU time 431.68 seconds
Started Aug 05 06:11:52 PM PDT 24
Finished Aug 05 06:19:03 PM PDT 24
Peak memory 201472 kb
Host smart-b7dc2b65-e009-4f9c-9c14-3e020507fad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807832148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2807832148
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2159783702
Short name T178
Test name
Test status
Simulation time 431667331 ps
CPU time 1.32 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:10:29 PM PDT 24
Peak memory 201232 kb
Host smart-debd8ffa-7ca2-42b2-9e8b-a57df5ede354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159783702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2159783702
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4168324388
Short name T75
Test name
Test status
Simulation time 4070968550 ps
CPU time 5.9 seconds
Started Aug 05 06:10:02 PM PDT 24
Finished Aug 05 06:10:08 PM PDT 24
Peak memory 201608 kb
Host smart-d32372f5-1398-4b1b-8820-6a711d344f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168324388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.4168324388
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.28973243
Short name T149
Test name
Test status
Simulation time 330950897639 ps
CPU time 202.41 seconds
Started Aug 05 06:11:24 PM PDT 24
Finished Aug 05 06:14:47 PM PDT 24
Peak memory 201468 kb
Host smart-d4db6d55-2078-4a9f-ac98-64302e045d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28973243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.28973243
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2101297752
Short name T300
Test name
Test status
Simulation time 456738868224 ps
CPU time 1022.49 seconds
Started Aug 05 06:13:32 PM PDT 24
Finished Aug 05 06:30:35 PM PDT 24
Peak memory 201464 kb
Host smart-a9d46b70-8e1e-4223-b1a5-27442900b571
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101297752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2101297752
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1116238705
Short name T222
Test name
Test status
Simulation time 547204999642 ps
CPU time 582.73 seconds
Started Aug 05 06:14:00 PM PDT 24
Finished Aug 05 06:23:43 PM PDT 24
Peak memory 201396 kb
Host smart-9ee74629-022d-4007-997d-dbc2a5a29b4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116238705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1116238705
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.10695312
Short name T266
Test name
Test status
Simulation time 364080988528 ps
CPU time 762.35 seconds
Started Aug 05 06:10:21 PM PDT 24
Finished Aug 05 06:23:04 PM PDT 24
Peak memory 201476 kb
Host smart-92fc5a23-97ed-4146-97cc-3e50d6bd4bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10695312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.10695312
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1501492525
Short name T305
Test name
Test status
Simulation time 169256903055 ps
CPU time 334.74 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:16:30 PM PDT 24
Peak memory 201456 kb
Host smart-476d00fa-fc96-4e67-ad64-97d54142cfa2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501492525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1501492525
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.280543574
Short name T235
Test name
Test status
Simulation time 452105746586 ps
CPU time 277.34 seconds
Started Aug 05 06:11:11 PM PDT 24
Finished Aug 05 06:15:48 PM PDT 24
Peak memory 210156 kb
Host smart-9e53f6d4-8cca-40f7-81f2-9a3eda5d972b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280543574 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.280543574
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.134572439
Short name T311
Test name
Test status
Simulation time 489813581270 ps
CPU time 1134.08 seconds
Started Aug 05 06:10:42 PM PDT 24
Finished Aug 05 06:29:37 PM PDT 24
Peak memory 201420 kb
Host smart-c73e6ca0-2a07-4b1e-8466-2e5b57677fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134572439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.134572439
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1265610184
Short name T182
Test name
Test status
Simulation time 352683583994 ps
CPU time 98.97 seconds
Started Aug 05 06:10:26 PM PDT 24
Finished Aug 05 06:12:06 PM PDT 24
Peak memory 201456 kb
Host smart-2abd2aa0-4ddc-4352-97b0-90b5f7f53e15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265610184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1265610184
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.412592782
Short name T327
Test name
Test status
Simulation time 486953114329 ps
CPU time 1090.47 seconds
Started Aug 05 06:11:09 PM PDT 24
Finished Aug 05 06:29:19 PM PDT 24
Peak memory 201448 kb
Host smart-9f2ad824-f915-416c-a730-22727f6768f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412592782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.412592782
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.335603333
Short name T16
Test name
Test status
Simulation time 386041593015 ps
CPU time 391.42 seconds
Started Aug 05 06:13:02 PM PDT 24
Finished Aug 05 06:19:33 PM PDT 24
Peak memory 210136 kb
Host smart-8db9475b-310d-4618-a646-6fdd1c3ec039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335603333 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.335603333
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.4261239916
Short name T310
Test name
Test status
Simulation time 346618187838 ps
CPU time 412.59 seconds
Started Aug 05 06:11:37 PM PDT 24
Finished Aug 05 06:18:30 PM PDT 24
Peak memory 201468 kb
Host smart-d7aa9fa2-d6ae-4e69-9600-dfb3c7acfab0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261239916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.4261239916
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2821533976
Short name T122
Test name
Test status
Simulation time 533447701 ps
CPU time 1.46 seconds
Started Aug 05 06:10:26 PM PDT 24
Finished Aug 05 06:10:27 PM PDT 24
Peak memory 201360 kb
Host smart-7b8404fc-be86-41bf-8bf5-29179c91cb30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821533976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2821533976
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.248264471
Short name T106
Test name
Test status
Simulation time 393473363865 ps
CPU time 174.33 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:14:14 PM PDT 24
Peak memory 201472 kb
Host smart-7f7c9559-3081-4079-ac44-b3918ca03997
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248264471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.248264471
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.934798497
Short name T232
Test name
Test status
Simulation time 501572606099 ps
CPU time 1240.55 seconds
Started Aug 05 06:11:10 PM PDT 24
Finished Aug 05 06:31:51 PM PDT 24
Peak memory 201456 kb
Host smart-91646dcf-6048-484b-85d9-bdcdef2c4bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934798497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.934798497
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1897186148
Short name T234
Test name
Test status
Simulation time 541716496714 ps
CPU time 423.77 seconds
Started Aug 05 06:11:23 PM PDT 24
Finished Aug 05 06:18:27 PM PDT 24
Peak memory 201464 kb
Host smart-b77bcd1b-71ff-4653-a72c-6851a2a7154b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897186148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1897186148
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.660251524
Short name T196
Test name
Test status
Simulation time 536354832233 ps
CPU time 300.41 seconds
Started Aug 05 06:13:35 PM PDT 24
Finished Aug 05 06:18:36 PM PDT 24
Peak memory 201500 kb
Host smart-259bba57-95bc-4308-a725-4e8913fc253a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660251524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.660251524
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1194401585
Short name T259
Test name
Test status
Simulation time 166738470208 ps
CPU time 321.97 seconds
Started Aug 05 06:10:20 PM PDT 24
Finished Aug 05 06:15:42 PM PDT 24
Peak memory 201440 kb
Host smart-72585677-8930-4c95-8373-b18bb83e9166
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194401585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1194401585
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.461079772
Short name T284
Test name
Test status
Simulation time 523618348638 ps
CPU time 1189.75 seconds
Started Aug 05 06:12:37 PM PDT 24
Finished Aug 05 06:32:27 PM PDT 24
Peak memory 201440 kb
Host smart-5caa0420-1662-4d0b-bd0d-cfb4b29c0086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461079772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
461079772
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.511659553
Short name T273
Test name
Test status
Simulation time 154693440408 ps
CPU time 229.24 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:14:47 PM PDT 24
Peak memory 210192 kb
Host smart-f7fceb4f-4143-4c48-876b-cacb823b6cb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511659553 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.511659553
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1933320353
Short name T197
Test name
Test status
Simulation time 536875052998 ps
CPU time 1223.53 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:31:18 PM PDT 24
Peak memory 201448 kb
Host smart-9e68bf11-99f2-4913-82bc-c28923954795
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933320353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1933320353
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.105624396
Short name T326
Test name
Test status
Simulation time 384955093735 ps
CPU time 225.63 seconds
Started Aug 05 06:10:59 PM PDT 24
Finished Aug 05 06:14:45 PM PDT 24
Peak memory 201476 kb
Host smart-8ed6188c-46e7-4426-b7a6-b1c4d34b9bab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105624396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.105624396
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.842967168
Short name T95
Test name
Test status
Simulation time 329630586437 ps
CPU time 174.15 seconds
Started Aug 05 06:11:12 PM PDT 24
Finished Aug 05 06:14:06 PM PDT 24
Peak memory 201508 kb
Host smart-5f33673f-f33e-44d0-b064-620cc99f2ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842967168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.842967168
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2069472895
Short name T315
Test name
Test status
Simulation time 517955749254 ps
CPU time 758.67 seconds
Started Aug 05 06:12:37 PM PDT 24
Finished Aug 05 06:25:15 PM PDT 24
Peak memory 201436 kb
Host smart-75f8955b-6475-40a9-b7a1-7ce0b02fcd12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069472895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2069472895
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.984416034
Short name T297
Test name
Test status
Simulation time 503218872280 ps
CPU time 336.25 seconds
Started Aug 05 06:14:18 PM PDT 24
Finished Aug 05 06:19:55 PM PDT 24
Peak memory 201444 kb
Host smart-794b362c-d97d-494f-a07c-8046c73fc16d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984416034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.984416034
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3801328043
Short name T209
Test name
Test status
Simulation time 659949192387 ps
CPU time 1894.19 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:42:30 PM PDT 24
Peak memory 212668 kb
Host smart-ad3eb54e-cb68-4668-a494-6b541ac0b1c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801328043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3801328043
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2403790241
Short name T749
Test name
Test status
Simulation time 511887282538 ps
CPU time 395.17 seconds
Started Aug 05 06:11:49 PM PDT 24
Finished Aug 05 06:18:25 PM PDT 24
Peak memory 210168 kb
Host smart-4ea2e33b-420d-4a03-b2a8-c2c9aa5aff3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403790241 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2403790241
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3028645925
Short name T171
Test name
Test status
Simulation time 499366931457 ps
CPU time 286.49 seconds
Started Aug 05 06:12:06 PM PDT 24
Finished Aug 05 06:16:52 PM PDT 24
Peak memory 201464 kb
Host smart-c424e64e-45b0-4a91-b88a-f23966bb86d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028645925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3028645925
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2941279735
Short name T249
Test name
Test status
Simulation time 484793666855 ps
CPU time 558.48 seconds
Started Aug 05 06:13:38 PM PDT 24
Finished Aug 05 06:22:57 PM PDT 24
Peak memory 201444 kb
Host smart-54b67c7c-9edd-4902-aa6a-fbbadee4a558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941279735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2941279735
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1327360083
Short name T114
Test name
Test status
Simulation time 493114468182 ps
CPU time 531.89 seconds
Started Aug 05 06:11:03 PM PDT 24
Finished Aug 05 06:19:55 PM PDT 24
Peak memory 201528 kb
Host smart-78110903-544f-4c43-a64a-40cf3792abf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327360083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1327360083
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1585780168
Short name T233
Test name
Test status
Simulation time 503042962879 ps
CPU time 517.64 seconds
Started Aug 05 06:11:05 PM PDT 24
Finished Aug 05 06:19:43 PM PDT 24
Peak memory 201348 kb
Host smart-6585dd96-fbd7-4b7f-92db-089f15abf39e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585780168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1585780168
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2883944625
Short name T158
Test name
Test status
Simulation time 489994928699 ps
CPU time 166.53 seconds
Started Aug 05 06:10:26 PM PDT 24
Finished Aug 05 06:13:13 PM PDT 24
Peak memory 201456 kb
Host smart-ec8421e0-b349-4cf3-b08c-7fc1ddb92939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883944625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2883944625
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.64762471
Short name T320
Test name
Test status
Simulation time 336839222341 ps
CPU time 742.53 seconds
Started Aug 05 06:12:25 PM PDT 24
Finished Aug 05 06:24:48 PM PDT 24
Peak memory 201492 kb
Host smart-e10cd127-493b-46a1-b03b-53885d22b01f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64762471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gatin
g.64762471
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.849879690
Short name T212
Test name
Test status
Simulation time 111880997554 ps
CPU time 396.1 seconds
Started Aug 05 06:13:12 PM PDT 24
Finished Aug 05 06:19:49 PM PDT 24
Peak memory 201900 kb
Host smart-40e60551-ccea-4047-9101-9e2bf34f45d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849879690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.849879690
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.794908585
Short name T308
Test name
Test status
Simulation time 342433819190 ps
CPU time 728.57 seconds
Started Aug 05 06:13:46 PM PDT 24
Finished Aug 05 06:25:54 PM PDT 24
Peak memory 201328 kb
Host smart-397fce17-b0a5-4399-86a4-87e6ee1a957c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794908585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.794908585
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2834681079
Short name T163
Test name
Test status
Simulation time 333282305976 ps
CPU time 780.25 seconds
Started Aug 05 06:13:50 PM PDT 24
Finished Aug 05 06:26:51 PM PDT 24
Peak memory 201444 kb
Host smart-fd5d44e7-f950-48ea-8b7c-bd66804f435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834681079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2834681079
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.500471979
Short name T299
Test name
Test status
Simulation time 493217900003 ps
CPU time 182.29 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:13:56 PM PDT 24
Peak memory 201460 kb
Host smart-ec04c1d5-c3a7-4769-8a26-07726fc151fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500471979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.500471979
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2927794174
Short name T69
Test name
Test status
Simulation time 459072444 ps
CPU time 2.4 seconds
Started Aug 05 06:09:47 PM PDT 24
Finished Aug 05 06:09:49 PM PDT 24
Peak memory 201532 kb
Host smart-519bfa9f-5347-48a5-9419-0a4f25cdcbdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927794174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2927794174
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3879923571
Short name T54
Test name
Test status
Simulation time 4543040406 ps
CPU time 4.15 seconds
Started Aug 05 06:09:38 PM PDT 24
Finished Aug 05 06:09:42 PM PDT 24
Peak memory 201672 kb
Host smart-97d33687-1dff-4116-b5cf-2d54a6f8f4d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879923571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3879923571
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3545195574
Short name T848
Test name
Test status
Simulation time 8423792981 ps
CPU time 6.08 seconds
Started Aug 05 06:09:59 PM PDT 24
Finished Aug 05 06:10:05 PM PDT 24
Peak memory 201660 kb
Host smart-20c021fa-acb5-4ce2-b8dc-bf02d2b80792
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545195574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3545195574
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2303236908
Short name T148
Test name
Test status
Simulation time 490511067867 ps
CPU time 546.98 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:19:35 PM PDT 24
Peak memory 201380 kb
Host smart-6e11e3ff-5346-4b2f-bc0e-a7ddb8c5bfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303236908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2303236908
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1702849449
Short name T732
Test name
Test status
Simulation time 651392668185 ps
CPU time 725.09 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:23:00 PM PDT 24
Peak memory 210028 kb
Host smart-ac65b3ce-067b-4ab3-b5b5-d320bf90ee18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702849449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1702849449
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.726412877
Short name T236
Test name
Test status
Simulation time 529918366770 ps
CPU time 243.82 seconds
Started Aug 05 06:11:08 PM PDT 24
Finished Aug 05 06:15:12 PM PDT 24
Peak memory 201404 kb
Host smart-7ce4f168-0fb1-47f2-af0f-261d4325c58f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726412877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.726412877
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2563989365
Short name T213
Test name
Test status
Simulation time 116593636464 ps
CPU time 310.78 seconds
Started Aug 05 06:11:11 PM PDT 24
Finished Aug 05 06:16:21 PM PDT 24
Peak memory 201760 kb
Host smart-b6573c6a-0adc-4c14-a5eb-f0ee387ae777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563989365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2563989365
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3639463806
Short name T202
Test name
Test status
Simulation time 147278630245 ps
CPU time 186.97 seconds
Started Aug 05 06:10:18 PM PDT 24
Finished Aug 05 06:13:26 PM PDT 24
Peak memory 210180 kb
Host smart-6cccb2e9-428d-4cf4-9c0a-584d154063dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639463806 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3639463806
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2288932537
Short name T257
Test name
Test status
Simulation time 177704198204 ps
CPU time 95.99 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:12:51 PM PDT 24
Peak memory 201448 kb
Host smart-8a046dce-1a6c-4f29-9dca-c57c37a329e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288932537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2288932537
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2348562013
Short name T191
Test name
Test status
Simulation time 329966074844 ps
CPU time 408.83 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:18:04 PM PDT 24
Peak memory 201420 kb
Host smart-08f0f395-5dd9-46ab-8766-1d8cbeddc27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348562013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2348562013
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4148533584
Short name T216
Test name
Test status
Simulation time 85392791760 ps
CPU time 297.18 seconds
Started Aug 05 06:11:25 PM PDT 24
Finished Aug 05 06:16:23 PM PDT 24
Peak memory 201852 kb
Host smart-088a1051-8272-46c5-9ce0-a797e384d47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148533584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4148533584
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.983208925
Short name T357
Test name
Test status
Simulation time 111636799740 ps
CPU time 554.83 seconds
Started Aug 05 06:11:47 PM PDT 24
Finished Aug 05 06:21:01 PM PDT 24
Peak memory 201824 kb
Host smart-ad4fb773-9c47-4835-b7b0-2fefbbed9cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983208925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.983208925
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2433568219
Short name T345
Test name
Test status
Simulation time 188769996083 ps
CPU time 224.02 seconds
Started Aug 05 06:11:56 PM PDT 24
Finished Aug 05 06:15:40 PM PDT 24
Peak memory 201448 kb
Host smart-75231032-2d2f-4121-93a6-94dea0a9425a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433568219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2433568219
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2858307312
Short name T282
Test name
Test status
Simulation time 177489809248 ps
CPU time 369.6 seconds
Started Aug 05 06:12:05 PM PDT 24
Finished Aug 05 06:18:15 PM PDT 24
Peak memory 201472 kb
Host smart-0e5c68cb-4177-477d-b0dc-186809159a28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858307312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2858307312
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.254531967
Short name T304
Test name
Test status
Simulation time 510470365426 ps
CPU time 645.17 seconds
Started Aug 05 06:10:22 PM PDT 24
Finished Aug 05 06:21:08 PM PDT 24
Peak memory 201536 kb
Host smart-85083823-7f6d-44c3-ba3a-a22c3b680845
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254531967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.254531967
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2261680527
Short name T162
Test name
Test status
Simulation time 553881954857 ps
CPU time 1098.91 seconds
Started Aug 05 06:12:55 PM PDT 24
Finished Aug 05 06:31:14 PM PDT 24
Peak memory 201424 kb
Host smart-bf07458f-d084-4a87-a442-b5d6073ff4c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261680527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2261680527
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1481338594
Short name T45
Test name
Test status
Simulation time 222317432533 ps
CPU time 452 seconds
Started Aug 05 06:13:55 PM PDT 24
Finished Aug 05 06:21:27 PM PDT 24
Peak memory 201500 kb
Host smart-44509313-b18a-4f37-abaa-28df681488dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481338594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1481338594
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1957959116
Short name T876
Test name
Test status
Simulation time 910754551 ps
CPU time 4.2 seconds
Started Aug 05 06:09:55 PM PDT 24
Finished Aug 05 06:10:00 PM PDT 24
Peak memory 201508 kb
Host smart-50ba7cde-d5de-4dab-a4dc-79cf4ba8b87c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957959116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1957959116
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3061536875
Short name T878
Test name
Test status
Simulation time 1052684205 ps
CPU time 3.07 seconds
Started Aug 05 06:09:52 PM PDT 24
Finished Aug 05 06:09:55 PM PDT 24
Peak memory 201356 kb
Host smart-980f4219-ff61-4a57-ac8d-5995f4b83241
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061536875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3061536875
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3850033859
Short name T904
Test name
Test status
Simulation time 497290736 ps
CPU time 1.08 seconds
Started Aug 05 06:10:01 PM PDT 24
Finished Aug 05 06:10:02 PM PDT 24
Peak memory 201512 kb
Host smart-d5c5f81d-82ea-4944-94f1-8f7e97657e0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850033859 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3850033859
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3857924945
Short name T810
Test name
Test status
Simulation time 410719869 ps
CPU time 1.19 seconds
Started Aug 05 06:09:54 PM PDT 24
Finished Aug 05 06:09:56 PM PDT 24
Peak memory 201376 kb
Host smart-63e31fd3-5f15-4616-931f-94de66537711
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857924945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3857924945
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1874414444
Short name T802
Test name
Test status
Simulation time 320353263 ps
CPU time 1.45 seconds
Started Aug 05 06:09:48 PM PDT 24
Finished Aug 05 06:09:49 PM PDT 24
Peak memory 201384 kb
Host smart-a56e034a-9309-49de-98b1-2b5ffa446679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874414444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1874414444
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1647017040
Short name T875
Test name
Test status
Simulation time 4367069245 ps
CPU time 17.03 seconds
Started Aug 05 06:09:43 PM PDT 24
Finished Aug 05 06:10:00 PM PDT 24
Peak memory 201600 kb
Host smart-fb60abd2-dcc5-45f1-8d52-e64a5c7269b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647017040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1647017040
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2907298505
Short name T890
Test name
Test status
Simulation time 622028154 ps
CPU time 1.8 seconds
Started Aug 05 06:09:43 PM PDT 24
Finished Aug 05 06:09:45 PM PDT 24
Peak memory 217800 kb
Host smart-29a75c34-58d8-4488-8d3f-0fd7a05f7fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907298505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2907298505
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.81977747
Short name T885
Test name
Test status
Simulation time 1284966836 ps
CPU time 2.89 seconds
Started Aug 05 06:09:52 PM PDT 24
Finished Aug 05 06:09:55 PM PDT 24
Peak memory 201528 kb
Host smart-811296bb-70c2-4c0f-98d7-7453ce028abf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81977747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasi
ng.81977747
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2650707346
Short name T51
Test name
Test status
Simulation time 51767492152 ps
CPU time 177.81 seconds
Started Aug 05 06:09:57 PM PDT 24
Finished Aug 05 06:12:55 PM PDT 24
Peak memory 201560 kb
Host smart-ae8dc318-9215-4547-a010-a632181c85ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650707346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2650707346
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2496405087
Short name T870
Test name
Test status
Simulation time 1342625112 ps
CPU time 1.59 seconds
Started Aug 05 06:09:36 PM PDT 24
Finished Aug 05 06:09:37 PM PDT 24
Peak memory 201312 kb
Host smart-96f9c071-c75a-4e7d-8e63-e9d606cb549d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496405087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2496405087
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3326706546
Short name T830
Test name
Test status
Simulation time 594626672 ps
CPU time 1.34 seconds
Started Aug 05 06:09:48 PM PDT 24
Finished Aug 05 06:09:50 PM PDT 24
Peak memory 201460 kb
Host smart-2bc28048-a7fd-4ff2-afd3-ba466d7496cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326706546 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3326706546
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3443730773
Short name T126
Test name
Test status
Simulation time 410454817 ps
CPU time 1.19 seconds
Started Aug 05 06:09:48 PM PDT 24
Finished Aug 05 06:09:49 PM PDT 24
Peak memory 201380 kb
Host smart-75cc10d3-3a47-4a08-820d-196bef65ccf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443730773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3443730773
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3904988698
Short name T811
Test name
Test status
Simulation time 400083339 ps
CPU time 1.06 seconds
Started Aug 05 06:09:51 PM PDT 24
Finished Aug 05 06:09:52 PM PDT 24
Peak memory 201364 kb
Host smart-6b8d1c31-3ea4-4678-9a15-6b64c1d10689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904988698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3904988698
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1199999889
Short name T855
Test name
Test status
Simulation time 4405832204 ps
CPU time 13.54 seconds
Started Aug 05 06:09:53 PM PDT 24
Finished Aug 05 06:10:06 PM PDT 24
Peak memory 201616 kb
Host smart-60f12580-9362-473f-9472-5256adebc06f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199999889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1199999889
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1235651169
Short name T832
Test name
Test status
Simulation time 8638054874 ps
CPU time 6.17 seconds
Started Aug 05 06:09:38 PM PDT 24
Finished Aug 05 06:09:44 PM PDT 24
Peak memory 201592 kb
Host smart-37c7eaa3-7469-4c4d-b0b1-10ff4ebce949
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235651169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1235651169
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1870767523
Short name T902
Test name
Test status
Simulation time 422231801 ps
CPU time 1.79 seconds
Started Aug 05 06:10:05 PM PDT 24
Finished Aug 05 06:10:07 PM PDT 24
Peak memory 201476 kb
Host smart-79727659-07d6-4787-8f76-b3c6c6ef2f4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870767523 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1870767523
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.836743796
Short name T805
Test name
Test status
Simulation time 372391777 ps
CPU time 1.04 seconds
Started Aug 05 06:10:15 PM PDT 24
Finished Aug 05 06:10:17 PM PDT 24
Peak memory 201544 kb
Host smart-b5581cff-5369-4e55-af0c-3ac706e86cb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836743796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.836743796
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.269984332
Short name T882
Test name
Test status
Simulation time 5214165904 ps
CPU time 2.88 seconds
Started Aug 05 06:10:01 PM PDT 24
Finished Aug 05 06:10:04 PM PDT 24
Peak memory 201628 kb
Host smart-4923f651-4982-48a5-982d-dac4c284af9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269984332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.269984332
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2373555326
Short name T65
Test name
Test status
Simulation time 344597256 ps
CPU time 2.4 seconds
Started Aug 05 06:10:01 PM PDT 24
Finished Aug 05 06:10:04 PM PDT 24
Peak memory 201500 kb
Host smart-65793429-2b80-4a9e-a57e-dffe404ccf87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373555326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2373555326
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.957084739
Short name T89
Test name
Test status
Simulation time 370338179 ps
CPU time 1.37 seconds
Started Aug 05 06:10:21 PM PDT 24
Finished Aug 05 06:10:23 PM PDT 24
Peak memory 201452 kb
Host smart-a3d58306-a268-46e5-a246-fd6632c7ffbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957084739 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.957084739
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.38460035
Short name T121
Test name
Test status
Simulation time 386822418 ps
CPU time 1.04 seconds
Started Aug 05 06:10:10 PM PDT 24
Finished Aug 05 06:10:12 PM PDT 24
Peak memory 201372 kb
Host smart-5257793e-e846-4005-a293-e58409907500
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38460035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.38460035
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3329580549
Short name T906
Test name
Test status
Simulation time 557193019 ps
CPU time 0.69 seconds
Started Aug 05 06:10:02 PM PDT 24
Finished Aug 05 06:10:03 PM PDT 24
Peak memory 201348 kb
Host smart-81f31de1-1d5d-4797-b677-f91c1f652c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329580549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3329580549
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.97777036
Short name T898
Test name
Test status
Simulation time 2683891408 ps
CPU time 10.32 seconds
Started Aug 05 06:10:00 PM PDT 24
Finished Aug 05 06:10:10 PM PDT 24
Peak memory 201440 kb
Host smart-94695a2b-3fde-4279-83fc-4f9da14cb046
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97777036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ct
rl_same_csr_outstanding.97777036
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4250059138
Short name T880
Test name
Test status
Simulation time 626920532 ps
CPU time 2.87 seconds
Started Aug 05 06:10:15 PM PDT 24
Finished Aug 05 06:10:18 PM PDT 24
Peak memory 201580 kb
Host smart-f12e1289-5700-45c3-9ee8-691ac062db3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250059138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.4250059138
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3746309835
Short name T816
Test name
Test status
Simulation time 4732790081 ps
CPU time 12.19 seconds
Started Aug 05 06:10:01 PM PDT 24
Finished Aug 05 06:10:13 PM PDT 24
Peak memory 201664 kb
Host smart-0ef599da-a8ba-4888-b017-4352e6b174f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746309835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3746309835
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.808234401
Short name T835
Test name
Test status
Simulation time 593981573 ps
CPU time 1.33 seconds
Started Aug 05 06:10:21 PM PDT 24
Finished Aug 05 06:10:22 PM PDT 24
Peak memory 201500 kb
Host smart-7287ff9b-532c-4a26-b80c-1ba87cd18118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808234401 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.808234401
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.858258875
Short name T843
Test name
Test status
Simulation time 370197872 ps
CPU time 1.58 seconds
Started Aug 05 06:10:16 PM PDT 24
Finished Aug 05 06:10:17 PM PDT 24
Peak memory 201368 kb
Host smart-55c754cd-1d75-474e-9535-dfdbf6787ed7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858258875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.858258875
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3205711071
Short name T828
Test name
Test status
Simulation time 417716441 ps
CPU time 0.79 seconds
Started Aug 05 06:10:14 PM PDT 24
Finished Aug 05 06:10:15 PM PDT 24
Peak memory 201336 kb
Host smart-a9f5ef90-85c0-42ac-91ac-765b97de39f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205711071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3205711071
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4091995726
Short name T53
Test name
Test status
Simulation time 3702771253 ps
CPU time 18.38 seconds
Started Aug 05 06:09:53 PM PDT 24
Finished Aug 05 06:10:11 PM PDT 24
Peak memory 201636 kb
Host smart-28e4e03f-9836-4bd1-ad36-5b2961a64f72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091995726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.4091995726
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.145898766
Short name T56
Test name
Test status
Simulation time 8059147684 ps
CPU time 15.97 seconds
Started Aug 05 06:10:01 PM PDT 24
Finished Aug 05 06:10:17 PM PDT 24
Peak memory 201652 kb
Host smart-f3bd0378-9709-4a23-8820-8c276773e334
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145898766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.145898766
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3946990897
Short name T812
Test name
Test status
Simulation time 436609843 ps
CPU time 1.92 seconds
Started Aug 05 06:10:16 PM PDT 24
Finished Aug 05 06:10:18 PM PDT 24
Peak memory 201476 kb
Host smart-883c2254-aac9-42b9-aec8-59970c7237da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946990897 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3946990897
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2348760978
Short name T903
Test name
Test status
Simulation time 582844099 ps
CPU time 0.96 seconds
Started Aug 05 06:10:03 PM PDT 24
Finished Aug 05 06:10:04 PM PDT 24
Peak memory 201356 kb
Host smart-814c2bcc-975a-4813-9ecf-8cefd33c6c45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348760978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2348760978
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1021160481
Short name T896
Test name
Test status
Simulation time 471924019 ps
CPU time 0.89 seconds
Started Aug 05 06:10:05 PM PDT 24
Finished Aug 05 06:10:06 PM PDT 24
Peak memory 201380 kb
Host smart-132320e3-ef9c-4e72-b839-25801a10d319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021160481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1021160481
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1526829066
Short name T134
Test name
Test status
Simulation time 4065794431 ps
CPU time 15.37 seconds
Started Aug 05 06:10:01 PM PDT 24
Finished Aug 05 06:10:16 PM PDT 24
Peak memory 201600 kb
Host smart-27d7bf6a-1e25-483d-8b6a-c899199de53f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526829066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1526829066
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1495048320
Short name T73
Test name
Test status
Simulation time 503206344 ps
CPU time 2.02 seconds
Started Aug 05 06:10:06 PM PDT 24
Finished Aug 05 06:10:08 PM PDT 24
Peak memory 201620 kb
Host smart-de6458d4-002f-44b3-b2aa-b4983a25d5bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495048320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1495048320
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1306815679
Short name T860
Test name
Test status
Simulation time 8201079673 ps
CPU time 19.72 seconds
Started Aug 05 06:10:04 PM PDT 24
Finished Aug 05 06:10:23 PM PDT 24
Peak memory 201644 kb
Host smart-4d24b782-6a5d-404f-ba36-d7688f70a73f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306815679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1306815679
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4172419418
Short name T893
Test name
Test status
Simulation time 530452194 ps
CPU time 2.22 seconds
Started Aug 05 06:10:02 PM PDT 24
Finished Aug 05 06:10:04 PM PDT 24
Peak memory 201476 kb
Host smart-b0c0afaa-39ff-475b-8f22-d9d04067822f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172419418 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.4172419418
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.737088533
Short name T849
Test name
Test status
Simulation time 346612790 ps
CPU time 1.6 seconds
Started Aug 05 06:10:05 PM PDT 24
Finished Aug 05 06:10:06 PM PDT 24
Peak memory 201352 kb
Host smart-326e13b5-222c-4622-a577-fb858847aa02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737088533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.737088533
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.447604737
Short name T901
Test name
Test status
Simulation time 415721623 ps
CPU time 0.88 seconds
Started Aug 05 06:10:21 PM PDT 24
Finished Aug 05 06:10:22 PM PDT 24
Peak memory 201368 kb
Host smart-7acda6ab-df82-4356-9369-b22951914fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447604737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.447604737
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.344823188
Short name T839
Test name
Test status
Simulation time 3939133699 ps
CPU time 5.42 seconds
Started Aug 05 06:10:05 PM PDT 24
Finished Aug 05 06:10:11 PM PDT 24
Peak memory 201472 kb
Host smart-fae9daab-fc7d-480f-9eab-b3e2fe303c6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344823188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.344823188
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2117619908
Short name T74
Test name
Test status
Simulation time 474139183 ps
CPU time 2.78 seconds
Started Aug 05 06:09:54 PM PDT 24
Finished Aug 05 06:09:56 PM PDT 24
Peak memory 201692 kb
Host smart-f5a2d77a-5d18-447b-b6f5-ca117fe54d97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117619908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2117619908
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.681043486
Short name T858
Test name
Test status
Simulation time 8475395375 ps
CPU time 12.43 seconds
Started Aug 05 06:10:02 PM PDT 24
Finished Aug 05 06:10:15 PM PDT 24
Peak memory 201664 kb
Host smart-263ec7ea-8896-4b1d-a351-53e2b6230456
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681043486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.681043486
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3258004066
Short name T910
Test name
Test status
Simulation time 365849906 ps
CPU time 1.6 seconds
Started Aug 05 06:10:03 PM PDT 24
Finished Aug 05 06:10:05 PM PDT 24
Peak memory 201528 kb
Host smart-d905c1c0-0863-4aa0-89b4-0ad983c2251f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258004066 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3258004066
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3658343703
Short name T861
Test name
Test status
Simulation time 528481407 ps
CPU time 2.16 seconds
Started Aug 05 06:10:09 PM PDT 24
Finished Aug 05 06:10:11 PM PDT 24
Peak memory 201336 kb
Host smart-7261f488-e0b1-4a92-86e8-83e68ef1500a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658343703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3658343703
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4198188307
Short name T820
Test name
Test status
Simulation time 325526867 ps
CPU time 0.81 seconds
Started Aug 05 06:10:10 PM PDT 24
Finished Aug 05 06:10:11 PM PDT 24
Peak memory 201344 kb
Host smart-14e4a49e-0311-4d04-b5ea-5c695f5493a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198188307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.4198188307
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3031921413
Short name T912
Test name
Test status
Simulation time 4951577293 ps
CPU time 6.52 seconds
Started Aug 05 06:10:02 PM PDT 24
Finished Aug 05 06:10:09 PM PDT 24
Peak memory 201600 kb
Host smart-d41e797d-768f-4a40-b3be-336159263c9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031921413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3031921413
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3617265666
Short name T844
Test name
Test status
Simulation time 341775427 ps
CPU time 1.34 seconds
Started Aug 05 06:10:04 PM PDT 24
Finished Aug 05 06:10:05 PM PDT 24
Peak memory 201652 kb
Host smart-61d0f924-12d9-4d84-9ea3-ac0052d36f21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617265666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3617265666
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1966615659
Short name T350
Test name
Test status
Simulation time 8674255701 ps
CPU time 19.4 seconds
Started Aug 05 06:10:06 PM PDT 24
Finished Aug 05 06:10:26 PM PDT 24
Peak memory 201564 kb
Host smart-c663f207-3b7a-46e0-afe3-bb5603febd67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966615659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1966615659
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3147696317
Short name T846
Test name
Test status
Simulation time 551081846 ps
CPU time 2.28 seconds
Started Aug 05 06:10:21 PM PDT 24
Finished Aug 05 06:10:24 PM PDT 24
Peak memory 201448 kb
Host smart-fc9d7185-48a4-4d2b-9aea-4978296404d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147696317 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3147696317
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.477762836
Short name T909
Test name
Test status
Simulation time 510426588 ps
CPU time 1.1 seconds
Started Aug 05 06:10:13 PM PDT 24
Finished Aug 05 06:10:14 PM PDT 24
Peak memory 201368 kb
Host smart-bc417ab0-5446-4234-81c6-b2043e245e1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477762836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.477762836
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1924298052
Short name T874
Test name
Test status
Simulation time 309446261 ps
CPU time 1.38 seconds
Started Aug 05 06:10:24 PM PDT 24
Finished Aug 05 06:10:26 PM PDT 24
Peak memory 201356 kb
Host smart-bbd7a495-5d9f-4979-beaa-90fe55ddaf21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924298052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1924298052
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2567806069
Short name T136
Test name
Test status
Simulation time 4902996690 ps
CPU time 3.57 seconds
Started Aug 05 06:10:01 PM PDT 24
Finished Aug 05 06:10:04 PM PDT 24
Peak memory 201632 kb
Host smart-d8313d84-3e7c-4c7b-8420-08e736c6936d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567806069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2567806069
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.4104958015
Short name T68
Test name
Test status
Simulation time 422337362 ps
CPU time 2.17 seconds
Started Aug 05 06:10:14 PM PDT 24
Finished Aug 05 06:10:17 PM PDT 24
Peak memory 201600 kb
Host smart-4b45dd69-aed3-45d1-b82d-ad5e61bbd152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104958015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.4104958015
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1977388258
Short name T871
Test name
Test status
Simulation time 4456539880 ps
CPU time 4.13 seconds
Started Aug 05 06:10:18 PM PDT 24
Finished Aug 05 06:10:22 PM PDT 24
Peak memory 201604 kb
Host smart-2b5cba88-8890-40cb-afd5-5599a1805535
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977388258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1977388258
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1549688314
Short name T90
Test name
Test status
Simulation time 492024368 ps
CPU time 2.19 seconds
Started Aug 05 06:10:36 PM PDT 24
Finished Aug 05 06:10:39 PM PDT 24
Peak memory 201528 kb
Host smart-15577197-84f9-49fd-953b-8ded2a5e280f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549688314 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1549688314
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2143968286
Short name T138
Test name
Test status
Simulation time 522075798 ps
CPU time 1.83 seconds
Started Aug 05 06:10:17 PM PDT 24
Finished Aug 05 06:10:19 PM PDT 24
Peak memory 201368 kb
Host smart-0ba6ccb7-7d6f-410f-a323-1a5abc31b6ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143968286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2143968286
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3839680631
Short name T817
Test name
Test status
Simulation time 321031750 ps
CPU time 0.81 seconds
Started Aug 05 06:10:17 PM PDT 24
Finished Aug 05 06:10:18 PM PDT 24
Peak memory 201356 kb
Host smart-7410b173-3ff3-4b31-8426-79473320993f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839680631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3839680631
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1346424405
Short name T864
Test name
Test status
Simulation time 4452514379 ps
CPU time 4.32 seconds
Started Aug 05 06:10:23 PM PDT 24
Finished Aug 05 06:10:28 PM PDT 24
Peak memory 201612 kb
Host smart-ebcc5c3a-1f4e-4f16-a6f0-e1ed995ce3cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346424405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1346424405
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2166648996
Short name T900
Test name
Test status
Simulation time 757611621 ps
CPU time 1.39 seconds
Started Aug 05 06:10:04 PM PDT 24
Finished Aug 05 06:10:05 PM PDT 24
Peak memory 201648 kb
Host smart-284ef429-81a1-41f6-84ae-f26276aee348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166648996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2166648996
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3720356371
Short name T841
Test name
Test status
Simulation time 8005518538 ps
CPU time 18.67 seconds
Started Aug 05 06:10:14 PM PDT 24
Finished Aug 05 06:10:33 PM PDT 24
Peak memory 201636 kb
Host smart-4af8e6a7-eb54-4b8e-a581-537d46ed45be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720356371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3720356371
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2994789535
Short name T63
Test name
Test status
Simulation time 551311770 ps
CPU time 2.21 seconds
Started Aug 05 06:10:25 PM PDT 24
Finished Aug 05 06:10:27 PM PDT 24
Peak memory 201476 kb
Host smart-57545838-70a2-4557-a4cb-abbb58c58b47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994789535 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2994789535
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3450563704
Short name T127
Test name
Test status
Simulation time 549033402 ps
CPU time 1.01 seconds
Started Aug 05 06:10:02 PM PDT 24
Finished Aug 05 06:10:03 PM PDT 24
Peak memory 201372 kb
Host smart-fe7eab2e-87df-40e2-9005-601c508ca502
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450563704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3450563704
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1688947451
Short name T806
Test name
Test status
Simulation time 550265431 ps
CPU time 0.85 seconds
Started Aug 05 06:10:04 PM PDT 24
Finished Aug 05 06:10:05 PM PDT 24
Peak memory 201352 kb
Host smart-47997bb2-e1d8-40bf-9d18-2051b8b196dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688947451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1688947451
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4255404861
Short name T135
Test name
Test status
Simulation time 2107523949 ps
CPU time 4.69 seconds
Started Aug 05 06:10:18 PM PDT 24
Finished Aug 05 06:10:22 PM PDT 24
Peak memory 201320 kb
Host smart-e1efe389-37f2-4fd5-bbe7-17b433907c12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255404861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.4255404861
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3250496991
Short name T886
Test name
Test status
Simulation time 461868574 ps
CPU time 2.75 seconds
Started Aug 05 06:10:10 PM PDT 24
Finished Aug 05 06:10:13 PM PDT 24
Peak memory 201652 kb
Host smart-9c27286d-593a-412a-8041-2344b04865c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250496991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3250496991
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3978673847
Short name T897
Test name
Test status
Simulation time 4438197577 ps
CPU time 8.25 seconds
Started Aug 05 06:10:20 PM PDT 24
Finished Aug 05 06:10:29 PM PDT 24
Peak memory 201644 kb
Host smart-75c4e0ad-6198-4bf1-b7fe-d2e515420af8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978673847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3978673847
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1212245535
Short name T57
Test name
Test status
Simulation time 538106749 ps
CPU time 1.58 seconds
Started Aug 05 06:10:11 PM PDT 24
Finished Aug 05 06:10:12 PM PDT 24
Peak memory 201476 kb
Host smart-136cd123-e7ed-4470-ad3c-dcd47de1caf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212245535 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1212245535
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2205625419
Short name T123
Test name
Test status
Simulation time 513717556 ps
CPU time 1.01 seconds
Started Aug 05 06:10:09 PM PDT 24
Finished Aug 05 06:10:10 PM PDT 24
Peak memory 201364 kb
Host smart-928f2958-fc8a-4f8f-96d7-8a935bffc679
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205625419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2205625419
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.909389293
Short name T800
Test name
Test status
Simulation time 373038704 ps
CPU time 0.77 seconds
Started Aug 05 06:10:21 PM PDT 24
Finished Aug 05 06:10:22 PM PDT 24
Peak memory 201380 kb
Host smart-1ceb9337-da96-4074-ba85-42aedba3af7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909389293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.909389293
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3142292851
Short name T868
Test name
Test status
Simulation time 5162214212 ps
CPU time 2.14 seconds
Started Aug 05 06:10:20 PM PDT 24
Finished Aug 05 06:10:23 PM PDT 24
Peak memory 201508 kb
Host smart-8e76e183-87c2-415e-b4ab-86d7ea8d50ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142292851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3142292851
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.928611522
Short name T847
Test name
Test status
Simulation time 418389042 ps
CPU time 3.31 seconds
Started Aug 05 06:10:25 PM PDT 24
Finished Aug 05 06:10:28 PM PDT 24
Peak memory 218032 kb
Host smart-d210bd78-a918-495c-b85e-8208e43285e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928611522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.928611522
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.398527674
Short name T71
Test name
Test status
Simulation time 4350021706 ps
CPU time 11.47 seconds
Started Aug 05 06:10:20 PM PDT 24
Finished Aug 05 06:10:32 PM PDT 24
Peak memory 201640 kb
Host smart-f781f4ca-61ca-4666-8eda-9807afd12496
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398527674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.398527674
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2733238410
Short name T125
Test name
Test status
Simulation time 1002486539 ps
CPU time 1.64 seconds
Started Aug 05 06:09:48 PM PDT 24
Finished Aug 05 06:09:54 PM PDT 24
Peak memory 201688 kb
Host smart-342d98d2-5685-4373-9ab2-f11b41fb7ccb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733238410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2733238410
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.844210697
Short name T129
Test name
Test status
Simulation time 8131143902 ps
CPU time 8.87 seconds
Started Aug 05 06:09:57 PM PDT 24
Finished Aug 05 06:10:06 PM PDT 24
Peak memory 201596 kb
Host smart-d5db9422-37c7-45e0-93eb-0cfd1977370f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844210697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.844210697
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3584115926
Short name T128
Test name
Test status
Simulation time 711695069 ps
CPU time 2.27 seconds
Started Aug 05 06:09:58 PM PDT 24
Finished Aug 05 06:10:01 PM PDT 24
Peak memory 201364 kb
Host smart-4fa69fc2-5ce6-4148-8677-1cfb11818dc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584115926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3584115926
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3271612615
Short name T70
Test name
Test status
Simulation time 509630006 ps
CPU time 2.01 seconds
Started Aug 05 06:09:59 PM PDT 24
Finished Aug 05 06:10:01 PM PDT 24
Peak memory 201448 kb
Host smart-70b6e59e-07e5-49ac-a504-04aed5681bf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271612615 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3271612615
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2893399650
Short name T913
Test name
Test status
Simulation time 431634409 ps
CPU time 1.05 seconds
Started Aug 05 06:09:48 PM PDT 24
Finished Aug 05 06:09:49 PM PDT 24
Peak memory 201360 kb
Host smart-db7bd435-9777-449f-aee9-af168b4584da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893399650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2893399650
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.56885725
Short name T818
Test name
Test status
Simulation time 313066683 ps
CPU time 0.95 seconds
Started Aug 05 06:09:53 PM PDT 24
Finished Aug 05 06:09:54 PM PDT 24
Peak memory 201376 kb
Host smart-b65dcaa4-bdc5-44c8-9fb1-01de1f21a6c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56885725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.56885725
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3831241932
Short name T838
Test name
Test status
Simulation time 572960546 ps
CPU time 1.44 seconds
Started Aug 05 06:09:49 PM PDT 24
Finished Aug 05 06:09:50 PM PDT 24
Peak memory 201684 kb
Host smart-f9ed6c22-3637-4476-a78e-c2c8fe0d8cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831241932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3831241932
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2007682229
Short name T72
Test name
Test status
Simulation time 9026309772 ps
CPU time 7.79 seconds
Started Aug 05 06:10:03 PM PDT 24
Finished Aug 05 06:10:11 PM PDT 24
Peak memory 201676 kb
Host smart-8d0412fc-ca84-4969-83f0-9f1e6a65d3f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007682229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2007682229
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3685405666
Short name T907
Test name
Test status
Simulation time 351486603 ps
CPU time 1 seconds
Started Aug 05 06:10:04 PM PDT 24
Finished Aug 05 06:10:05 PM PDT 24
Peak memory 201360 kb
Host smart-c63fe2a7-a74a-4f76-90b1-521445685878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685405666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3685405666
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1145565424
Short name T894
Test name
Test status
Simulation time 332147338 ps
CPU time 0.83 seconds
Started Aug 05 06:10:02 PM PDT 24
Finished Aug 05 06:10:03 PM PDT 24
Peak memory 201388 kb
Host smart-7f78f0b4-8ba4-4f86-a087-1481be48d541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145565424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1145565424
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3953277149
Short name T821
Test name
Test status
Simulation time 453824305 ps
CPU time 1.14 seconds
Started Aug 05 06:10:20 PM PDT 24
Finished Aug 05 06:10:21 PM PDT 24
Peak memory 201372 kb
Host smart-fc705835-0efb-4675-9ef4-b5cf150d3982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953277149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3953277149
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1156848075
Short name T826
Test name
Test status
Simulation time 299966866 ps
CPU time 1.3 seconds
Started Aug 05 06:10:04 PM PDT 24
Finished Aug 05 06:10:06 PM PDT 24
Peak memory 201376 kb
Host smart-04df0127-911b-4560-8a19-8a776190efd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156848075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1156848075
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.664846512
Short name T819
Test name
Test status
Simulation time 434030047 ps
CPU time 1.08 seconds
Started Aug 05 06:10:18 PM PDT 24
Finished Aug 05 06:10:20 PM PDT 24
Peak memory 201384 kb
Host smart-e2ae6f1d-7177-4427-84ea-8291642a36f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664846512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.664846512
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2843900231
Short name T857
Test name
Test status
Simulation time 529495587 ps
CPU time 1.8 seconds
Started Aug 05 06:10:04 PM PDT 24
Finished Aug 05 06:10:06 PM PDT 24
Peak memory 201220 kb
Host smart-051d9b4d-ff39-4123-bcf9-ab00d84b3f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843900231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2843900231
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2173597416
Short name T825
Test name
Test status
Simulation time 499054191 ps
CPU time 1.8 seconds
Started Aug 05 06:10:02 PM PDT 24
Finished Aug 05 06:10:04 PM PDT 24
Peak memory 201364 kb
Host smart-7464664c-4ee3-416c-b652-74911b3fc61c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173597416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2173597416
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3461582656
Short name T813
Test name
Test status
Simulation time 315495728 ps
CPU time 0.99 seconds
Started Aug 05 06:10:10 PM PDT 24
Finished Aug 05 06:10:12 PM PDT 24
Peak memory 201364 kb
Host smart-8aa20e12-d581-4b40-afb5-9d4ae95fe6ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461582656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3461582656
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1415547946
Short name T834
Test name
Test status
Simulation time 497559328 ps
CPU time 0.91 seconds
Started Aug 05 06:10:21 PM PDT 24
Finished Aug 05 06:10:22 PM PDT 24
Peak memory 201360 kb
Host smart-b2f4849c-92bf-42e6-b85b-b4a31cb80dba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415547946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1415547946
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1207513513
Short name T872
Test name
Test status
Simulation time 453349019 ps
CPU time 1.59 seconds
Started Aug 05 06:10:07 PM PDT 24
Finished Aug 05 06:10:08 PM PDT 24
Peak memory 201372 kb
Host smart-c9749bad-e49d-4f89-a29c-ecb96160c6fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207513513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1207513513
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3478813384
Short name T131
Test name
Test status
Simulation time 792300458 ps
CPU time 2.67 seconds
Started Aug 05 06:10:03 PM PDT 24
Finished Aug 05 06:10:06 PM PDT 24
Peak memory 201528 kb
Host smart-ed4838cd-8b5b-4c87-b5c3-17e0ab6b6a70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478813384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3478813384
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2606020223
Short name T139
Test name
Test status
Simulation time 53748138809 ps
CPU time 65.54 seconds
Started Aug 05 06:09:58 PM PDT 24
Finished Aug 05 06:11:03 PM PDT 24
Peak memory 201568 kb
Host smart-4b7a4de7-9186-4658-bb71-f69bacf37750
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606020223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2606020223
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2685242315
Short name T124
Test name
Test status
Simulation time 1345463899 ps
CPU time 1.55 seconds
Started Aug 05 06:09:55 PM PDT 24
Finished Aug 05 06:09:57 PM PDT 24
Peak memory 201368 kb
Host smart-7d028dcd-54ef-402d-8a14-5024dbbbff45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685242315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2685242315
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2618809930
Short name T851
Test name
Test status
Simulation time 549425849 ps
CPU time 1.01 seconds
Started Aug 05 06:09:49 PM PDT 24
Finished Aug 05 06:09:55 PM PDT 24
Peak memory 201484 kb
Host smart-484b2b27-426a-4111-8e6e-bf410ad22f61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618809930 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2618809930
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.757936118
Short name T853
Test name
Test status
Simulation time 618230706 ps
CPU time 0.8 seconds
Started Aug 05 06:09:58 PM PDT 24
Finished Aug 05 06:09:59 PM PDT 24
Peak memory 201360 kb
Host smart-673bae5c-8721-4652-a131-f78f2e31b7f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757936118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.757936118
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1040803793
Short name T899
Test name
Test status
Simulation time 385503090 ps
CPU time 0.88 seconds
Started Aug 05 06:09:47 PM PDT 24
Finished Aug 05 06:09:48 PM PDT 24
Peak memory 201364 kb
Host smart-d96068ef-a305-4bfc-9348-377cf35f1005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040803793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1040803793
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2917869863
Short name T836
Test name
Test status
Simulation time 1960413198 ps
CPU time 6.38 seconds
Started Aug 05 06:09:52 PM PDT 24
Finished Aug 05 06:09:58 PM PDT 24
Peak memory 201388 kb
Host smart-14239a01-5ba0-4077-ac7e-34bce3f31d54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917869863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2917869863
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.962566386
Short name T842
Test name
Test status
Simulation time 725195553 ps
CPU time 2.55 seconds
Started Aug 05 06:10:12 PM PDT 24
Finished Aug 05 06:10:15 PM PDT 24
Peak memory 209808 kb
Host smart-eb3d9396-f1e0-4470-b831-4cfd0aae0edc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962566386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.962566386
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.427400620
Short name T59
Test name
Test status
Simulation time 7815001854 ps
CPU time 4.86 seconds
Started Aug 05 06:09:54 PM PDT 24
Finished Aug 05 06:09:59 PM PDT 24
Peak memory 201616 kb
Host smart-6fa9191a-2ff3-4430-9f66-bf51f9152abb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427400620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.427400620
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4257036317
Short name T808
Test name
Test status
Simulation time 540825281 ps
CPU time 0.71 seconds
Started Aug 05 06:10:18 PM PDT 24
Finished Aug 05 06:10:19 PM PDT 24
Peak memory 201384 kb
Host smart-f284472a-7347-4463-b7e9-60914b2581de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257036317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.4257036317
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1435158622
Short name T815
Test name
Test status
Simulation time 278777873 ps
CPU time 1.26 seconds
Started Aug 05 06:10:25 PM PDT 24
Finished Aug 05 06:10:27 PM PDT 24
Peak memory 201320 kb
Host smart-a05b366b-0771-4b7a-9538-cb7e94839db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435158622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1435158622
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3293804589
Short name T807
Test name
Test status
Simulation time 494426173 ps
CPU time 1.81 seconds
Started Aug 05 06:10:06 PM PDT 24
Finished Aug 05 06:10:08 PM PDT 24
Peak memory 201344 kb
Host smart-a3380d05-4902-4883-a4e4-4b5023e05ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293804589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3293804589
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2459765129
Short name T801
Test name
Test status
Simulation time 348058871 ps
CPU time 1.26 seconds
Started Aug 05 06:10:23 PM PDT 24
Finished Aug 05 06:10:25 PM PDT 24
Peak memory 201360 kb
Host smart-8f4e842a-7a7c-49f7-a111-36363a8c609f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459765129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2459765129
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.894943585
Short name T863
Test name
Test status
Simulation time 370860772 ps
CPU time 1.53 seconds
Started Aug 05 06:10:26 PM PDT 24
Finished Aug 05 06:10:27 PM PDT 24
Peak memory 201368 kb
Host smart-40d8e8c3-41d7-455e-a5de-4d75df196972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894943585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.894943585
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1598435675
Short name T865
Test name
Test status
Simulation time 478383318 ps
CPU time 0.87 seconds
Started Aug 05 06:10:16 PM PDT 24
Finished Aug 05 06:10:17 PM PDT 24
Peak memory 201360 kb
Host smart-cf8fe798-224e-40a6-9267-7f2cab01feef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598435675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1598435675
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2133073526
Short name T914
Test name
Test status
Simulation time 418312740 ps
CPU time 1.53 seconds
Started Aug 05 06:10:06 PM PDT 24
Finished Aug 05 06:10:07 PM PDT 24
Peak memory 201348 kb
Host smart-3803890c-ca16-4bab-aeb1-60642744f4ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133073526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2133073526
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4152896899
Short name T822
Test name
Test status
Simulation time 432186202 ps
CPU time 1.56 seconds
Started Aug 05 06:10:18 PM PDT 24
Finished Aug 05 06:10:20 PM PDT 24
Peak memory 201348 kb
Host smart-8e052674-e6bf-429c-baca-5934587a4521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152896899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.4152896899
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.4231379865
Short name T889
Test name
Test status
Simulation time 402137035 ps
CPU time 1.31 seconds
Started Aug 05 06:10:15 PM PDT 24
Finished Aug 05 06:10:16 PM PDT 24
Peak memory 201356 kb
Host smart-2bebbad7-f3a6-4a70-8b65-9c1f7344c40d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231379865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.4231379865
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3325758219
Short name T827
Test name
Test status
Simulation time 305089921 ps
CPU time 1.01 seconds
Started Aug 05 06:10:07 PM PDT 24
Finished Aug 05 06:10:08 PM PDT 24
Peak memory 201360 kb
Host smart-6154cad7-93e0-4baa-8087-c1d582fccf53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325758219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3325758219
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.346859171
Short name T895
Test name
Test status
Simulation time 1225159957 ps
CPU time 3.63 seconds
Started Aug 05 06:09:55 PM PDT 24
Finished Aug 05 06:09:59 PM PDT 24
Peak memory 201552 kb
Host smart-9085a880-5601-4322-86f6-8292e96fc107
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346859171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.346859171
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3614945598
Short name T52
Test name
Test status
Simulation time 23077721288 ps
CPU time 51.58 seconds
Started Aug 05 06:09:54 PM PDT 24
Finished Aug 05 06:10:46 PM PDT 24
Peak memory 201556 kb
Host smart-9b62694e-d36e-4d4a-9b36-256be0397288
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614945598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3614945598
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3227564178
Short name T119
Test name
Test status
Simulation time 929044537 ps
CPU time 2.65 seconds
Started Aug 05 06:09:51 PM PDT 24
Finished Aug 05 06:09:54 PM PDT 24
Peak memory 201380 kb
Host smart-f17bb00b-42aa-47ba-8999-97ea6ddea43a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227564178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3227564178
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.406428121
Short name T877
Test name
Test status
Simulation time 461263446 ps
CPU time 1.85 seconds
Started Aug 05 06:10:03 PM PDT 24
Finished Aug 05 06:10:05 PM PDT 24
Peak memory 201476 kb
Host smart-c9a57d7e-10f7-44c9-b60a-5c4854e3379a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406428121 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.406428121
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3034543449
Short name T866
Test name
Test status
Simulation time 337238463 ps
CPU time 1.5 seconds
Started Aug 05 06:09:55 PM PDT 24
Finished Aug 05 06:09:57 PM PDT 24
Peak memory 201252 kb
Host smart-ed3e010b-3e30-4370-8523-b588f0d992d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034543449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3034543449
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.970734493
Short name T887
Test name
Test status
Simulation time 418536715 ps
CPU time 0.86 seconds
Started Aug 05 06:09:54 PM PDT 24
Finished Aug 05 06:09:55 PM PDT 24
Peak memory 201360 kb
Host smart-f21d52fd-eb07-4187-8bb6-034301e5d8b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970734493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.970734493
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1747070374
Short name T840
Test name
Test status
Simulation time 3925836412 ps
CPU time 9.82 seconds
Started Aug 05 06:09:54 PM PDT 24
Finished Aug 05 06:10:04 PM PDT 24
Peak memory 201620 kb
Host smart-497fcdc7-4a3c-4686-ab76-13a98bbdb629
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747070374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1747070374
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1794638969
Short name T862
Test name
Test status
Simulation time 477179862 ps
CPU time 2.45 seconds
Started Aug 05 06:09:59 PM PDT 24
Finished Aug 05 06:10:02 PM PDT 24
Peak memory 217608 kb
Host smart-0676c99f-afd9-4730-a27f-298a4caa4291
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794638969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1794638969
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3769844736
Short name T55
Test name
Test status
Simulation time 4439652241 ps
CPU time 10.27 seconds
Started Aug 05 06:10:05 PM PDT 24
Finished Aug 05 06:10:15 PM PDT 24
Peak memory 201616 kb
Host smart-949d7051-a043-4fb1-9e33-4aa5705e8d3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769844736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3769844736
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1754288024
Short name T856
Test name
Test status
Simulation time 331227039 ps
CPU time 0.98 seconds
Started Aug 05 06:10:17 PM PDT 24
Finished Aug 05 06:10:18 PM PDT 24
Peak memory 201352 kb
Host smart-b804a755-c33a-4e6d-a3be-9b128fa8541c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754288024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1754288024
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3687443836
Short name T869
Test name
Test status
Simulation time 375702129 ps
CPU time 1.07 seconds
Started Aug 05 06:10:18 PM PDT 24
Finished Aug 05 06:10:20 PM PDT 24
Peak memory 201324 kb
Host smart-aed577c2-6b29-4d0f-a28a-f379a486bf44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687443836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3687443836
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1142739136
Short name T916
Test name
Test status
Simulation time 449930081 ps
CPU time 0.92 seconds
Started Aug 05 06:10:26 PM PDT 24
Finished Aug 05 06:10:32 PM PDT 24
Peak memory 201380 kb
Host smart-262fc6cb-bb00-4bd3-b88f-6de029ae3611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142739136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1142739136
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3558793678
Short name T803
Test name
Test status
Simulation time 447762151 ps
CPU time 0.74 seconds
Started Aug 05 06:10:20 PM PDT 24
Finished Aug 05 06:10:21 PM PDT 24
Peak memory 201344 kb
Host smart-11b2f416-7072-46cc-b5e5-507ca4108b33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558793678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3558793678
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4242217695
Short name T850
Test name
Test status
Simulation time 462449648 ps
CPU time 0.7 seconds
Started Aug 05 06:10:09 PM PDT 24
Finished Aug 05 06:10:10 PM PDT 24
Peak memory 201372 kb
Host smart-e1bfbd5a-7d5f-40f3-8ba2-fb65b424542b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242217695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4242217695
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2304954702
Short name T809
Test name
Test status
Simulation time 631319088 ps
CPU time 0.75 seconds
Started Aug 05 06:10:24 PM PDT 24
Finished Aug 05 06:10:24 PM PDT 24
Peak memory 201356 kb
Host smart-4ab7cfbc-3067-4aa8-bc8f-f032c5419a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304954702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2304954702
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1681970328
Short name T814
Test name
Test status
Simulation time 525023496 ps
CPU time 1.74 seconds
Started Aug 05 06:10:03 PM PDT 24
Finished Aug 05 06:10:05 PM PDT 24
Peak memory 201372 kb
Host smart-f729c5b9-7faa-431a-be15-dd5421739416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681970328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1681970328
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3178566769
Short name T891
Test name
Test status
Simulation time 284199579 ps
CPU time 1.21 seconds
Started Aug 05 06:10:05 PM PDT 24
Finished Aug 05 06:10:06 PM PDT 24
Peak memory 201348 kb
Host smart-802f0753-2ae4-4a56-91ce-f0a9ad1a0a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178566769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3178566769
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1501092004
Short name T883
Test name
Test status
Simulation time 288241866 ps
CPU time 1.25 seconds
Started Aug 05 06:10:25 PM PDT 24
Finished Aug 05 06:10:26 PM PDT 24
Peak memory 201248 kb
Host smart-a6b6bd4e-c4ae-486c-890f-93e57496f5ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501092004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1501092004
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3349994930
Short name T873
Test name
Test status
Simulation time 413285241 ps
CPU time 0.8 seconds
Started Aug 05 06:10:05 PM PDT 24
Finished Aug 05 06:10:06 PM PDT 24
Peak memory 201396 kb
Host smart-23be3d34-eb5e-4598-bbf8-2c6386902507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349994930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3349994930
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.122186067
Short name T854
Test name
Test status
Simulation time 569907783 ps
CPU time 1.38 seconds
Started Aug 05 06:10:03 PM PDT 24
Finished Aug 05 06:10:05 PM PDT 24
Peak memory 212148 kb
Host smart-011140ed-585f-467c-94e9-39563f09b922
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122186067 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.122186067
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3414798161
Short name T911
Test name
Test status
Simulation time 586584787 ps
CPU time 0.87 seconds
Started Aug 05 06:10:10 PM PDT 24
Finished Aug 05 06:10:11 PM PDT 24
Peak memory 201384 kb
Host smart-5732b7cb-cf2b-4adc-a05e-9d9ad2b4cbe4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414798161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3414798161
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1021831047
Short name T824
Test name
Test status
Simulation time 440788784 ps
CPU time 0.87 seconds
Started Aug 05 06:10:25 PM PDT 24
Finished Aug 05 06:10:26 PM PDT 24
Peak memory 201264 kb
Host smart-43cedef3-ce99-4ac9-85f2-dee6ae7e1a13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021831047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1021831047
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2197294160
Short name T915
Test name
Test status
Simulation time 2070061036 ps
CPU time 1.97 seconds
Started Aug 05 06:09:59 PM PDT 24
Finished Aug 05 06:10:01 PM PDT 24
Peak memory 201388 kb
Host smart-f9fb2d48-022e-4b33-95fb-b7871a5c756d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197294160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2197294160
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3134116301
Short name T892
Test name
Test status
Simulation time 448256100 ps
CPU time 2.1 seconds
Started Aug 05 06:10:01 PM PDT 24
Finished Aug 05 06:10:08 PM PDT 24
Peak memory 209860 kb
Host smart-9a68518c-632e-4a9f-a4f4-a079c85be5ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134116301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3134116301
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3949149144
Short name T884
Test name
Test status
Simulation time 8388401802 ps
CPU time 20.96 seconds
Started Aug 05 06:10:11 PM PDT 24
Finished Aug 05 06:10:32 PM PDT 24
Peak memory 201684 kb
Host smart-bbaa4732-d095-4dd6-aa23-e9b63790234b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949149144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3949149144
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.731492735
Short name T823
Test name
Test status
Simulation time 609500733 ps
CPU time 1.36 seconds
Started Aug 05 06:10:24 PM PDT 24
Finished Aug 05 06:10:25 PM PDT 24
Peak memory 201508 kb
Host smart-4e9e3043-6c06-45d7-9f89-ade503cf5661
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731492735 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.731492735
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1908146209
Short name T137
Test name
Test status
Simulation time 424124124 ps
CPU time 1.18 seconds
Started Aug 05 06:10:11 PM PDT 24
Finished Aug 05 06:10:13 PM PDT 24
Peak memory 201388 kb
Host smart-a8224d95-4a15-4f63-9cba-17b10c33bfad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908146209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1908146209
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2477438044
Short name T879
Test name
Test status
Simulation time 509944269 ps
CPU time 1.73 seconds
Started Aug 05 06:10:03 PM PDT 24
Finished Aug 05 06:10:05 PM PDT 24
Peak memory 201364 kb
Host smart-ee474862-54a3-47eb-b900-ae25cab92f3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477438044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2477438044
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2050748046
Short name T859
Test name
Test status
Simulation time 5262246289 ps
CPU time 6.64 seconds
Started Aug 05 06:10:08 PM PDT 24
Finished Aug 05 06:10:15 PM PDT 24
Peak memory 201544 kb
Host smart-29d4207e-1758-40f5-8d14-c6b6da32da8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050748046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2050748046
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.742186976
Short name T66
Test name
Test status
Simulation time 1109355932 ps
CPU time 3.11 seconds
Started Aug 05 06:09:55 PM PDT 24
Finished Aug 05 06:09:58 PM PDT 24
Peak memory 201652 kb
Host smart-b2eea86a-69c8-424b-a6f5-065c2674f1ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742186976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.742186976
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1136026340
Short name T837
Test name
Test status
Simulation time 7973120619 ps
CPU time 19.12 seconds
Started Aug 05 06:10:09 PM PDT 24
Finished Aug 05 06:10:28 PM PDT 24
Peak memory 201644 kb
Host smart-322b6ea3-6111-4931-8950-36f9b61be42a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136026340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1136026340
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.595454698
Short name T881
Test name
Test status
Simulation time 493279299 ps
CPU time 0.98 seconds
Started Aug 05 06:10:08 PM PDT 24
Finished Aug 05 06:10:09 PM PDT 24
Peak memory 201504 kb
Host smart-f874a8be-ed86-4efb-b2f3-e3d55955826a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595454698 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.595454698
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3576877071
Short name T908
Test name
Test status
Simulation time 487704568 ps
CPU time 1.05 seconds
Started Aug 05 06:10:06 PM PDT 24
Finished Aug 05 06:10:07 PM PDT 24
Peak memory 201340 kb
Host smart-5b31335a-8810-4066-ad6c-c5080130664b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576877071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3576877071
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3658589507
Short name T831
Test name
Test status
Simulation time 506677449 ps
CPU time 0.91 seconds
Started Aug 05 06:10:05 PM PDT 24
Finished Aug 05 06:10:06 PM PDT 24
Peak memory 201384 kb
Host smart-d9f62c11-ab95-4907-b988-40eb8706b8bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658589507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3658589507
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.860042744
Short name T132
Test name
Test status
Simulation time 4391576130 ps
CPU time 2.58 seconds
Started Aug 05 06:10:12 PM PDT 24
Finished Aug 05 06:10:14 PM PDT 24
Peak memory 201592 kb
Host smart-81c59da2-080b-4d87-900b-fb9b2b6b8203
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860042744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.860042744
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2761040344
Short name T888
Test name
Test status
Simulation time 683155198 ps
CPU time 2.16 seconds
Started Aug 05 06:10:09 PM PDT 24
Finished Aug 05 06:10:12 PM PDT 24
Peak memory 201652 kb
Host smart-c9ca34e9-df93-4b01-817f-0ea2e071cbd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761040344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2761040344
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1379398623
Short name T829
Test name
Test status
Simulation time 8816874293 ps
CPU time 23.4 seconds
Started Aug 05 06:10:06 PM PDT 24
Finished Aug 05 06:10:30 PM PDT 24
Peak memory 201680 kb
Host smart-b7b880d2-a85f-47e3-b967-752c8d935cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379398623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1379398623
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4101287389
Short name T58
Test name
Test status
Simulation time 903561951 ps
CPU time 1.18 seconds
Started Aug 05 06:10:08 PM PDT 24
Finished Aug 05 06:10:09 PM PDT 24
Peak memory 201492 kb
Host smart-b2b9c278-8ea1-49bd-84e2-2a18750be3c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101287389 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.4101287389
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2530343690
Short name T140
Test name
Test status
Simulation time 323683449 ps
CPU time 1.5 seconds
Started Aug 05 06:10:24 PM PDT 24
Finished Aug 05 06:10:26 PM PDT 24
Peak memory 201348 kb
Host smart-f095a07c-8fdf-4bd1-9b2b-40a751c07746
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530343690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2530343690
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2865344791
Short name T804
Test name
Test status
Simulation time 448691046 ps
CPU time 1.12 seconds
Started Aug 05 06:10:04 PM PDT 24
Finished Aug 05 06:10:06 PM PDT 24
Peak memory 201364 kb
Host smart-6f40dca0-4617-4b65-b61c-04a9c0e6939e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865344791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2865344791
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.702873296
Short name T867
Test name
Test status
Simulation time 2375552570 ps
CPU time 1.48 seconds
Started Aug 05 06:09:57 PM PDT 24
Finished Aug 05 06:09:58 PM PDT 24
Peak memory 201388 kb
Host smart-4b050e2c-d1d6-43c2-a74b-df636dec1ac8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702873296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.702873296
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3241444661
Short name T833
Test name
Test status
Simulation time 450741981 ps
CPU time 3.06 seconds
Started Aug 05 06:10:00 PM PDT 24
Finished Aug 05 06:10:04 PM PDT 24
Peak memory 209836 kb
Host smart-6ab5a698-3296-422e-a01b-58d601e914ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241444661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3241444661
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2740666013
Short name T67
Test name
Test status
Simulation time 4596432633 ps
CPU time 12.08 seconds
Started Aug 05 06:09:57 PM PDT 24
Finished Aug 05 06:10:10 PM PDT 24
Peak memory 201688 kb
Host smart-f645bc3d-4c4a-44e0-8c71-6ec8231ce026
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740666013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2740666013
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.435946688
Short name T905
Test name
Test status
Simulation time 539946155 ps
CPU time 2.19 seconds
Started Aug 05 06:09:59 PM PDT 24
Finished Aug 05 06:10:01 PM PDT 24
Peak memory 201472 kb
Host smart-0ccf016c-116d-43c5-8800-2ac3b3a425e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435946688 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.435946688
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1135639962
Short name T130
Test name
Test status
Simulation time 411648616 ps
CPU time 1.78 seconds
Started Aug 05 06:10:00 PM PDT 24
Finished Aug 05 06:10:02 PM PDT 24
Peak memory 201368 kb
Host smart-2898e2a1-a75c-4bfa-b772-21d753385992
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135639962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1135639962
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4126120777
Short name T845
Test name
Test status
Simulation time 319123357 ps
CPU time 0.81 seconds
Started Aug 05 06:10:12 PM PDT 24
Finished Aug 05 06:10:13 PM PDT 24
Peak memory 201368 kb
Host smart-dd9b724d-cd28-4ffb-92ef-493cd4ed8228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126120777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4126120777
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.586746999
Short name T133
Test name
Test status
Simulation time 4848499806 ps
CPU time 19.66 seconds
Started Aug 05 06:10:01 PM PDT 24
Finished Aug 05 06:10:21 PM PDT 24
Peak memory 201448 kb
Host smart-495e2e2a-72e2-4833-92ea-21da6b531bef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586746999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.586746999
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.979364022
Short name T852
Test name
Test status
Simulation time 637037881 ps
CPU time 4.18 seconds
Started Aug 05 06:09:58 PM PDT 24
Finished Aug 05 06:10:02 PM PDT 24
Peak memory 201648 kb
Host smart-c60b3b06-a46e-4de0-8d68-e31f7a8847a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979364022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.979364022
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1492215342
Short name T167
Test name
Test status
Simulation time 549264594986 ps
CPU time 110.57 seconds
Started Aug 05 06:10:25 PM PDT 24
Finished Aug 05 06:12:16 PM PDT 24
Peak memory 201460 kb
Host smart-643df6b0-8f8c-4f1b-b99c-318e7995bf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492215342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1492215342
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1927923807
Short name T194
Test name
Test status
Simulation time 336040799760 ps
CPU time 192.25 seconds
Started Aug 05 06:10:26 PM PDT 24
Finished Aug 05 06:13:39 PM PDT 24
Peak memory 201456 kb
Host smart-454015aa-456f-41d2-bc35-975b234fce9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927923807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1927923807
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.4121064047
Short name T407
Test name
Test status
Simulation time 331073230857 ps
CPU time 376.65 seconds
Started Aug 05 06:10:29 PM PDT 24
Finished Aug 05 06:16:46 PM PDT 24
Peak memory 201088 kb
Host smart-c7e85ed4-6849-4399-8f8e-18a6c2fa2076
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121064047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.4121064047
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.650987398
Short name T92
Test name
Test status
Simulation time 498143013338 ps
CPU time 293.27 seconds
Started Aug 05 06:10:31 PM PDT 24
Finished Aug 05 06:15:24 PM PDT 24
Peak memory 201452 kb
Host smart-e91d5f62-26e2-47bc-96fc-312dc9cde07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650987398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.650987398
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1749761581
Short name T369
Test name
Test status
Simulation time 158370579705 ps
CPU time 171.98 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:13:20 PM PDT 24
Peak memory 201424 kb
Host smart-d87b3c82-a25f-4b48-a709-74200ff2edbb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749761581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1749761581
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4265095880
Short name T464
Test name
Test status
Simulation time 396917638461 ps
CPU time 244.24 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:14:33 PM PDT 24
Peak memory 201508 kb
Host smart-d9bf2bcc-d503-4386-92e1-1c569a9b55d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265095880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.4265095880
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2881440838
Short name T706
Test name
Test status
Simulation time 85901617714 ps
CPU time 270.97 seconds
Started Aug 05 06:10:21 PM PDT 24
Finished Aug 05 06:14:52 PM PDT 24
Peak memory 201856 kb
Host smart-e8e924f3-e36e-4a50-a9aa-6fc6cb251e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881440838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2881440838
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2188106175
Short name T564
Test name
Test status
Simulation time 39474024991 ps
CPU time 89.56 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:11:57 PM PDT 24
Peak memory 201356 kb
Host smart-33c1752d-1fe5-4f3d-9792-87d7e368bbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188106175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2188106175
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.692272011
Short name T26
Test name
Test status
Simulation time 3888199471 ps
CPU time 4.74 seconds
Started Aug 05 06:10:25 PM PDT 24
Finished Aug 05 06:10:30 PM PDT 24
Peak memory 201364 kb
Host smart-f2ff0c12-0b44-43d9-b02d-ec85ee6d6712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692272011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.692272011
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1443324984
Short name T77
Test name
Test status
Simulation time 4162903274 ps
CPU time 9.66 seconds
Started Aug 05 06:10:25 PM PDT 24
Finished Aug 05 06:10:35 PM PDT 24
Peak memory 217080 kb
Host smart-0d91d4e6-448b-4832-a79c-bda9a0920ff5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443324984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1443324984
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3789562712
Short name T550
Test name
Test status
Simulation time 5832300933 ps
CPU time 4.33 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:10:32 PM PDT 24
Peak memory 201344 kb
Host smart-c3ac1e37-0732-4618-88d4-f3d3c73c1a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789562712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3789562712
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2178017447
Short name T283
Test name
Test status
Simulation time 204730314777 ps
CPU time 108.34 seconds
Started Aug 05 06:10:38 PM PDT 24
Finished Aug 05 06:12:26 PM PDT 24
Peak memory 201460 kb
Host smart-750a551e-4b7a-4e9e-b35a-e6f427ba0498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178017447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2178017447
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.853407725
Short name T111
Test name
Test status
Simulation time 60395991484 ps
CPU time 78.82 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:11:48 PM PDT 24
Peak memory 210152 kb
Host smart-d8c03aca-4d1c-4886-92a7-0f3e8eb8cbb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853407725 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.853407725
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3155332380
Short name T669
Test name
Test status
Simulation time 417785291 ps
CPU time 0.7 seconds
Started Aug 05 06:10:21 PM PDT 24
Finished Aug 05 06:10:22 PM PDT 24
Peak memory 201236 kb
Host smart-44ebb506-5b3e-47b3-9c26-18b904b3082a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155332380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3155332380
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2746720718
Short name T242
Test name
Test status
Simulation time 161345039602 ps
CPU time 73.47 seconds
Started Aug 05 06:10:24 PM PDT 24
Finished Aug 05 06:11:38 PM PDT 24
Peak memory 201412 kb
Host smart-a14b13af-6568-40a1-ac13-fc18919c9597
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746720718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2746720718
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1083972597
Short name T460
Test name
Test status
Simulation time 163975364855 ps
CPU time 142.58 seconds
Started Aug 05 06:10:18 PM PDT 24
Finished Aug 05 06:12:41 PM PDT 24
Peak memory 201480 kb
Host smart-3930cfce-a3a6-4aa4-a6de-e14d44899ee6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083972597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1083972597
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1221110445
Short name T160
Test name
Test status
Simulation time 328677459734 ps
CPU time 770.51 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:23:19 PM PDT 24
Peak memory 201396 kb
Host smart-aee86014-05f9-4e2a-b06a-cb11949453e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221110445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1221110445
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1833380271
Short name T545
Test name
Test status
Simulation time 331661691352 ps
CPU time 207.2 seconds
Started Aug 05 06:10:33 PM PDT 24
Finished Aug 05 06:14:01 PM PDT 24
Peak memory 201460 kb
Host smart-be0d0ee4-ef17-4dd2-8b80-46d285c6fe0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833380271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1833380271
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.4200352654
Short name T798
Test name
Test status
Simulation time 384582351003 ps
CPU time 954.79 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:26:23 PM PDT 24
Peak memory 201344 kb
Host smart-a3236b35-5180-402f-9322-917f8a12b425
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200352654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.4200352654
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3601548398
Short name T492
Test name
Test status
Simulation time 204084319117 ps
CPU time 446.04 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:17:54 PM PDT 24
Peak memory 201504 kb
Host smart-33621bc1-5e6b-408c-99bb-2d16017e9933
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601548398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3601548398
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3257252023
Short name T497
Test name
Test status
Simulation time 70787080961 ps
CPU time 392.28 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:17:01 PM PDT 24
Peak memory 201852 kb
Host smart-4e79440a-9761-4f0a-adbb-7086fe480801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257252023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3257252023
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.4071825127
Short name T392
Test name
Test status
Simulation time 37716372703 ps
CPU time 84.51 seconds
Started Aug 05 06:10:21 PM PDT 24
Finished Aug 05 06:11:51 PM PDT 24
Peak memory 201324 kb
Host smart-b53f0688-fb75-4b65-83e7-15a8f496b9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071825127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4071825127
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2820341476
Short name T637
Test name
Test status
Simulation time 4173750341 ps
CPU time 5.71 seconds
Started Aug 05 06:10:37 PM PDT 24
Finished Aug 05 06:10:42 PM PDT 24
Peak memory 201348 kb
Host smart-d04b1c1a-ab58-4677-bf73-1684d8d284ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820341476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2820341476
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3444246999
Short name T76
Test name
Test status
Simulation time 7310749597 ps
CPU time 18.04 seconds
Started Aug 05 06:10:24 PM PDT 24
Finished Aug 05 06:10:42 PM PDT 24
Peak memory 218284 kb
Host smart-cdaac93e-4d73-4350-9010-6fb888e0765d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444246999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3444246999
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.655327924
Short name T699
Test name
Test status
Simulation time 6077393038 ps
CPU time 13.77 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:10:42 PM PDT 24
Peak memory 201388 kb
Host smart-402c2419-002a-43db-8b39-8a2d8d929605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655327924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.655327924
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.812884169
Short name T346
Test name
Test status
Simulation time 328244419790 ps
CPU time 714.25 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:22:22 PM PDT 24
Peak memory 201452 kb
Host smart-f5eaf51a-2985-4e82-8a75-a3a42a5853c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812884169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.812884169
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1709360870
Short name T772
Test name
Test status
Simulation time 882311152461 ps
CPU time 255.05 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:14:44 PM PDT 24
Peak memory 210160 kb
Host smart-378da343-351e-4a7b-9613-060ac1073afd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709360870 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1709360870
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.4057588317
Short name T498
Test name
Test status
Simulation time 324782715 ps
CPU time 0.81 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:10:56 PM PDT 24
Peak memory 201252 kb
Host smart-dd99ec37-f648-4c42-a435-6c36742732fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057588317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.4057588317
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1467152438
Short name T165
Test name
Test status
Simulation time 331636688943 ps
CPU time 222.51 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:14:37 PM PDT 24
Peak memory 201508 kb
Host smart-933104b2-6398-4549-a3d3-bf76a5d2d9d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467152438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1467152438
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3705827313
Short name T633
Test name
Test status
Simulation time 163661923425 ps
CPU time 344.62 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:16:42 PM PDT 24
Peak memory 201440 kb
Host smart-70d58af8-88d2-466b-a604-c7d3b86be1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705827313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3705827313
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1500144482
Short name T768
Test name
Test status
Simulation time 329947550781 ps
CPU time 342.72 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:16:38 PM PDT 24
Peak memory 201516 kb
Host smart-f230df1b-d9c7-424d-80ea-34ed8b657ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500144482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1500144482
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3748955034
Short name T652
Test name
Test status
Simulation time 162418506590 ps
CPU time 361.77 seconds
Started Aug 05 06:11:03 PM PDT 24
Finished Aug 05 06:17:05 PM PDT 24
Peak memory 201416 kb
Host smart-c6dacbb2-366f-4ddb-962d-4653153f10f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748955034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3748955034
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.765044418
Short name T256
Test name
Test status
Simulation time 160699273192 ps
CPU time 379.15 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:17:14 PM PDT 24
Peak memory 201424 kb
Host smart-dc9ad7e1-b249-40f3-a46e-f2bb2c0476e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765044418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.765044418
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2020583887
Short name T186
Test name
Test status
Simulation time 161744590700 ps
CPU time 360.13 seconds
Started Aug 05 06:10:56 PM PDT 24
Finished Aug 05 06:16:57 PM PDT 24
Peak memory 201484 kb
Host smart-3ccbf2b7-285a-4f8d-8246-e390c2a68e0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020583887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2020583887
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.4241799635
Short name T264
Test name
Test status
Simulation time 363345855503 ps
CPU time 210.43 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:14:25 PM PDT 24
Peak memory 201448 kb
Host smart-5f951d52-c24d-4754-8f5f-8da74307df04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241799635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.4241799635
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2459537703
Short name T682
Test name
Test status
Simulation time 598200532168 ps
CPU time 1437.42 seconds
Started Aug 05 06:10:56 PM PDT 24
Finished Aug 05 06:34:53 PM PDT 24
Peak memory 201516 kb
Host smart-7c0c66db-97fd-4ba6-8d96-7a003ce164dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459537703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2459537703
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1465292363
Short name T507
Test name
Test status
Simulation time 119561531750 ps
CPU time 438.67 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:18:14 PM PDT 24
Peak memory 201840 kb
Host smart-f55eeeb0-4805-4af3-a781-e68e26f69909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465292363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1465292363
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2341651044
Short name T594
Test name
Test status
Simulation time 30431501567 ps
CPU time 34.49 seconds
Started Aug 05 06:11:01 PM PDT 24
Finished Aug 05 06:11:35 PM PDT 24
Peak memory 201384 kb
Host smart-2c14ae6b-5ac4-4f3a-a4c2-acfbe3ea4721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341651044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2341651044
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.553343399
Short name T96
Test name
Test status
Simulation time 3845166771 ps
CPU time 1.53 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:11:14 PM PDT 24
Peak memory 201288 kb
Host smart-077273f3-5a2c-468c-b463-7bb20a6ae394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553343399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.553343399
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.533685951
Short name T42
Test name
Test status
Simulation time 5938250324 ps
CPU time 2.32 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:10:57 PM PDT 24
Peak memory 201376 kb
Host smart-1cf10320-aa01-4ed0-8551-f24420906df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533685951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.533685951
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1042031140
Short name T33
Test name
Test status
Simulation time 345382279220 ps
CPU time 288.93 seconds
Started Aug 05 06:11:03 PM PDT 24
Finished Aug 05 06:15:52 PM PDT 24
Peak memory 210156 kb
Host smart-f4846a5a-a374-404c-baca-562fe6a92b8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042031140 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1042031140
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.564504548
Short name T465
Test name
Test status
Simulation time 396859607 ps
CPU time 1.54 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:10:57 PM PDT 24
Peak memory 201256 kb
Host smart-52da8074-df3f-404e-82aa-270079d9b146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564504548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.564504548
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2849763052
Short name T185
Test name
Test status
Simulation time 497941159702 ps
CPU time 317.73 seconds
Started Aug 05 06:10:59 PM PDT 24
Finished Aug 05 06:16:17 PM PDT 24
Peak memory 201436 kb
Host smart-67496fbd-fc5a-40db-adac-fce693fb1af1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849763052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2849763052
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3106057005
Short name T276
Test name
Test status
Simulation time 514651650436 ps
CPU time 327.19 seconds
Started Aug 05 06:11:06 PM PDT 24
Finished Aug 05 06:16:33 PM PDT 24
Peak memory 201440 kb
Host smart-0faa8805-60c3-4b83-bc84-8cde37e6732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106057005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3106057005
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1701867852
Short name T777
Test name
Test status
Simulation time 163275165708 ps
CPU time 381.48 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:17:19 PM PDT 24
Peak memory 201464 kb
Host smart-ad294c6e-0873-476a-8a00-b609dc4c5fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701867852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1701867852
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1465803319
Short name T590
Test name
Test status
Simulation time 321357281767 ps
CPU time 220.56 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:14:36 PM PDT 24
Peak memory 201448 kb
Host smart-7d48f302-00b7-4e18-98c4-6662d7f47e2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465803319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1465803319
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3724274573
Short name T742
Test name
Test status
Simulation time 495979033011 ps
CPU time 219.19 seconds
Started Aug 05 06:11:09 PM PDT 24
Finished Aug 05 06:14:49 PM PDT 24
Peak memory 201456 kb
Host smart-944f61e8-9c77-4e42-93dc-f0f2866ae767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724274573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3724274573
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1314333370
Short name T458
Test name
Test status
Simulation time 325953467745 ps
CPU time 765.68 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:23:44 PM PDT 24
Peak memory 201452 kb
Host smart-8eaa0544-2a1d-4fed-a60a-e9575ecaab85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314333370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1314333370
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1301053775
Short name T690
Test name
Test status
Simulation time 389650034770 ps
CPU time 220.32 seconds
Started Aug 05 06:11:04 PM PDT 24
Finished Aug 05 06:14:44 PM PDT 24
Peak memory 201448 kb
Host smart-6291e3e8-ea73-464b-8977-df69e061d3ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301053775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1301053775
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2440378696
Short name T81
Test name
Test status
Simulation time 75388488531 ps
CPU time 261.5 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:15:20 PM PDT 24
Peak memory 201836 kb
Host smart-4e272bf2-5b34-4a10-a528-bdcb07a9e49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440378696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2440378696
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.321410502
Short name T515
Test name
Test status
Simulation time 26819492964 ps
CPU time 32.52 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:11:31 PM PDT 24
Peak memory 201340 kb
Host smart-ab791a17-6185-4e21-b040-c1042f6ce259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321410502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.321410502
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3748002454
Short name T403
Test name
Test status
Simulation time 3199676758 ps
CPU time 1.05 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:10:55 PM PDT 24
Peak memory 201328 kb
Host smart-cb905df4-2edf-4be6-982c-1c8243570c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748002454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3748002454
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3213558266
Short name T463
Test name
Test status
Simulation time 5655206777 ps
CPU time 3.3 seconds
Started Aug 05 06:11:02 PM PDT 24
Finished Aug 05 06:11:05 PM PDT 24
Peak memory 201380 kb
Host smart-11b9d66e-5b70-4000-a2b4-e5e59d20eab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213558266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3213558266
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1206849044
Short name T153
Test name
Test status
Simulation time 196964919685 ps
CPU time 235.68 seconds
Started Aug 05 06:10:59 PM PDT 24
Finished Aug 05 06:14:55 PM PDT 24
Peak memory 201452 kb
Host smart-e154f97b-5378-4f09-a62e-7b8fee18662d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206849044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1206849044
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3353244647
Short name T159
Test name
Test status
Simulation time 16505002975 ps
CPU time 41.45 seconds
Started Aug 05 06:10:53 PM PDT 24
Finished Aug 05 06:11:35 PM PDT 24
Peak memory 210136 kb
Host smart-2abd60e8-8f55-4e5e-9127-b6b24713dd55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353244647 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3353244647
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2045933318
Short name T656
Test name
Test status
Simulation time 534341844 ps
CPU time 0.96 seconds
Started Aug 05 06:11:12 PM PDT 24
Finished Aug 05 06:11:13 PM PDT 24
Peak memory 201244 kb
Host smart-7245b2a4-23a5-4fa4-841e-9dbb9987be12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045933318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2045933318
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.4054974901
Short name T721
Test name
Test status
Simulation time 326568059402 ps
CPU time 725.82 seconds
Started Aug 05 06:11:04 PM PDT 24
Finished Aug 05 06:23:10 PM PDT 24
Peak memory 201436 kb
Host smart-f1fa990f-3791-41b3-8fff-833968debf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054974901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.4054974901
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3725028231
Short name T738
Test name
Test status
Simulation time 163721156673 ps
CPU time 192.78 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:14:10 PM PDT 24
Peak memory 201432 kb
Host smart-bd89a2f7-bacf-4139-af13-d1c33b47623d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725028231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3725028231
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2061933424
Short name T402
Test name
Test status
Simulation time 323998833336 ps
CPU time 687.62 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:22:47 PM PDT 24
Peak memory 201440 kb
Host smart-5a6699b9-b028-4ce6-801f-396853df2aa5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061933424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2061933424
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.4081589702
Short name T192
Test name
Test status
Simulation time 334837335093 ps
CPU time 210.16 seconds
Started Aug 05 06:11:04 PM PDT 24
Finished Aug 05 06:14:34 PM PDT 24
Peak memory 201420 kb
Host smart-ae63e7f2-db46-4870-8185-dc87d5c144f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081589702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.4081589702
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1749786565
Short name T436
Test name
Test status
Simulation time 485846962987 ps
CPU time 588.71 seconds
Started Aug 05 06:11:03 PM PDT 24
Finished Aug 05 06:20:52 PM PDT 24
Peak memory 201420 kb
Host smart-059fab6b-493d-42b4-a58b-b439b22b0e56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749786565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1749786565
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3511156128
Short name T146
Test name
Test status
Simulation time 349664309351 ps
CPU time 200.16 seconds
Started Aug 05 06:11:03 PM PDT 24
Finished Aug 05 06:14:24 PM PDT 24
Peak memory 201444 kb
Host smart-dd0f3bd9-2f58-47e3-8cba-d7e727e0f300
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511156128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3511156128
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1979550609
Short name T725
Test name
Test status
Simulation time 393821181983 ps
CPU time 155.26 seconds
Started Aug 05 06:10:47 PM PDT 24
Finished Aug 05 06:13:23 PM PDT 24
Peak memory 201456 kb
Host smart-a360ba2b-d48f-4259-819b-a378b16fdc78
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979550609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1979550609
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3678208177
Short name T205
Test name
Test status
Simulation time 77154864953 ps
CPU time 283.46 seconds
Started Aug 05 06:11:14 PM PDT 24
Finished Aug 05 06:15:57 PM PDT 24
Peak memory 201792 kb
Host smart-78d9b364-70f4-4e15-b95c-29953ca56d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678208177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3678208177
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.515940779
Short name T412
Test name
Test status
Simulation time 24075137442 ps
CPU time 4.84 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:11:02 PM PDT 24
Peak memory 201316 kb
Host smart-0f4b3a92-43de-4674-a597-a81faed3cb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515940779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.515940779
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2171363036
Short name T573
Test name
Test status
Simulation time 4720580766 ps
CPU time 3.51 seconds
Started Aug 05 06:11:04 PM PDT 24
Finished Aug 05 06:11:08 PM PDT 24
Peak memory 201316 kb
Host smart-755ebf16-e2f2-4756-89d6-c04ec1580c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171363036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2171363036
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2217842285
Short name T424
Test name
Test status
Simulation time 5553400672 ps
CPU time 12.51 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:11:10 PM PDT 24
Peak memory 201384 kb
Host smart-dde37eed-6b9c-42ce-bbdd-225860e9c90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217842285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2217842285
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.978107706
Short name T290
Test name
Test status
Simulation time 209819081686 ps
CPU time 36.94 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:11:35 PM PDT 24
Peak memory 201512 kb
Host smart-941469ef-c791-497f-8104-1b566cbb44fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978107706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
978107706
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.518202744
Short name T23
Test name
Test status
Simulation time 40389555770 ps
CPU time 43.94 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:12:00 PM PDT 24
Peak memory 201560 kb
Host smart-f4874bd4-9fc1-48fc-b292-cfa6d56173ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518202744 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.518202744
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2476475201
Short name T366
Test name
Test status
Simulation time 490269310 ps
CPU time 0.93 seconds
Started Aug 05 06:11:06 PM PDT 24
Finished Aug 05 06:11:07 PM PDT 24
Peak memory 201252 kb
Host smart-96b2543d-83ee-453c-aa6e-0dae48cf7301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476475201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2476475201
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.526031398
Short name T454
Test name
Test status
Simulation time 171199146129 ps
CPU time 368.95 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:17:22 PM PDT 24
Peak memory 201520 kb
Host smart-120f6fe1-2960-4a65-aefc-d31a3789342b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526031398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.526031398
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.4172567313
Short name T261
Test name
Test status
Simulation time 189884483703 ps
CPU time 98.93 seconds
Started Aug 05 06:11:05 PM PDT 24
Finished Aug 05 06:12:44 PM PDT 24
Peak memory 201412 kb
Host smart-d96e152a-35ea-49f3-aa3d-b7f69f98537d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172567313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.4172567313
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.4115598397
Short name T316
Test name
Test status
Simulation time 162539442912 ps
CPU time 99 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:12:37 PM PDT 24
Peak memory 201420 kb
Host smart-2bd49d97-366b-4d11-88f2-d955f2c2fe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115598397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.4115598397
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2696383719
Short name T576
Test name
Test status
Simulation time 163796204321 ps
CPU time 382.46 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:17:17 PM PDT 24
Peak memory 201448 kb
Host smart-2dcf9759-8269-4c77-8950-b7e4ec23b02c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696383719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2696383719
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1006493772
Short name T603
Test name
Test status
Simulation time 164761254521 ps
CPU time 41.06 seconds
Started Aug 05 06:11:14 PM PDT 24
Finished Aug 05 06:11:55 PM PDT 24
Peak memory 201444 kb
Host smart-5d5f6169-5c76-4b31-8ccd-2e7406d9e3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006493772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1006493772
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2937361709
Short name T665
Test name
Test status
Simulation time 161831261113 ps
CPU time 81.64 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:12:34 PM PDT 24
Peak memory 201420 kb
Host smart-c974f7a9-bd61-4df8-bfb9-0bb356914305
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937361709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2937361709
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2797427843
Short name T614
Test name
Test status
Simulation time 359261822217 ps
CPU time 446.83 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:18:24 PM PDT 24
Peak memory 201468 kb
Host smart-ed566079-c64b-4fa0-a159-d33b384ae3b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797427843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2797427843
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2410140791
Short name T743
Test name
Test status
Simulation time 404827614577 ps
CPU time 241.5 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:14:56 PM PDT 24
Peak memory 201456 kb
Host smart-df68bca6-a331-4e6e-b277-a5a2f247cb7f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410140791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2410140791
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2867924757
Short name T46
Test name
Test status
Simulation time 118603649285 ps
CPU time 459.03 seconds
Started Aug 05 06:11:02 PM PDT 24
Finished Aug 05 06:18:42 PM PDT 24
Peak memory 201860 kb
Host smart-acfec9c9-19e3-4433-935d-c1ae7ca9113a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867924757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2867924757
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3245182260
Short name T543
Test name
Test status
Simulation time 27683545032 ps
CPU time 65.41 seconds
Started Aug 05 06:11:11 PM PDT 24
Finished Aug 05 06:12:16 PM PDT 24
Peak memory 201116 kb
Host smart-c72fa21d-e042-4103-bf51-12d60c86020c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245182260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3245182260
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1002554595
Short name T107
Test name
Test status
Simulation time 3466218798 ps
CPU time 1.93 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:10:59 PM PDT 24
Peak memory 201348 kb
Host smart-a063ca62-123b-49d9-a2f0-a9a8bf58d7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002554595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1002554595
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.744010917
Short name T190
Test name
Test status
Simulation time 5795928066 ps
CPU time 14.83 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:11:13 PM PDT 24
Peak memory 201260 kb
Host smart-39928840-6454-4ace-8d75-e06f8d98bf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744010917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.744010917
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1044852944
Short name T539
Test name
Test status
Simulation time 167618516598 ps
CPU time 160.55 seconds
Started Aug 05 06:11:03 PM PDT 24
Finished Aug 05 06:13:43 PM PDT 24
Peak memory 201440 kb
Host smart-6ca43242-995a-4968-ba66-a868adeae269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044852944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1044852944
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2887466792
Short name T278
Test name
Test status
Simulation time 60298380929 ps
CPU time 73.26 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:12:12 PM PDT 24
Peak memory 210176 kb
Host smart-5ebfd765-c043-4266-98c3-f03397106efe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887466792 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2887466792
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1729857418
Short name T429
Test name
Test status
Simulation time 321218989 ps
CPU time 1.28 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:10:58 PM PDT 24
Peak memory 201260 kb
Host smart-d15f5bec-44ec-4797-8589-6fda03fe2048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729857418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1729857418
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1986930421
Short name T547
Test name
Test status
Simulation time 480006924683 ps
CPU time 540.43 seconds
Started Aug 05 06:11:02 PM PDT 24
Finished Aug 05 06:20:03 PM PDT 24
Peak memory 201436 kb
Host smart-a9609084-d355-4c59-8b1f-4a532605c64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986930421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1986930421
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2389411671
Short name T449
Test name
Test status
Simulation time 167227759092 ps
CPU time 105.86 seconds
Started Aug 05 06:11:06 PM PDT 24
Finished Aug 05 06:12:52 PM PDT 24
Peak memory 201476 kb
Host smart-5fc3fe8a-1653-4426-bbfa-29275784b020
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389411671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2389411671
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1033847563
Short name T279
Test name
Test status
Simulation time 166339917557 ps
CPU time 369.93 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:17:08 PM PDT 24
Peak memory 201456 kb
Host smart-24bd406f-cf81-48e8-9a70-f07789b88124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033847563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1033847563
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.244432749
Short name T715
Test name
Test status
Simulation time 167720448173 ps
CPU time 50.06 seconds
Started Aug 05 06:11:08 PM PDT 24
Finished Aug 05 06:11:59 PM PDT 24
Peak memory 201416 kb
Host smart-18ddf94a-d51e-49a7-b4ea-21ed01a60ee3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=244432749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.244432749
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3384094009
Short name T767
Test name
Test status
Simulation time 190762649874 ps
CPU time 105.81 seconds
Started Aug 05 06:11:07 PM PDT 24
Finished Aug 05 06:12:53 PM PDT 24
Peak memory 201460 kb
Host smart-58e99840-19ee-45df-95b8-07214f979ca4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384094009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3384094009
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2858976199
Short name T525
Test name
Test status
Simulation time 594307937332 ps
CPU time 418.29 seconds
Started Aug 05 06:10:59 PM PDT 24
Finished Aug 05 06:17:57 PM PDT 24
Peak memory 201452 kb
Host smart-00ad382b-8e2f-4f42-a114-53622cebfa15
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858976199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2858976199
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3579214603
Short name T355
Test name
Test status
Simulation time 67231049615 ps
CPU time 350.19 seconds
Started Aug 05 06:11:06 PM PDT 24
Finished Aug 05 06:16:56 PM PDT 24
Peak memory 201900 kb
Host smart-ef19124b-7fbe-4db3-b572-3c30c3ac0b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579214603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3579214603
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.480485911
Short name T480
Test name
Test status
Simulation time 22691537066 ps
CPU time 50.96 seconds
Started Aug 05 06:11:04 PM PDT 24
Finished Aug 05 06:11:55 PM PDT 24
Peak memory 201376 kb
Host smart-f099765c-f9fe-4b5f-ba15-f9e0a308668d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480485911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.480485911
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3143415665
Short name T723
Test name
Test status
Simulation time 4318439384 ps
CPU time 3.71 seconds
Started Aug 05 06:10:56 PM PDT 24
Finished Aug 05 06:11:00 PM PDT 24
Peak memory 201352 kb
Host smart-1041f14a-b01a-42bf-8f98-d19533899b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143415665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3143415665
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4193345134
Short name T24
Test name
Test status
Simulation time 5666848978 ps
CPU time 2.09 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:11:15 PM PDT 24
Peak memory 201376 kb
Host smart-f0e645f5-0d9b-41f2-b431-0669b0ccb82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193345134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4193345134
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3249552351
Short name T786
Test name
Test status
Simulation time 165398613227 ps
CPU time 200.68 seconds
Started Aug 05 06:11:20 PM PDT 24
Finished Aug 05 06:14:41 PM PDT 24
Peak memory 201688 kb
Host smart-62fdb038-eac4-4838-b876-ef12fc59c1b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249552351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3249552351
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.117836015
Short name T588
Test name
Test status
Simulation time 93015084464 ps
CPU time 359.73 seconds
Started Aug 05 06:10:59 PM PDT 24
Finished Aug 05 06:16:59 PM PDT 24
Peak memory 210060 kb
Host smart-d5ff44b3-f9a5-42f8-840f-e2c7aba941f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117836015 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.117836015
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.667058270
Short name T378
Test name
Test status
Simulation time 438980924 ps
CPU time 0.83 seconds
Started Aug 05 06:11:20 PM PDT 24
Finished Aug 05 06:11:21 PM PDT 24
Peak memory 201200 kb
Host smart-a919bb26-0462-4f99-adf6-538d47494d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667058270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.667058270
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.628283443
Short name T168
Test name
Test status
Simulation time 185026945356 ps
CPU time 152.83 seconds
Started Aug 05 06:11:12 PM PDT 24
Finished Aug 05 06:13:45 PM PDT 24
Peak memory 201460 kb
Host smart-d78d56b1-bc48-4938-990a-063056051bd8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628283443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.628283443
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2004673574
Short name T254
Test name
Test status
Simulation time 161719932106 ps
CPU time 28.36 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:11:26 PM PDT 24
Peak memory 201468 kb
Host smart-7d7d1d47-dd63-4f76-975d-6d3c08306248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004673574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2004673574
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.28706658
Short name T695
Test name
Test status
Simulation time 491880490269 ps
CPU time 77.9 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:12:31 PM PDT 24
Peak memory 201456 kb
Host smart-cde4e864-420c-4775-b18d-3e29dc21bacc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=28706658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt
_fixed.28706658
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3757787902
Short name T667
Test name
Test status
Simulation time 165142513957 ps
CPU time 398.64 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:17:33 PM PDT 24
Peak memory 201460 kb
Host smart-61caa054-c364-4ecf-9e59-abce54d249fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757787902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3757787902
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3093972435
Short name T689
Test name
Test status
Simulation time 194338869946 ps
CPU time 111.19 seconds
Started Aug 05 06:11:12 PM PDT 24
Finished Aug 05 06:13:03 PM PDT 24
Peak memory 201452 kb
Host smart-9313b0bd-fd1f-4b5c-b1ce-76ca0b67c379
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093972435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3093972435
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3609970771
Short name T714
Test name
Test status
Simulation time 198733993394 ps
CPU time 122.42 seconds
Started Aug 05 06:11:20 PM PDT 24
Finished Aug 05 06:13:22 PM PDT 24
Peak memory 201396 kb
Host smart-e77e1e59-6e78-4cbe-ad48-fe3b822e7eb1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609970771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3609970771
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.410719816
Short name T353
Test name
Test status
Simulation time 134391281483 ps
CPU time 466.82 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:18:45 PM PDT 24
Peak memory 201848 kb
Host smart-a2c623e2-3f32-4f47-9d97-3524d8ae0bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410719816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.410719816
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1271760067
Short name T750
Test name
Test status
Simulation time 27610591489 ps
CPU time 52 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:12:05 PM PDT 24
Peak memory 201388 kb
Host smart-5a6ad885-cc40-44e4-bcf6-dce2634dbc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271760067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1271760067
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2604519547
Short name T481
Test name
Test status
Simulation time 4083050809 ps
CPU time 3.24 seconds
Started Aug 05 06:11:11 PM PDT 24
Finished Aug 05 06:11:14 PM PDT 24
Peak memory 201064 kb
Host smart-63376950-4a4f-42b3-b6cf-dfb9a720680e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604519547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2604519547
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2999478690
Short name T450
Test name
Test status
Simulation time 5840798587 ps
CPU time 4.25 seconds
Started Aug 05 06:11:09 PM PDT 24
Finished Aug 05 06:11:14 PM PDT 24
Peak memory 201388 kb
Host smart-4c289c76-8be2-44d6-be8a-74e58b3f6d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999478690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2999478690
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2373316995
Short name T169
Test name
Test status
Simulation time 640514954064 ps
CPU time 409.99 seconds
Started Aug 05 06:11:00 PM PDT 24
Finished Aug 05 06:17:50 PM PDT 24
Peak memory 201428 kb
Host smart-f179ca99-c252-4451-8e6b-547e12d5f6d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373316995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2373316995
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1519983667
Short name T755
Test name
Test status
Simulation time 385727648037 ps
CPU time 143.14 seconds
Started Aug 05 06:11:00 PM PDT 24
Finished Aug 05 06:13:23 PM PDT 24
Peak memory 210232 kb
Host smart-310785dc-4f47-4486-a32b-fc635681e32c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519983667 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1519983667
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.589300966
Short name T487
Test name
Test status
Simulation time 404654496 ps
CPU time 1.44 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:11:21 PM PDT 24
Peak memory 201248 kb
Host smart-35a1bb9d-ae57-40d4-b128-0fcefbc4ac4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589300966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.589300966
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2835360890
Short name T296
Test name
Test status
Simulation time 165423656005 ps
CPU time 351.9 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:17:05 PM PDT 24
Peak memory 201444 kb
Host smart-558330de-7cd9-4a42-9727-1757464e7590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835360890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2835360890
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.4001358190
Short name T270
Test name
Test status
Simulation time 332942189712 ps
CPU time 441.71 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:18:37 PM PDT 24
Peak memory 201440 kb
Host smart-f4eafe2a-52e2-4dc8-b187-6cc14e05a79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001358190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.4001358190
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1889813816
Short name T531
Test name
Test status
Simulation time 486891471077 ps
CPU time 1165.88 seconds
Started Aug 05 06:11:00 PM PDT 24
Finished Aug 05 06:30:26 PM PDT 24
Peak memory 201444 kb
Host smart-55fc3a31-7a13-4ae8-96b1-580899fe79ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889813816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1889813816
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.4115327587
Short name T252
Test name
Test status
Simulation time 163896917913 ps
CPU time 91.15 seconds
Started Aug 05 06:11:22 PM PDT 24
Finished Aug 05 06:12:53 PM PDT 24
Peak memory 201432 kb
Host smart-56d2fc06-b3a5-453b-8dc9-eb62fd57bb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115327587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.4115327587
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.285702578
Short name T395
Test name
Test status
Simulation time 163677955388 ps
CPU time 151.72 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:13:45 PM PDT 24
Peak memory 201456 kb
Host smart-c55686be-1679-41a1-978b-0845c71f5e3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=285702578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.285702578
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2419578983
Short name T240
Test name
Test status
Simulation time 165656732255 ps
CPU time 360.5 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:17:16 PM PDT 24
Peak memory 201432 kb
Host smart-8e0be868-c4f4-4b78-aaea-0f54484da26b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419578983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2419578983
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2741031665
Short name T578
Test name
Test status
Simulation time 115576322559 ps
CPU time 369.09 seconds
Started Aug 05 06:11:03 PM PDT 24
Finished Aug 05 06:17:12 PM PDT 24
Peak memory 201840 kb
Host smart-7516472b-af11-48c4-9eea-4e3afd676e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741031665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2741031665
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1133535591
Short name T439
Test name
Test status
Simulation time 46933077994 ps
CPU time 28.52 seconds
Started Aug 05 06:11:10 PM PDT 24
Finished Aug 05 06:11:39 PM PDT 24
Peak memory 201336 kb
Host smart-70abb59d-443a-4303-aeda-89d33096e67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133535591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1133535591
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.40620736
Short name T361
Test name
Test status
Simulation time 5093130760 ps
CPU time 1.45 seconds
Started Aug 05 06:11:14 PM PDT 24
Finished Aug 05 06:11:15 PM PDT 24
Peak memory 201356 kb
Host smart-ced8e46a-bfd3-4cc6-9df6-496038f5fd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40620736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.40620736
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1728942056
Short name T688
Test name
Test status
Simulation time 5640053927 ps
CPU time 13.15 seconds
Started Aug 05 06:11:22 PM PDT 24
Finished Aug 05 06:11:35 PM PDT 24
Peak memory 201348 kb
Host smart-b4ea64b7-62c0-4184-9b6c-4d3bcce16811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728942056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1728942056
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1109910585
Short name T632
Test name
Test status
Simulation time 209192576838 ps
CPU time 127.27 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:13:04 PM PDT 24
Peak memory 201492 kb
Host smart-f2366ae6-6686-4910-bb3c-7cb7cb4bb1c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109910585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1109910585
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.882296364
Short name T109
Test name
Test status
Simulation time 314556939352 ps
CPU time 282.08 seconds
Started Aug 05 06:11:20 PM PDT 24
Finished Aug 05 06:16:03 PM PDT 24
Peak memory 217492 kb
Host smart-a310f536-db8d-4aca-89d8-bb612e4e9e34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882296364 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.882296364
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2702384339
Short name T29
Test name
Test status
Simulation time 504749242 ps
CPU time 0.92 seconds
Started Aug 05 06:11:05 PM PDT 24
Finished Aug 05 06:11:06 PM PDT 24
Peak memory 201260 kb
Host smart-580e8d8c-13ff-4da6-8a76-225702867e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702384339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2702384339
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1246349643
Short name T223
Test name
Test status
Simulation time 166040654334 ps
CPU time 359.91 seconds
Started Aug 05 06:11:22 PM PDT 24
Finished Aug 05 06:17:22 PM PDT 24
Peak memory 201500 kb
Host smart-cac85411-1efc-4f93-8fce-308d3183178e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246349643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1246349643
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.856504713
Short name T289
Test name
Test status
Simulation time 370591426456 ps
CPU time 420.42 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:18:18 PM PDT 24
Peak memory 201476 kb
Host smart-0f06c05a-a6b6-4bc8-acb2-35d3bb2c66af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856504713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.856504713
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.424016897
Short name T423
Test name
Test status
Simulation time 164715030836 ps
CPU time 397.58 seconds
Started Aug 05 06:11:01 PM PDT 24
Finished Aug 05 06:17:39 PM PDT 24
Peak memory 201512 kb
Host smart-2488d2c8-a591-40dd-bad8-8524aaf33ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424016897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.424016897
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.4162451875
Short name T555
Test name
Test status
Simulation time 330564711381 ps
CPU time 197.47 seconds
Started Aug 05 06:11:08 PM PDT 24
Finished Aug 05 06:14:25 PM PDT 24
Peak memory 201448 kb
Host smart-7b24332a-aaaf-45c8-ae4c-fd1f3c58b876
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162451875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.4162451875
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1518023803
Short name T340
Test name
Test status
Simulation time 487319436584 ps
CPU time 1084.2 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:29:23 PM PDT 24
Peak memory 201452 kb
Host smart-61457a36-e17f-43ac-aa48-d7bbfc8c46f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518023803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1518023803
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.459162612
Short name T474
Test name
Test status
Simulation time 493467007464 ps
CPU time 275.34 seconds
Started Aug 05 06:11:04 PM PDT 24
Finished Aug 05 06:15:40 PM PDT 24
Peak memory 201452 kb
Host smart-2fbca17c-c291-4909-b4d3-ce696258f3d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=459162612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.459162612
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3309292171
Short name T741
Test name
Test status
Simulation time 193490185468 ps
CPU time 136.85 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:13:32 PM PDT 24
Peak memory 201472 kb
Host smart-af84c4a4-a889-4453-b118-84799339bbaa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309292171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3309292171
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4265131840
Short name T354
Test name
Test status
Simulation time 120927087816 ps
CPU time 402.7 seconds
Started Aug 05 06:11:22 PM PDT 24
Finished Aug 05 06:18:04 PM PDT 24
Peak memory 201836 kb
Host smart-1e050085-b710-4a9a-a1fc-b2a78d18ee69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265131840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4265131840
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.77572856
Short name T93
Test name
Test status
Simulation time 38239599197 ps
CPU time 22.95 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:11:20 PM PDT 24
Peak memory 201356 kb
Host smart-75ddf142-ec9f-4ab2-a0c7-2e276771f9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77572856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.77572856
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3801965637
Short name T793
Test name
Test status
Simulation time 5043828181 ps
CPU time 2.93 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:11:20 PM PDT 24
Peak memory 201376 kb
Host smart-95edd6c3-1159-497c-85ad-b3c46d5b4a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801965637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3801965637
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1552588126
Short name T532
Test name
Test status
Simulation time 6235813798 ps
CPU time 13.75 seconds
Started Aug 05 06:11:14 PM PDT 24
Finished Aug 05 06:11:27 PM PDT 24
Peak memory 201372 kb
Host smart-a11887f1-138b-43d8-ba81-1c87c1311b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552588126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1552588126
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2555403771
Short name T520
Test name
Test status
Simulation time 31088822653 ps
CPU time 17.47 seconds
Started Aug 05 06:11:20 PM PDT 24
Finished Aug 05 06:11:37 PM PDT 24
Peak memory 201376 kb
Host smart-2042fdd6-381b-4534-aae7-8da97f3a5266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555403771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2555403771
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.118606044
Short name T598
Test name
Test status
Simulation time 16320398191 ps
CPU time 33.22 seconds
Started Aug 05 06:11:24 PM PDT 24
Finished Aug 05 06:11:58 PM PDT 24
Peak memory 209896 kb
Host smart-a1d93afe-15b6-4e55-b99d-d7cebe7a2b82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118606044 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.118606044
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.783894136
Short name T518
Test name
Test status
Simulation time 501180616 ps
CPU time 0.73 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:11:14 PM PDT 24
Peak memory 201236 kb
Host smart-6931455e-9827-44a5-a562-89aaf33817f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783894136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.783894136
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.4058746630
Short name T97
Test name
Test status
Simulation time 378541396931 ps
CPU time 207.45 seconds
Started Aug 05 06:11:02 PM PDT 24
Finished Aug 05 06:14:30 PM PDT 24
Peak memory 201500 kb
Host smart-83085ec6-a863-43c1-9142-9c612b31ca71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058746630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.4058746630
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1487154390
Short name T697
Test name
Test status
Simulation time 169304958062 ps
CPU time 113.6 seconds
Started Aug 05 06:11:08 PM PDT 24
Finished Aug 05 06:13:01 PM PDT 24
Peak memory 201472 kb
Host smart-066a3721-8fcf-434a-a67a-84e9a27db0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487154390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1487154390
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1820575592
Short name T79
Test name
Test status
Simulation time 500335706141 ps
CPU time 288.96 seconds
Started Aug 05 06:11:10 PM PDT 24
Finished Aug 05 06:15:59 PM PDT 24
Peak memory 201452 kb
Host smart-0689cdec-1b14-492f-9e20-6b585b45379b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820575592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1820575592
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1405656748
Short name T201
Test name
Test status
Simulation time 487233272793 ps
CPU time 271.57 seconds
Started Aug 05 06:11:05 PM PDT 24
Finished Aug 05 06:15:37 PM PDT 24
Peak memory 201456 kb
Host smart-40a7ac76-c497-4059-acb1-b5911b14e5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405656748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1405656748
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2805970263
Short name T769
Test name
Test status
Simulation time 495756007958 ps
CPU time 303.67 seconds
Started Aug 05 06:11:14 PM PDT 24
Finished Aug 05 06:16:18 PM PDT 24
Peak memory 201436 kb
Host smart-3f9eb3a5-7121-41f8-a15b-4aeb5ecc2d08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805970263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2805970263
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1024429761
Short name T572
Test name
Test status
Simulation time 184168368917 ps
CPU time 193.09 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:14:33 PM PDT 24
Peak memory 201448 kb
Host smart-ea089d8b-3d37-4256-8868-05f47e46e62b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024429761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1024429761
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.706767727
Short name T156
Test name
Test status
Simulation time 190007992923 ps
CPU time 36.04 seconds
Started Aug 05 06:11:07 PM PDT 24
Finished Aug 05 06:11:43 PM PDT 24
Peak memory 201436 kb
Host smart-882f9971-900a-424e-a659-911decd7aee5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706767727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.706767727
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3124860779
Short name T206
Test name
Test status
Simulation time 128949620911 ps
CPU time 443.93 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:18:37 PM PDT 24
Peak memory 201828 kb
Host smart-d24c69a6-2fc9-4ef2-8792-13dcb3fd1202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124860779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3124860779
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1609838197
Short name T680
Test name
Test status
Simulation time 31911951313 ps
CPU time 66.1 seconds
Started Aug 05 06:11:14 PM PDT 24
Finished Aug 05 06:12:20 PM PDT 24
Peak memory 201324 kb
Host smart-a0aec575-5663-458c-8da2-6bc5ac73ba50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609838197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1609838197
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3839001510
Short name T730
Test name
Test status
Simulation time 4413723086 ps
CPU time 10.2 seconds
Started Aug 05 06:11:14 PM PDT 24
Finished Aug 05 06:11:24 PM PDT 24
Peak memory 201372 kb
Host smart-6e4c5531-f7a5-4dc8-b0e3-2ae6a7070735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839001510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3839001510
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1243059196
Short name T372
Test name
Test status
Simulation time 5651874032 ps
CPU time 4.05 seconds
Started Aug 05 06:11:04 PM PDT 24
Finished Aug 05 06:11:08 PM PDT 24
Peak memory 201376 kb
Host smart-0b9cf043-86bc-4e2a-a53c-c9d194facdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243059196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1243059196
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2489555016
Short name T757
Test name
Test status
Simulation time 422507634552 ps
CPU time 63.23 seconds
Started Aug 05 06:11:22 PM PDT 24
Finished Aug 05 06:12:25 PM PDT 24
Peak memory 201464 kb
Host smart-148ecead-0c1e-4da3-bdcc-77095fb2f47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489555016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2489555016
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.868866192
Short name T199
Test name
Test status
Simulation time 21340570507 ps
CPU time 60.55 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:12:17 PM PDT 24
Peak memory 210156 kb
Host smart-2ec49bea-571e-4d96-861b-5cac1c9229a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868866192 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.868866192
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3960880693
Short name T556
Test name
Test status
Simulation time 516729175 ps
CPU time 1.2 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:11:17 PM PDT 24
Peak memory 201244 kb
Host smart-df41f9ac-e8ed-47e0-888c-61b60f523bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960880693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3960880693
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2149585716
Short name T558
Test name
Test status
Simulation time 175082225087 ps
CPU time 134.99 seconds
Started Aug 05 06:11:12 PM PDT 24
Finished Aug 05 06:13:27 PM PDT 24
Peak memory 201512 kb
Host smart-19521ee9-667c-4dd6-b178-4e91f6062d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149585716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2149585716
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1579937854
Short name T154
Test name
Test status
Simulation time 321282163038 ps
CPU time 325.38 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:16:41 PM PDT 24
Peak memory 201512 kb
Host smart-9e5948b7-e84f-4bc5-84fd-9e27a3913084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579937854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1579937854
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3787883216
Short name T411
Test name
Test status
Simulation time 491176413021 ps
CPU time 1043.35 seconds
Started Aug 05 06:11:12 PM PDT 24
Finished Aug 05 06:28:36 PM PDT 24
Peak memory 201508 kb
Host smart-85e7b5e5-b67a-431e-914a-e3a6c78f2115
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787883216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3787883216
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.4002183873
Short name T735
Test name
Test status
Simulation time 493447927726 ps
CPU time 1178.68 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:30:53 PM PDT 24
Peak memory 201476 kb
Host smart-235860ac-d816-487b-9e4b-20028cd687e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002183873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.4002183873
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2585561307
Short name T239
Test name
Test status
Simulation time 359933408410 ps
CPU time 783.05 seconds
Started Aug 05 06:11:11 PM PDT 24
Finished Aug 05 06:24:14 PM PDT 24
Peak memory 201484 kb
Host smart-aa324102-7b17-4bd8-936c-7b78a2688cf6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585561307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2585561307
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3153764207
Short name T260
Test name
Test status
Simulation time 200831340278 ps
CPU time 231.87 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:15:05 PM PDT 24
Peak memory 201468 kb
Host smart-fec4acbc-c3e3-488f-9602-3dd989332558
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153764207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3153764207
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2726076329
Short name T774
Test name
Test status
Simulation time 45037333487 ps
CPU time 23.27 seconds
Started Aug 05 06:11:23 PM PDT 24
Finished Aug 05 06:11:46 PM PDT 24
Peak memory 201380 kb
Host smart-ceb18e18-a3da-443b-9fc9-fce7fee7f35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726076329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2726076329
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3180158086
Short name T684
Test name
Test status
Simulation time 3385595977 ps
CPU time 2.35 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:11:16 PM PDT 24
Peak memory 201344 kb
Host smart-a3f69609-2dfb-4ed2-a770-8d36ed93b5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180158086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3180158086
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.927342545
Short name T382
Test name
Test status
Simulation time 5645721342 ps
CPU time 3.85 seconds
Started Aug 05 06:11:12 PM PDT 24
Finished Aug 05 06:11:16 PM PDT 24
Peak memory 201356 kb
Host smart-dddcbd06-5764-4f23-aed3-9051694f5e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927342545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.927342545
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.4061503831
Short name T271
Test name
Test status
Simulation time 498767067269 ps
CPU time 1078.68 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:29:15 PM PDT 24
Peak memory 201428 kb
Host smart-3fbeebaa-3a17-4a4f-ab6d-3aadd7d3d7b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061503831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.4061503831
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3870732395
Short name T413
Test name
Test status
Simulation time 344506118 ps
CPU time 1 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:10:29 PM PDT 24
Peak memory 201248 kb
Host smart-44fc7c69-1f7e-4d82-928b-853301c67ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870732395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3870732395
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.4008214581
Short name T226
Test name
Test status
Simulation time 541001698852 ps
CPU time 1063.94 seconds
Started Aug 05 06:10:20 PM PDT 24
Finished Aug 05 06:28:05 PM PDT 24
Peak memory 201352 kb
Host smart-68354e2c-203f-43d5-8af3-c106aaa88278
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008214581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.4008214581
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1118671952
Short name T113
Test name
Test status
Simulation time 354275057171 ps
CPU time 114.73 seconds
Started Aug 05 06:10:32 PM PDT 24
Finished Aug 05 06:12:27 PM PDT 24
Peak memory 200812 kb
Host smart-5237b323-894d-4d13-866f-671f30e68c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118671952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1118671952
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1615723148
Short name T765
Test name
Test status
Simulation time 166952280540 ps
CPU time 174.8 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:13:23 PM PDT 24
Peak memory 201536 kb
Host smart-63b5abad-7cd1-4b10-922b-bde6101b2752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615723148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1615723148
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1737746365
Short name T422
Test name
Test status
Simulation time 164446832083 ps
CPU time 199.51 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:13:47 PM PDT 24
Peak memory 201472 kb
Host smart-a7dcd81d-66ca-48db-8dda-e7412d395ff1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737746365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1737746365
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1540896978
Short name T643
Test name
Test status
Simulation time 166418792170 ps
CPU time 361.21 seconds
Started Aug 05 06:10:23 PM PDT 24
Finished Aug 05 06:16:25 PM PDT 24
Peak memory 201396 kb
Host smart-22730f28-e8f4-4360-abb7-dfa72bfe817d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540896978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1540896978
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.288893217
Short name T102
Test name
Test status
Simulation time 487358275065 ps
CPU time 266.12 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:14:55 PM PDT 24
Peak memory 201440 kb
Host smart-1b59c667-8696-49c2-876b-4ae989f3de7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=288893217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.288893217
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3903523984
Short name T344
Test name
Test status
Simulation time 550106653235 ps
CPU time 1301.28 seconds
Started Aug 05 06:10:37 PM PDT 24
Finished Aug 05 06:32:18 PM PDT 24
Peak memory 201468 kb
Host smart-4a4d085d-c8c9-4027-acec-21c5ecb2b6d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903523984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3903523984
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.116169037
Short name T484
Test name
Test status
Simulation time 594360845130 ps
CPU time 1289.59 seconds
Started Aug 05 06:10:26 PM PDT 24
Finished Aug 05 06:31:56 PM PDT 24
Peak memory 201432 kb
Host smart-90d6b2b1-8101-4d05-8a8d-759ee6107e10
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116169037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.116169037
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3277838083
Short name T358
Test name
Test status
Simulation time 118305047852 ps
CPU time 571.81 seconds
Started Aug 05 06:10:17 PM PDT 24
Finished Aug 05 06:19:49 PM PDT 24
Peak memory 201888 kb
Host smart-32efcdbc-31e9-495f-81e3-75cfe0d3c424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277838083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3277838083
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2391892770
Short name T187
Test name
Test status
Simulation time 44680751141 ps
CPU time 107.48 seconds
Started Aug 05 06:10:26 PM PDT 24
Finished Aug 05 06:12:14 PM PDT 24
Peak memory 201352 kb
Host smart-6e13581e-26ea-45a5-94a8-99ce6448fb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391892770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2391892770
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2009225291
Short name T391
Test name
Test status
Simulation time 4200720229 ps
CPU time 2.08 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:10:29 PM PDT 24
Peak memory 201336 kb
Host smart-b4f8ad50-c713-46c9-8513-7e8862c0f5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009225291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2009225291
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4262472608
Short name T593
Test name
Test status
Simulation time 5805329091 ps
CPU time 4.42 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:10:32 PM PDT 24
Peak memory 201372 kb
Host smart-3a786ea1-39c2-459e-ab00-a4204cdaa50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262472608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4262472608
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2336040952
Short name T476
Test name
Test status
Simulation time 168951012747 ps
CPU time 394.86 seconds
Started Aug 05 06:10:29 PM PDT 24
Finished Aug 05 06:17:04 PM PDT 24
Peak memory 201436 kb
Host smart-ebe26fc9-ba8a-492e-ac64-8027d0b96ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336040952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2336040952
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3815507244
Short name T359
Test name
Test status
Simulation time 297895891 ps
CPU time 1.3 seconds
Started Aug 05 06:11:18 PM PDT 24
Finished Aug 05 06:11:19 PM PDT 24
Peak memory 201232 kb
Host smart-20245d66-a4b3-4665-8b9d-968782f2425c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815507244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3815507244
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3310854347
Short name T238
Test name
Test status
Simulation time 162606531137 ps
CPU time 92.98 seconds
Started Aug 05 06:11:20 PM PDT 24
Finished Aug 05 06:12:53 PM PDT 24
Peak memory 201456 kb
Host smart-488ed2c5-2c68-44a7-b2bf-c4b6d009d336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310854347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3310854347
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3759996730
Short name T482
Test name
Test status
Simulation time 486615885374 ps
CPU time 534.03 seconds
Started Aug 05 06:11:09 PM PDT 24
Finished Aug 05 06:20:03 PM PDT 24
Peak memory 201448 kb
Host smart-ff7294c8-090d-43d2-b17d-107c6261200b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759996730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3759996730
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2945010729
Short name T10
Test name
Test status
Simulation time 485586938612 ps
CPU time 680.48 seconds
Started Aug 05 06:11:12 PM PDT 24
Finished Aug 05 06:22:33 PM PDT 24
Peak memory 201440 kb
Host smart-8f051d1f-eedc-4aa7-87a5-de395163f0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945010729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2945010729
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2824922915
Short name T368
Test name
Test status
Simulation time 494868068888 ps
CPU time 299.28 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:16:15 PM PDT 24
Peak memory 201404 kb
Host smart-5f51c6e4-5e32-4b91-b619-e3705d05831b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824922915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2824922915
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3670926562
Short name T200
Test name
Test status
Simulation time 679610698617 ps
CPU time 388.83 seconds
Started Aug 05 06:11:10 PM PDT 24
Finished Aug 05 06:17:39 PM PDT 24
Peak memory 201440 kb
Host smart-7815a31d-73df-452e-af4c-4a16bebd8f62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670926562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3670926562
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2776708075
Short name T451
Test name
Test status
Simulation time 400181671999 ps
CPU time 478.66 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:19:14 PM PDT 24
Peak memory 201520 kb
Host smart-17f770dd-ea36-406c-b1fc-3892ce73f768
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776708075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2776708075
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2516052995
Short name T86
Test name
Test status
Simulation time 79792922949 ps
CPU time 394.63 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:17:54 PM PDT 24
Peak memory 201848 kb
Host smart-7d376249-e0b1-4aab-b752-205ba0e8ee31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516052995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2516052995
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1661646142
Short name T624
Test name
Test status
Simulation time 36859264236 ps
CPU time 42.17 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:12:01 PM PDT 24
Peak memory 201352 kb
Host smart-495ea1c6-a7f4-4cf1-b862-80200ccf6271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661646142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1661646142
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1072169111
Short name T91
Test name
Test status
Simulation time 4025800949 ps
CPU time 3.18 seconds
Started Aug 05 06:11:11 PM PDT 24
Finished Aug 05 06:11:14 PM PDT 24
Peak memory 201356 kb
Host smart-6ba614bd-f332-4336-b6d0-4a2a85fc5f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072169111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1072169111
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1961405813
Short name T696
Test name
Test status
Simulation time 5966368597 ps
CPU time 15 seconds
Started Aug 05 06:11:09 PM PDT 24
Finished Aug 05 06:11:24 PM PDT 24
Peak memory 201388 kb
Host smart-9431efe6-0529-4d3d-a754-179a20c6416a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961405813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1961405813
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.697052939
Short name T780
Test name
Test status
Simulation time 347816779064 ps
CPU time 222.08 seconds
Started Aug 05 06:11:10 PM PDT 24
Finished Aug 05 06:14:52 PM PDT 24
Peak memory 201444 kb
Host smart-f5d6b79b-99bc-4126-bba1-776568232488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697052939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
697052939
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1934623003
Short name T604
Test name
Test status
Simulation time 544020957 ps
CPU time 0.91 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:11:18 PM PDT 24
Peak memory 201224 kb
Host smart-1e4a7c22-136d-4ddd-bc1f-11789a9bd020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934623003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1934623003
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3685090592
Short name T553
Test name
Test status
Simulation time 336342491408 ps
CPU time 402.64 seconds
Started Aug 05 06:11:14 PM PDT 24
Finished Aug 05 06:17:56 PM PDT 24
Peak memory 201440 kb
Host smart-85668848-3b52-4334-9654-3cf292c9d5b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685090592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3685090592
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1191928830
Short name T526
Test name
Test status
Simulation time 169427301497 ps
CPU time 151.83 seconds
Started Aug 05 06:11:09 PM PDT 24
Finished Aug 05 06:13:41 PM PDT 24
Peak memory 201464 kb
Host smart-9ef4f1f8-4255-47eb-8c46-2edeca31d48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191928830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1191928830
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3724258685
Short name T446
Test name
Test status
Simulation time 493057457453 ps
CPU time 574.87 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:20:51 PM PDT 24
Peak memory 201436 kb
Host smart-921b23ff-015a-4b94-b5dc-6f7e7c7cb7db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724258685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3724258685
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.325944743
Short name T782
Test name
Test status
Simulation time 494424204323 ps
CPU time 1211.87 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:31:27 PM PDT 24
Peak memory 201468 kb
Host smart-ba798540-5190-4edc-b52d-fc073f590539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325944743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.325944743
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3404270499
Short name T574
Test name
Test status
Simulation time 491557212296 ps
CPU time 1159.19 seconds
Started Aug 05 06:11:08 PM PDT 24
Finished Aug 05 06:30:27 PM PDT 24
Peak memory 201376 kb
Host smart-1a04b354-7f15-49fa-aae6-b48648cffb79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404270499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3404270499
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.492879909
Short name T241
Test name
Test status
Simulation time 598995632921 ps
CPU time 1398.6 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:34:36 PM PDT 24
Peak memory 201516 kb
Host smart-6b567f00-1647-4abc-b6f8-46e7ad79fb3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492879909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.492879909
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3438960288
Short name T472
Test name
Test status
Simulation time 615276440178 ps
CPU time 698.83 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:22:56 PM PDT 24
Peak memory 201460 kb
Host smart-42362279-818b-4645-bee6-f14079234554
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438960288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3438960288
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3773122847
Short name T356
Test name
Test status
Simulation time 144170247430 ps
CPU time 742.6 seconds
Started Aug 05 06:11:12 PM PDT 24
Finished Aug 05 06:23:35 PM PDT 24
Peak memory 201836 kb
Host smart-d48ee54b-5c30-402a-91f6-5fc5807cd05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773122847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3773122847
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1458807285
Short name T650
Test name
Test status
Simulation time 25842327417 ps
CPU time 15.74 seconds
Started Aug 05 06:11:14 PM PDT 24
Finished Aug 05 06:11:30 PM PDT 24
Peak memory 201324 kb
Host smart-a571205e-c033-42ac-ac2f-beec3d30195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458807285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1458807285
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1258699589
Short name T785
Test name
Test status
Simulation time 3772531988 ps
CPU time 5.14 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:11:24 PM PDT 24
Peak memory 201360 kb
Host smart-eff5c55a-0edc-4b56-8cd2-86b6fa54529c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258699589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1258699589
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1869947390
Short name T686
Test name
Test status
Simulation time 6020621476 ps
CPU time 3.89 seconds
Started Aug 05 06:11:22 PM PDT 24
Finished Aug 05 06:11:26 PM PDT 24
Peak memory 201388 kb
Host smart-a2b172bb-6b9a-46e3-9a9f-d3d22dcb2517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869947390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1869947390
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.425894726
Short name T613
Test name
Test status
Simulation time 349180348525 ps
CPU time 742.31 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:23:38 PM PDT 24
Peak memory 211104 kb
Host smart-7f32aaa5-e6b6-470b-aa2c-c9724d8fd570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425894726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
425894726
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2579902285
Short name T38
Test name
Test status
Simulation time 48765448718 ps
CPU time 213.76 seconds
Started Aug 05 06:11:12 PM PDT 24
Finished Aug 05 06:14:46 PM PDT 24
Peak memory 210188 kb
Host smart-d2fa10c5-e9a3-43f4-b1b1-590882b866f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579902285 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2579902285
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3504281720
Short name T581
Test name
Test status
Simulation time 489430027 ps
CPU time 1.15 seconds
Started Aug 05 06:11:20 PM PDT 24
Finished Aug 05 06:11:21 PM PDT 24
Peak memory 201200 kb
Host smart-f3c4b333-f804-4b49-8c15-1a536fa5dded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504281720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3504281720
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2854960364
Short name T195
Test name
Test status
Simulation time 563855467386 ps
CPU time 943.47 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:26:57 PM PDT 24
Peak memory 201460 kb
Host smart-36508385-7319-4b34-9a3f-8d51708d18d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854960364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2854960364
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1392602816
Short name T227
Test name
Test status
Simulation time 333030256228 ps
CPU time 420.14 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:18:20 PM PDT 24
Peak memory 201448 kb
Host smart-14c7c7cc-5bdf-4ea3-b664-f8e6fd4ca8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392602816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1392602816
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2045591502
Short name T301
Test name
Test status
Simulation time 162216681867 ps
CPU time 34.42 seconds
Started Aug 05 06:11:18 PM PDT 24
Finished Aug 05 06:11:52 PM PDT 24
Peak memory 201464 kb
Host smart-51f43ea6-4947-41d2-9124-284a09f45f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045591502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2045591502
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1189586405
Short name T384
Test name
Test status
Simulation time 489958090719 ps
CPU time 1195.69 seconds
Started Aug 05 06:11:18 PM PDT 24
Finished Aug 05 06:31:14 PM PDT 24
Peak memory 201424 kb
Host smart-4b2ce745-ff1e-47c3-a5a9-6bda3506de6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189586405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1189586405
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3026321117
Short name T666
Test name
Test status
Simulation time 163092780227 ps
CPU time 369.09 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:17:26 PM PDT 24
Peak memory 201416 kb
Host smart-c27a8ae5-9818-49f9-817e-1781b8ecc4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026321117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3026321117
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3853186544
Short name T668
Test name
Test status
Simulation time 489730643701 ps
CPU time 281.59 seconds
Started Aug 05 06:11:21 PM PDT 24
Finished Aug 05 06:16:02 PM PDT 24
Peak memory 201440 kb
Host smart-c19c9c96-0861-4862-b628-642cce318a94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853186544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3853186544
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1521173472
Short name T334
Test name
Test status
Simulation time 182336626092 ps
CPU time 128 seconds
Started Aug 05 06:11:10 PM PDT 24
Finished Aug 05 06:13:18 PM PDT 24
Peak memory 201544 kb
Host smart-2f48736b-ee9e-4bed-a142-b69b0f713fc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521173472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1521173472
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.4044242033
Short name T542
Test name
Test status
Simulation time 205905242755 ps
CPU time 102.17 seconds
Started Aug 05 06:11:23 PM PDT 24
Finished Aug 05 06:13:05 PM PDT 24
Peak memory 201448 kb
Host smart-2a9bbcb6-81f6-4d29-983b-f9a5032366bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044242033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.4044242033
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1770091411
Short name T351
Test name
Test status
Simulation time 109495903225 ps
CPU time 607.32 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:21:25 PM PDT 24
Peak memory 201848 kb
Host smart-33470e1e-38de-4ecd-ae7d-b67ef144eb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770091411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1770091411
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1662117568
Short name T371
Test name
Test status
Simulation time 31358415167 ps
CPU time 60.09 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:12:19 PM PDT 24
Peak memory 201448 kb
Host smart-857a429f-68e3-4956-befe-e83b33932191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662117568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1662117568
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1910244372
Short name T468
Test name
Test status
Simulation time 3856953158 ps
CPU time 1.35 seconds
Started Aug 05 06:11:18 PM PDT 24
Finished Aug 05 06:11:19 PM PDT 24
Peak memory 201324 kb
Host smart-cf56e77e-df40-4b92-bd4b-b938ba912f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910244372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1910244372
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2255023404
Short name T538
Test name
Test status
Simulation time 5802612146 ps
CPU time 1.5 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:11:18 PM PDT 24
Peak memory 201384 kb
Host smart-cf07369a-130d-4d9b-a5ce-9b0ecf32c049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255023404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2255023404
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.25721987
Short name T44
Test name
Test status
Simulation time 387418360022 ps
CPU time 490.3 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:19:24 PM PDT 24
Peak memory 201396 kb
Host smart-7f063a90-65dd-498d-a26d-a5e289aa328d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25721987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.25721987
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3365110550
Short name T281
Test name
Test status
Simulation time 72081190083 ps
CPU time 84.24 seconds
Started Aug 05 06:11:20 PM PDT 24
Finished Aug 05 06:12:44 PM PDT 24
Peak memory 218384 kb
Host smart-8bf73cd5-59c0-4267-8292-467bc07a1188
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365110550 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3365110550
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3392365694
Short name T522
Test name
Test status
Simulation time 431740751 ps
CPU time 0.92 seconds
Started Aug 05 06:11:11 PM PDT 24
Finished Aug 05 06:11:12 PM PDT 24
Peak memory 201252 kb
Host smart-a2492c64-4c7f-4414-835e-5f2cd0ba22ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392365694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3392365694
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3601920037
Short name T258
Test name
Test status
Simulation time 185793158156 ps
CPU time 429.74 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:18:27 PM PDT 24
Peak memory 201448 kb
Host smart-28d8773d-0906-48c6-aee1-89c8bb3d6bc3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601920037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3601920037
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1125122319
Short name T265
Test name
Test status
Simulation time 203600419783 ps
CPU time 475.6 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:19:11 PM PDT 24
Peak memory 201464 kb
Host smart-a03f9f66-baba-4059-b374-9e878da12653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125122319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1125122319
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2432767081
Short name T596
Test name
Test status
Simulation time 323921512300 ps
CPU time 323.01 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:16:40 PM PDT 24
Peak memory 201388 kb
Host smart-247f5d8e-0c82-4905-ad47-97cacb269426
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432767081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2432767081
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3635333299
Short name T181
Test name
Test status
Simulation time 481319106283 ps
CPU time 285.33 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:16:04 PM PDT 24
Peak memory 201452 kb
Host smart-dcbf5888-2c9c-40e2-9798-b8b9467ffe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635333299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3635333299
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3647710630
Short name T489
Test name
Test status
Simulation time 492670087931 ps
CPU time 310.44 seconds
Started Aug 05 06:11:27 PM PDT 24
Finished Aug 05 06:16:37 PM PDT 24
Peak memory 201404 kb
Host smart-b5ca6ccd-27d7-4406-b5f4-09ff51f0b0ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647710630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3647710630
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3146800691
Short name T152
Test name
Test status
Simulation time 544908776013 ps
CPU time 1169.6 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:30:45 PM PDT 24
Peak memory 201396 kb
Host smart-66a0d14c-2aa3-41b5-b2ca-5d738f378d46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146800691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3146800691
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1556411235
Short name T569
Test name
Test status
Simulation time 392631294105 ps
CPU time 799.51 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:24:36 PM PDT 24
Peak memory 201460 kb
Host smart-56796d01-baaf-4be3-baa5-19736f0e1c73
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556411235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1556411235
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4279068101
Short name T208
Test name
Test status
Simulation time 137710138301 ps
CPU time 705.96 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:23:00 PM PDT 24
Peak memory 201764 kb
Host smart-09facb58-668f-4b4c-91ec-622f04b65cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279068101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4279068101
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2950177776
Short name T770
Test name
Test status
Simulation time 24778045555 ps
CPU time 6.04 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:11:25 PM PDT 24
Peak memory 201340 kb
Host smart-fb4c32f0-87f4-4232-a8a2-6056e96dd181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950177776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2950177776
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.217773799
Short name T528
Test name
Test status
Simulation time 4061545278 ps
CPU time 3.29 seconds
Started Aug 05 06:11:18 PM PDT 24
Finished Aug 05 06:11:21 PM PDT 24
Peak memory 201352 kb
Host smart-d9996caf-d7c5-4ef8-83cc-71d4c01cf5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217773799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.217773799
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1916381335
Short name T432
Test name
Test status
Simulation time 6067399431 ps
CPU time 6.74 seconds
Started Aug 05 06:11:14 PM PDT 24
Finished Aug 05 06:11:21 PM PDT 24
Peak memory 201368 kb
Host smart-0d42ae14-cde8-4809-8a38-5280a67c638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916381335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1916381335
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.260748978
Short name T595
Test name
Test status
Simulation time 6442022806 ps
CPU time 15.24 seconds
Started Aug 05 06:11:12 PM PDT 24
Finished Aug 05 06:11:27 PM PDT 24
Peak memory 201540 kb
Host smart-6529a3b7-8345-468c-bbca-90c1fece0577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260748978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
260748978
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1083674508
Short name T664
Test name
Test status
Simulation time 102768360827 ps
CPU time 225.39 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:15:00 PM PDT 24
Peak memory 209848 kb
Host smart-1e05c106-da05-42cf-acb0-073c18023330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083674508 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1083674508
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1463799501
Short name T510
Test name
Test status
Simulation time 426337343 ps
CPU time 1.59 seconds
Started Aug 05 06:11:18 PM PDT 24
Finished Aug 05 06:11:19 PM PDT 24
Peak memory 201128 kb
Host smart-020dd61d-54a6-4d05-991a-2506a0cd2253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463799501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1463799501
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.4230012789
Short name T337
Test name
Test status
Simulation time 589692429565 ps
CPU time 645.19 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:22:01 PM PDT 24
Peak memory 201448 kb
Host smart-13a95da1-21c6-4d08-9f0d-0967702cea29
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230012789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.4230012789
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.4268137094
Short name T280
Test name
Test status
Simulation time 205053590161 ps
CPU time 77.76 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:12:37 PM PDT 24
Peak memory 201452 kb
Host smart-163baace-811d-43ae-b170-db190dd9daf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268137094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.4268137094
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3494258477
Short name T599
Test name
Test status
Simulation time 330132196128 ps
CPU time 405.44 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:18:01 PM PDT 24
Peak memory 201496 kb
Host smart-9fd12a1b-06b6-4e4e-93f1-1b489d02dbec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494258477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3494258477
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3867626966
Short name T533
Test name
Test status
Simulation time 489446140569 ps
CPU time 489.06 seconds
Started Aug 05 06:11:19 PM PDT 24
Finished Aug 05 06:19:29 PM PDT 24
Peak memory 201436 kb
Host smart-16c304c6-11e1-4273-8b84-cfbc27f90457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867626966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3867626966
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.958924844
Short name T519
Test name
Test status
Simulation time 326029187000 ps
CPU time 722.68 seconds
Started Aug 05 06:11:11 PM PDT 24
Finished Aug 05 06:23:14 PM PDT 24
Peak memory 201416 kb
Host smart-4733f95e-5f4f-4b50-83cb-9d95ff1da504
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=958924844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.958924844
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2764414118
Short name T698
Test name
Test status
Simulation time 294582935081 ps
CPU time 652.13 seconds
Started Aug 05 06:11:10 PM PDT 24
Finished Aug 05 06:22:02 PM PDT 24
Peak memory 201448 kb
Host smart-c11deb77-af6d-4225-b8ed-1e6d69c0580f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764414118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2764414118
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2225394254
Short name T11
Test name
Test status
Simulation time 402706507040 ps
CPU time 883.31 seconds
Started Aug 05 06:11:24 PM PDT 24
Finished Aug 05 06:26:08 PM PDT 24
Peak memory 201368 kb
Host smart-7456c671-c44b-4b1b-8c4b-964a3ee23ab9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225394254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2225394254
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2949555206
Short name T112
Test name
Test status
Simulation time 42216571496 ps
CPU time 98.2 seconds
Started Aug 05 06:11:20 PM PDT 24
Finished Aug 05 06:12:58 PM PDT 24
Peak memory 201324 kb
Host smart-a4ceb4ee-cfcf-41df-b60c-0a703d81fc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949555206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2949555206
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.4216214178
Short name T722
Test name
Test status
Simulation time 2639536083 ps
CPU time 2.11 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:11:19 PM PDT 24
Peak memory 201344 kb
Host smart-a770fb12-ab0b-4936-9fe6-41297b223e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216214178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.4216214178
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2389483188
Short name T362
Test name
Test status
Simulation time 5728082113 ps
CPU time 13.24 seconds
Started Aug 05 06:11:22 PM PDT 24
Finished Aug 05 06:11:35 PM PDT 24
Peak memory 201356 kb
Host smart-6cd44e5e-f084-4c7d-bec0-468d34d52a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389483188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2389483188
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1946914557
Short name T108
Test name
Test status
Simulation time 135782422168 ps
CPU time 47.38 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:12:03 PM PDT 24
Peak memory 209884 kb
Host smart-38783898-5ef8-4a1b-8a2f-a1eef95dbe54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946914557 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1946914557
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3544619354
Short name T731
Test name
Test status
Simulation time 512190283 ps
CPU time 1.8 seconds
Started Aug 05 06:11:25 PM PDT 24
Finished Aug 05 06:11:27 PM PDT 24
Peak memory 201260 kb
Host smart-934d004a-699d-4caa-8f7d-429bbd582262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544619354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3544619354
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.342695001
Short name T784
Test name
Test status
Simulation time 360464228624 ps
CPU time 457.38 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:18:53 PM PDT 24
Peak memory 201452 kb
Host smart-49d1be10-7b39-4eaa-9362-1a6ab27c1051
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342695001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.342695001
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3375754698
Short name T779
Test name
Test status
Simulation time 165061507162 ps
CPU time 383.11 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:17:39 PM PDT 24
Peak memory 201460 kb
Host smart-fed841e6-a29e-434d-ae89-7d0275a00679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375754698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3375754698
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2343813609
Short name T638
Test name
Test status
Simulation time 483292498167 ps
CPU time 300.06 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:16:14 PM PDT 24
Peak memory 201480 kb
Host smart-ae6cc633-2144-49bf-95d7-2a17006e585d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343813609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2343813609
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.544166312
Short name T771
Test name
Test status
Simulation time 328859919703 ps
CPU time 687.02 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:22:43 PM PDT 24
Peak memory 201452 kb
Host smart-21f1e2c1-02c1-478a-addc-5ea937a30ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544166312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.544166312
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1307359888
Short name T400
Test name
Test status
Simulation time 499005459111 ps
CPU time 1101.75 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:29:37 PM PDT 24
Peak memory 201472 kb
Host smart-287a3a1a-5b5f-4ca3-a722-4bc3dc8728c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307359888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1307359888
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3360201604
Short name T244
Test name
Test status
Simulation time 200763426301 ps
CPU time 106.76 seconds
Started Aug 05 06:11:18 PM PDT 24
Finished Aug 05 06:13:05 PM PDT 24
Peak memory 201444 kb
Host smart-dbc5cfdc-5f22-4ff0-b3f1-85d1eabd2389
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360201604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3360201604
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2364529336
Short name T692
Test name
Test status
Simulation time 392019677762 ps
CPU time 808.58 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:24:44 PM PDT 24
Peak memory 201556 kb
Host smart-70fab954-951f-418c-aa92-2ab70c7c079a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364529336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2364529336
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.4156200042
Short name T619
Test name
Test status
Simulation time 44250870954 ps
CPU time 104.45 seconds
Started Aug 05 06:11:31 PM PDT 24
Finished Aug 05 06:13:16 PM PDT 24
Peak memory 201372 kb
Host smart-42905250-d670-4577-aa7d-fbfe87da3c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156200042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.4156200042
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1282802141
Short name T717
Test name
Test status
Simulation time 2855193635 ps
CPU time 6.59 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:11:24 PM PDT 24
Peak memory 201328 kb
Host smart-d98bb9a4-b297-44eb-83f0-d00d27b02edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282802141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1282802141
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3653783789
Short name T448
Test name
Test status
Simulation time 5929923806 ps
CPU time 3.45 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:11:19 PM PDT 24
Peak memory 201384 kb
Host smart-735856fc-5ad6-409c-82ed-9a30897fef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653783789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3653783789
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2997621696
Short name T640
Test name
Test status
Simulation time 161128149191 ps
CPU time 101.06 seconds
Started Aug 05 06:11:16 PM PDT 24
Finished Aug 05 06:12:57 PM PDT 24
Peak memory 201444 kb
Host smart-9a3fa9c0-71cc-4316-9376-c1ff9812bd72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997621696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2997621696
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3765867346
Short name T764
Test name
Test status
Simulation time 337526451600 ps
CPU time 341.88 seconds
Started Aug 05 06:11:17 PM PDT 24
Finished Aug 05 06:16:59 PM PDT 24
Peak memory 210156 kb
Host smart-12c51d73-eac3-46cb-9c8f-ef5d4b1d799b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765867346 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3765867346
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.286971478
Short name T794
Test name
Test status
Simulation time 448716854 ps
CPU time 1.11 seconds
Started Aug 05 06:11:21 PM PDT 24
Finished Aug 05 06:11:23 PM PDT 24
Peak memory 201256 kb
Host smart-eb6a8b3f-b077-406e-bc15-c3b987e047cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286971478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.286971478
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1539466395
Short name T339
Test name
Test status
Simulation time 341838420650 ps
CPU time 558.18 seconds
Started Aug 05 06:11:18 PM PDT 24
Finished Aug 05 06:20:36 PM PDT 24
Peak memory 201488 kb
Host smart-eb8cfcc6-016b-4e02-9c0e-f4437f55edf2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539466395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1539466395
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1928031296
Short name T347
Test name
Test status
Simulation time 169393860809 ps
CPU time 94.49 seconds
Started Aug 05 06:11:23 PM PDT 24
Finished Aug 05 06:12:58 PM PDT 24
Peak memory 201444 kb
Host smart-259ed067-387f-466d-8eda-d6556ec4120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928031296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1928031296
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3191462767
Short name T94
Test name
Test status
Simulation time 161557529566 ps
CPU time 352.86 seconds
Started Aug 05 06:11:22 PM PDT 24
Finished Aug 05 06:17:15 PM PDT 24
Peak memory 201484 kb
Host smart-63ac492c-d01a-44ca-bd15-90e7494d95fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191462767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3191462767
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2393908669
Short name T552
Test name
Test status
Simulation time 325985936840 ps
CPU time 185.55 seconds
Started Aug 05 06:11:15 PM PDT 24
Finished Aug 05 06:14:21 PM PDT 24
Peak memory 201448 kb
Host smart-06d935e9-b22f-49f7-9601-c13b0c346dbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393908669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2393908669
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2584947975
Short name T646
Test name
Test status
Simulation time 163349925613 ps
CPU time 161.92 seconds
Started Aug 05 06:11:18 PM PDT 24
Finished Aug 05 06:14:00 PM PDT 24
Peak memory 201440 kb
Host smart-043717fe-82b7-4580-ab16-e7f04fc97c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584947975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2584947975
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3899596336
Short name T535
Test name
Test status
Simulation time 166472278804 ps
CPU time 297.03 seconds
Started Aug 05 06:11:20 PM PDT 24
Finished Aug 05 06:16:17 PM PDT 24
Peak memory 201420 kb
Host smart-d87d9f93-cb85-4c23-bd97-71c307c53f3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899596336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3899596336
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.352491566
Short name T788
Test name
Test status
Simulation time 475803189477 ps
CPU time 988.29 seconds
Started Aug 05 06:11:21 PM PDT 24
Finished Aug 05 06:27:49 PM PDT 24
Peak memory 201364 kb
Host smart-f27c33af-220f-4225-9f89-219364f3722b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352491566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.352491566
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1004008789
Short name T483
Test name
Test status
Simulation time 597731432546 ps
CPU time 1306.44 seconds
Started Aug 05 06:11:21 PM PDT 24
Finished Aug 05 06:33:08 PM PDT 24
Peak memory 201460 kb
Host smart-119c6bfb-e97f-473d-80ee-52f539e7b8b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004008789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1004008789
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2777815093
Short name T491
Test name
Test status
Simulation time 137905385623 ps
CPU time 477.78 seconds
Started Aug 05 06:11:25 PM PDT 24
Finished Aug 05 06:19:23 PM PDT 24
Peak memory 201832 kb
Host smart-06c2a6e0-01b0-4068-9848-b6ae860fc8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777815093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2777815093
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2511786005
Short name T428
Test name
Test status
Simulation time 38251054657 ps
CPU time 7.05 seconds
Started Aug 05 06:11:21 PM PDT 24
Finished Aug 05 06:11:29 PM PDT 24
Peak memory 201384 kb
Host smart-b247205a-9637-4f20-975f-5a31ad088433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511786005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2511786005
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2625386546
Short name T670
Test name
Test status
Simulation time 4328887249 ps
CPU time 3.35 seconds
Started Aug 05 06:11:28 PM PDT 24
Finished Aug 05 06:11:31 PM PDT 24
Peak memory 201356 kb
Host smart-c707559d-32c1-424f-b713-fbd72cd05962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625386546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2625386546
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.728086012
Short name T605
Test name
Test status
Simulation time 5959020953 ps
CPU time 4.15 seconds
Started Aug 05 06:11:20 PM PDT 24
Finished Aug 05 06:11:24 PM PDT 24
Peak memory 201376 kb
Host smart-8b292c84-cabc-46b2-ad69-bcdce13b4ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728086012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.728086012
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3444653276
Short name T707
Test name
Test status
Simulation time 587812146365 ps
CPU time 560.1 seconds
Started Aug 05 06:11:31 PM PDT 24
Finished Aug 05 06:20:51 PM PDT 24
Peak memory 201816 kb
Host smart-4195ea62-9a8c-468b-b83c-c5f51bec4668
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444653276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3444653276
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1304872785
Short name T318
Test name
Test status
Simulation time 117498175001 ps
CPU time 73.89 seconds
Started Aug 05 06:11:31 PM PDT 24
Finished Aug 05 06:12:45 PM PDT 24
Peak memory 209764 kb
Host smart-fb0c1961-e556-4dad-8879-37ecf5e58844
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304872785 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1304872785
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.335646217
Short name T442
Test name
Test status
Simulation time 393423546 ps
CPU time 1.04 seconds
Started Aug 05 06:11:28 PM PDT 24
Finished Aug 05 06:11:29 PM PDT 24
Peak memory 201232 kb
Host smart-16c5a269-87b3-420a-bf9b-87d2fd5049d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335646217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.335646217
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.4088635787
Short name T621
Test name
Test status
Simulation time 171914546281 ps
CPU time 275.66 seconds
Started Aug 05 06:11:30 PM PDT 24
Finished Aug 05 06:16:06 PM PDT 24
Peak memory 201424 kb
Host smart-9438e5c9-4d67-4b00-9ece-a9ea35d5bb2f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088635787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.4088635787
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.214556006
Short name T101
Test name
Test status
Simulation time 487572897197 ps
CPU time 604.12 seconds
Started Aug 05 06:11:25 PM PDT 24
Finished Aug 05 06:21:30 PM PDT 24
Peak memory 201472 kb
Host smart-7d639efb-c66b-4c06-ace9-268464fda257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214556006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.214556006
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.35144571
Short name T180
Test name
Test status
Simulation time 333323355151 ps
CPU time 184.69 seconds
Started Aug 05 06:11:34 PM PDT 24
Finished Aug 05 06:14:39 PM PDT 24
Peak memory 201436 kb
Host smart-d3ad012b-dedd-465a-86ea-e7406a059d76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=35144571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt
_fixed.35144571
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.609728714
Short name T559
Test name
Test status
Simulation time 169859104141 ps
CPU time 162.36 seconds
Started Aug 05 06:11:25 PM PDT 24
Finished Aug 05 06:14:08 PM PDT 24
Peak memory 201456 kb
Host smart-15d63a82-fc31-4b54-8d03-4fa4d3ee6a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609728714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.609728714
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1916563337
Short name T396
Test name
Test status
Simulation time 160700429250 ps
CPU time 334.6 seconds
Started Aug 05 06:11:27 PM PDT 24
Finished Aug 05 06:17:01 PM PDT 24
Peak memory 201468 kb
Host smart-de24dc17-2321-415a-80b6-d2453b60626f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916563337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1916563337
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.128132485
Short name T83
Test name
Test status
Simulation time 521093909472 ps
CPU time 258.7 seconds
Started Aug 05 06:11:28 PM PDT 24
Finished Aug 05 06:15:47 PM PDT 24
Peak memory 201460 kb
Host smart-2958d466-55b4-422f-ab02-f1d83c66e7b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128132485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.128132485
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.61930342
Short name T116
Test name
Test status
Simulation time 201659556021 ps
CPU time 119.74 seconds
Started Aug 05 06:11:29 PM PDT 24
Finished Aug 05 06:13:28 PM PDT 24
Peak memory 201456 kb
Host smart-d57bd045-7197-4622-9bd5-b9d0b00129ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61930342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.a
dc_ctrl_filters_wakeup_fixed.61930342
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3707303188
Short name T48
Test name
Test status
Simulation time 124030192038 ps
CPU time 588.73 seconds
Started Aug 05 06:11:28 PM PDT 24
Finished Aug 05 06:21:17 PM PDT 24
Peak memory 201828 kb
Host smart-06a912ec-88dd-4f5f-b008-9dae94cd68c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707303188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3707303188
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.233529933
Short name T375
Test name
Test status
Simulation time 40250347103 ps
CPU time 84.88 seconds
Started Aug 05 06:11:32 PM PDT 24
Finished Aug 05 06:12:57 PM PDT 24
Peak memory 201392 kb
Host smart-ce673394-b6ae-4f87-8c84-6db3a25793b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233529933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.233529933
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3308315244
Short name T470
Test name
Test status
Simulation time 4187879453 ps
CPU time 5.56 seconds
Started Aug 05 06:11:29 PM PDT 24
Finished Aug 05 06:11:35 PM PDT 24
Peak memory 201308 kb
Host smart-1366da5c-8924-4534-b344-3f6ef2cc5499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308315244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3308315244
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3620765502
Short name T441
Test name
Test status
Simulation time 6077165737 ps
CPU time 8.89 seconds
Started Aug 05 06:11:32 PM PDT 24
Finished Aug 05 06:11:41 PM PDT 24
Peak memory 201352 kb
Host smart-1db141a1-9d69-42db-8022-c6d2a58beac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620765502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3620765502
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.639288725
Short name T600
Test name
Test status
Simulation time 167606006878 ps
CPU time 377.17 seconds
Started Aug 05 06:11:25 PM PDT 24
Finished Aug 05 06:17:43 PM PDT 24
Peak memory 201456 kb
Host smart-0ffdfdd6-766b-4350-831a-c8bea9e47e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639288725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
639288725
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3036408144
Short name T110
Test name
Test status
Simulation time 45201236275 ps
CPU time 133.96 seconds
Started Aug 05 06:11:28 PM PDT 24
Finished Aug 05 06:13:42 PM PDT 24
Peak memory 210140 kb
Host smart-fb300497-b0f9-41d3-b811-8faa29b7750e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036408144 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3036408144
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3997962966
Short name T579
Test name
Test status
Simulation time 359101470 ps
CPU time 0.93 seconds
Started Aug 05 06:11:34 PM PDT 24
Finished Aug 05 06:11:35 PM PDT 24
Peak memory 201248 kb
Host smart-7e1bf9e8-f069-4848-adab-636e1ff3991d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997962966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3997962966
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3039569347
Short name T319
Test name
Test status
Simulation time 332537381631 ps
CPU time 698.84 seconds
Started Aug 05 06:11:32 PM PDT 24
Finished Aug 05 06:23:11 PM PDT 24
Peak memory 201444 kb
Host smart-a93dc20f-f566-41ba-a881-6787670409c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039569347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3039569347
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1800226356
Short name T104
Test name
Test status
Simulation time 166570027618 ps
CPU time 74.68 seconds
Started Aug 05 06:11:28 PM PDT 24
Finished Aug 05 06:12:43 PM PDT 24
Peak memory 201464 kb
Host smart-87f07cd7-6a39-49eb-8626-6c9b806d2745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800226356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1800226356
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1243709724
Short name T567
Test name
Test status
Simulation time 330306361716 ps
CPU time 646.3 seconds
Started Aug 05 06:11:29 PM PDT 24
Finished Aug 05 06:22:16 PM PDT 24
Peak memory 201404 kb
Host smart-a88b0403-2902-4732-bc34-06e0cf175df8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243709724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1243709724
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2699434705
Short name T789
Test name
Test status
Simulation time 166237473469 ps
CPU time 368.29 seconds
Started Aug 05 06:11:26 PM PDT 24
Finished Aug 05 06:17:35 PM PDT 24
Peak memory 201460 kb
Host smart-7ea6d237-802c-41a8-a4ae-647cbf24aa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699434705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2699434705
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2788545290
Short name T398
Test name
Test status
Simulation time 327708997092 ps
CPU time 173.25 seconds
Started Aug 05 06:11:35 PM PDT 24
Finished Aug 05 06:14:28 PM PDT 24
Peak memory 201452 kb
Host smart-0777cd2f-07f4-48b6-a2f0-a1c8d155cec0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788545290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2788545290
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1344855194
Short name T330
Test name
Test status
Simulation time 559864499202 ps
CPU time 1379.09 seconds
Started Aug 05 06:11:35 PM PDT 24
Finished Aug 05 06:34:34 PM PDT 24
Peak memory 201484 kb
Host smart-5c92b20b-a827-4061-aa8e-d4c0dba0c6a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344855194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1344855194
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3096502512
Short name T512
Test name
Test status
Simulation time 395528109993 ps
CPU time 237.23 seconds
Started Aug 05 06:11:35 PM PDT 24
Finished Aug 05 06:15:33 PM PDT 24
Peak memory 201456 kb
Host smart-70108999-9be6-4a1f-b849-42b5304b1192
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096502512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3096502512
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2544471587
Short name T28
Test name
Test status
Simulation time 123022291266 ps
CPU time 626.39 seconds
Started Aug 05 06:11:33 PM PDT 24
Finished Aug 05 06:22:00 PM PDT 24
Peak memory 201868 kb
Host smart-10064ed2-f1a1-45fa-ab67-915de5bac8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544471587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2544471587
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.138571683
Short name T500
Test name
Test status
Simulation time 27570341025 ps
CPU time 64.56 seconds
Started Aug 05 06:11:33 PM PDT 24
Finished Aug 05 06:12:38 PM PDT 24
Peak memory 201448 kb
Host smart-5468fb43-0d0a-471e-be09-8a7ebca329e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138571683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.138571683
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1384196753
Short name T658
Test name
Test status
Simulation time 5044382827 ps
CPU time 12.78 seconds
Started Aug 05 06:11:40 PM PDT 24
Finished Aug 05 06:11:53 PM PDT 24
Peak memory 201340 kb
Host smart-9ece660a-eed1-4396-9309-fbc9177c239b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384196753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1384196753
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2336296903
Short name T700
Test name
Test status
Simulation time 5928899851 ps
CPU time 7.23 seconds
Started Aug 05 06:11:26 PM PDT 24
Finished Aug 05 06:11:33 PM PDT 24
Peak memory 201376 kb
Host smart-dace0b09-b92d-4fea-b015-9b9af1dc687c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336296903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2336296903
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2526371497
Short name T530
Test name
Test status
Simulation time 240234483568 ps
CPU time 803.09 seconds
Started Aug 05 06:11:33 PM PDT 24
Finished Aug 05 06:24:57 PM PDT 24
Peak memory 201912 kb
Host smart-403b531d-c166-4b70-a3ab-ad2bb5d7c39e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526371497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2526371497
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.4029423084
Short name T277
Test name
Test status
Simulation time 222936144869 ps
CPU time 192.39 seconds
Started Aug 05 06:11:32 PM PDT 24
Finished Aug 05 06:14:45 PM PDT 24
Peak memory 210116 kb
Host smart-fe83b7a1-11ec-451d-81dd-b61ce74b8958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029423084 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.4029423084
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.479525524
Short name T379
Test name
Test status
Simulation time 484258421 ps
CPU time 1.16 seconds
Started Aug 05 06:11:40 PM PDT 24
Finished Aug 05 06:11:42 PM PDT 24
Peak memory 201196 kb
Host smart-18cc8f4b-af8f-45d6-82dd-fb66fcfa1d6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479525524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.479525524
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2881100713
Short name T740
Test name
Test status
Simulation time 335558230820 ps
CPU time 75.74 seconds
Started Aug 05 06:11:34 PM PDT 24
Finished Aug 05 06:12:50 PM PDT 24
Peak memory 201416 kb
Host smart-611f2f3c-84f1-4516-bf22-a67987e74a75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881100713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2881100713
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2379044015
Short name T427
Test name
Test status
Simulation time 166291354969 ps
CPU time 189.17 seconds
Started Aug 05 06:11:35 PM PDT 24
Finished Aug 05 06:14:44 PM PDT 24
Peak memory 201520 kb
Host smart-8999e2be-f43a-428f-b5d2-4e78f0d8c68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379044015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2379044015
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2510245986
Short name T635
Test name
Test status
Simulation time 496205495557 ps
CPU time 656.31 seconds
Started Aug 05 06:11:34 PM PDT 24
Finished Aug 05 06:22:31 PM PDT 24
Peak memory 201472 kb
Host smart-9668f402-05d4-4021-9a83-b7a063fcf6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510245986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2510245986
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2494338604
Short name T602
Test name
Test status
Simulation time 163339087785 ps
CPU time 75.15 seconds
Started Aug 05 06:11:33 PM PDT 24
Finished Aug 05 06:12:48 PM PDT 24
Peak memory 201464 kb
Host smart-56b85976-d1b0-4674-8bf6-ce8e9aa408bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494338604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2494338604
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3381084213
Short name T702
Test name
Test status
Simulation time 491931223242 ps
CPU time 312.82 seconds
Started Aug 05 06:11:36 PM PDT 24
Finished Aug 05 06:16:49 PM PDT 24
Peak memory 201424 kb
Host smart-29d9e9c3-a299-4597-9735-93cd05e8167f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381084213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3381084213
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2668650079
Short name T509
Test name
Test status
Simulation time 196963731679 ps
CPU time 356.52 seconds
Started Aug 05 06:11:35 PM PDT 24
Finished Aug 05 06:17:32 PM PDT 24
Peak memory 201428 kb
Host smart-2ed307be-7c27-4638-b6b1-a51939146f7c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668650079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2668650079
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3663842848
Short name T606
Test name
Test status
Simulation time 106926838582 ps
CPU time 576.96 seconds
Started Aug 05 06:11:44 PM PDT 24
Finished Aug 05 06:21:21 PM PDT 24
Peak memory 201892 kb
Host smart-42ca9a10-c5a9-4b95-9005-fd335677e3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663842848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3663842848
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1645834885
Short name T374
Test name
Test status
Simulation time 33547382437 ps
CPU time 11.88 seconds
Started Aug 05 06:11:37 PM PDT 24
Finished Aug 05 06:11:49 PM PDT 24
Peak memory 201364 kb
Host smart-6da3e1dd-c082-4a55-a217-5a498337b41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645834885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1645834885
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.4035583372
Short name T503
Test name
Test status
Simulation time 3284524441 ps
CPU time 2.66 seconds
Started Aug 05 06:11:36 PM PDT 24
Finished Aug 05 06:11:39 PM PDT 24
Peak memory 201348 kb
Host smart-303f0d74-eb16-4c92-8b48-f69205643168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035583372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.4035583372
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1256631269
Short name T426
Test name
Test status
Simulation time 6146018871 ps
CPU time 8.33 seconds
Started Aug 05 06:11:34 PM PDT 24
Finished Aug 05 06:11:42 PM PDT 24
Peak memory 201380 kb
Host smart-dd5299b9-1273-4bbf-92a1-3ff1b526e7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256631269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1256631269
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.710469443
Short name T88
Test name
Test status
Simulation time 64804153543 ps
CPU time 186.21 seconds
Started Aug 05 06:11:39 PM PDT 24
Finished Aug 05 06:14:46 PM PDT 24
Peak memory 210224 kb
Host smart-43b81ccc-3a11-407a-88f0-513082e1e0de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710469443 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.710469443
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3567932414
Short name T657
Test name
Test status
Simulation time 283429838 ps
CPU time 1.25 seconds
Started Aug 05 06:10:32 PM PDT 24
Finished Aug 05 06:10:34 PM PDT 24
Peak memory 201256 kb
Host smart-dffa7023-4a23-4df5-bd82-e650a10a6d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567932414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3567932414
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.553156054
Short name T629
Test name
Test status
Simulation time 164313948398 ps
CPU time 384.06 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:16:53 PM PDT 24
Peak memory 201524 kb
Host smart-e05cc3f5-32d3-4982-8d2e-0585561d3855
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553156054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.553156054
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2270307370
Short name T570
Test name
Test status
Simulation time 323795136589 ps
CPU time 351.16 seconds
Started Aug 05 06:10:41 PM PDT 24
Finished Aug 05 06:16:32 PM PDT 24
Peak memory 201456 kb
Host smart-69a0306d-320f-41de-b286-1f787b0aa4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270307370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2270307370
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.691769743
Short name T703
Test name
Test status
Simulation time 162915883740 ps
CPU time 396.84 seconds
Started Aug 05 06:10:26 PM PDT 24
Finished Aug 05 06:17:04 PM PDT 24
Peak memory 201424 kb
Host smart-7df66937-393d-46f6-82cb-7d0d55a5da8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691769743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.691769743
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3000309275
Short name T580
Test name
Test status
Simulation time 499831605064 ps
CPU time 1181.84 seconds
Started Aug 05 06:10:17 PM PDT 24
Finished Aug 05 06:29:59 PM PDT 24
Peak memory 201516 kb
Host smart-9a427fc2-fffc-4905-bf57-6b835d28e8f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000309275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3000309275
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.971756501
Short name T373
Test name
Test status
Simulation time 487397265789 ps
CPU time 676.08 seconds
Started Aug 05 06:10:13 PM PDT 24
Finished Aug 05 06:21:29 PM PDT 24
Peak memory 201364 kb
Host smart-f195d1bd-a8e9-4b60-9448-e5d2a7a9de76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=971756501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.971756501
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.694770202
Short name T78
Test name
Test status
Simulation time 175535879750 ps
CPU time 97.61 seconds
Started Aug 05 06:10:26 PM PDT 24
Finished Aug 05 06:12:04 PM PDT 24
Peak memory 201388 kb
Host smart-790432b1-7001-4fe9-aba0-16351d2591cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694770202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.694770202
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.628299740
Short name T560
Test name
Test status
Simulation time 572562774901 ps
CPU time 330.54 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:15:58 PM PDT 24
Peak memory 201420 kb
Host smart-686d0027-1913-4e7c-8392-c732e1ab1a64
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628299740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.628299740
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3233458571
Short name T736
Test name
Test status
Simulation time 82537821758 ps
CPU time 415.07 seconds
Started Aug 05 06:10:45 PM PDT 24
Finished Aug 05 06:17:40 PM PDT 24
Peak memory 201864 kb
Host smart-202b3b47-baed-4717-bff5-9b0620f4c3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233458571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3233458571
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3535245751
Short name T601
Test name
Test status
Simulation time 32499937341 ps
CPU time 19.83 seconds
Started Aug 05 06:10:29 PM PDT 24
Finished Aug 05 06:10:49 PM PDT 24
Peak memory 201380 kb
Host smart-d4e463bd-f641-4ad0-ac02-0e8f6a8a77e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535245751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3535245751
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2794325133
Short name T642
Test name
Test status
Simulation time 2934114471 ps
CPU time 2.66 seconds
Started Aug 05 06:10:29 PM PDT 24
Finished Aug 05 06:10:32 PM PDT 24
Peak memory 200960 kb
Host smart-f72088ed-8fae-432b-921e-7b504f30b9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794325133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2794325133
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2377162585
Short name T61
Test name
Test status
Simulation time 8727431638 ps
CPU time 21.76 seconds
Started Aug 05 06:10:44 PM PDT 24
Finished Aug 05 06:11:05 PM PDT 24
Peak memory 218228 kb
Host smart-422043d7-7e57-4c44-8271-36e36c59e422
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377162585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2377162585
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3753664671
Short name T563
Test name
Test status
Simulation time 5791265292 ps
CPU time 2.43 seconds
Started Aug 05 06:10:35 PM PDT 24
Finished Aug 05 06:10:38 PM PDT 24
Peak memory 201368 kb
Host smart-fb98902e-8e7a-4821-9c30-59b40b1b5ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753664671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3753664671
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1442130388
Short name T612
Test name
Test status
Simulation time 243769665360 ps
CPU time 153.95 seconds
Started Aug 05 06:10:30 PM PDT 24
Finished Aug 05 06:13:05 PM PDT 24
Peak memory 201456 kb
Host smart-bbf8c1a2-324b-4b70-a627-f4a830eacde7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442130388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1442130388
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2257556648
Short name T634
Test name
Test status
Simulation time 45486824784 ps
CPU time 26.13 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:10:53 PM PDT 24
Peak memory 209752 kb
Host smart-7e9e7743-651b-47fd-9384-87ba90625086
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257556648 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2257556648
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.360772389
Short name T471
Test name
Test status
Simulation time 307364129 ps
CPU time 1.32 seconds
Started Aug 05 06:11:50 PM PDT 24
Finished Aug 05 06:11:51 PM PDT 24
Peak memory 201224 kb
Host smart-b44a8f31-c325-46dd-84df-94233a1c879e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360772389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.360772389
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3567058601
Short name T617
Test name
Test status
Simulation time 168095424274 ps
CPU time 332.69 seconds
Started Aug 05 06:11:45 PM PDT 24
Finished Aug 05 06:17:17 PM PDT 24
Peak memory 201404 kb
Host smart-0bef8786-5c66-4749-b56f-73214a6d11da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567058601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3567058601
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3241936972
Short name T322
Test name
Test status
Simulation time 561715241903 ps
CPU time 1351.51 seconds
Started Aug 05 06:11:45 PM PDT 24
Finished Aug 05 06:34:17 PM PDT 24
Peak memory 201516 kb
Host smart-0dd43e41-3ced-42b8-a488-d31c3a9b8860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241936972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3241936972
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2946732614
Short name T80
Test name
Test status
Simulation time 163054621922 ps
CPU time 388.34 seconds
Started Aug 05 06:11:38 PM PDT 24
Finished Aug 05 06:18:06 PM PDT 24
Peak memory 201504 kb
Host smart-8a3bf367-d699-4e6a-b744-b7bf356bea6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946732614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2946732614
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1180704524
Short name T87
Test name
Test status
Simulation time 319087452560 ps
CPU time 49.08 seconds
Started Aug 05 06:11:39 PM PDT 24
Finished Aug 05 06:12:28 PM PDT 24
Peak memory 201464 kb
Host smart-f169d067-73df-4729-9eed-70e5453a1984
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180704524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1180704524
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.854352988
Short name T795
Test name
Test status
Simulation time 164503438922 ps
CPU time 386.18 seconds
Started Aug 05 06:11:37 PM PDT 24
Finished Aug 05 06:18:03 PM PDT 24
Peak memory 201440 kb
Host smart-831af2f0-2fc8-471b-9df7-4884b4e041fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854352988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.854352988
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2193323404
Short name T705
Test name
Test status
Simulation time 331581943928 ps
CPU time 768.18 seconds
Started Aug 05 06:11:43 PM PDT 24
Finished Aug 05 06:24:31 PM PDT 24
Peak memory 201468 kb
Host smart-1d357bcc-6d2c-4023-b35b-bb9208f67e47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193323404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2193323404
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3505178458
Short name T245
Test name
Test status
Simulation time 196888329587 ps
CPU time 431.34 seconds
Started Aug 05 06:11:39 PM PDT 24
Finished Aug 05 06:18:50 PM PDT 24
Peak memory 201452 kb
Host smart-63395160-7e95-4cc7-8199-3b0b8b057cec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505178458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3505178458
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.568477592
Short name T529
Test name
Test status
Simulation time 194127450386 ps
CPU time 453.55 seconds
Started Aug 05 06:11:44 PM PDT 24
Finished Aug 05 06:19:18 PM PDT 24
Peak memory 201448 kb
Host smart-5a4ac0a4-5bd3-4d09-86ed-0a5ccda4c71a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568477592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.568477592
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3732581476
Short name T32
Test name
Test status
Simulation time 44525897342 ps
CPU time 74.53 seconds
Started Aug 05 06:11:45 PM PDT 24
Finished Aug 05 06:13:00 PM PDT 24
Peak memory 201348 kb
Host smart-79604eb5-e014-4652-ad04-8ae4f75e0832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732581476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3732581476
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2532646785
Short name T430
Test name
Test status
Simulation time 4736518047 ps
CPU time 12.16 seconds
Started Aug 05 06:11:46 PM PDT 24
Finished Aug 05 06:11:58 PM PDT 24
Peak memory 201352 kb
Host smart-7bfd5e22-b765-4ed7-a7c5-36efa8d380b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532646785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2532646785
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1598917139
Short name T103
Test name
Test status
Simulation time 5756804647 ps
CPU time 14.47 seconds
Started Aug 05 06:11:40 PM PDT 24
Finished Aug 05 06:11:55 PM PDT 24
Peak memory 201320 kb
Host smart-2598d23f-07a7-49d6-9c4f-79fa62a68263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598917139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1598917139
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2128004133
Short name T417
Test name
Test status
Simulation time 26299904592 ps
CPU time 57.95 seconds
Started Aug 05 06:11:47 PM PDT 24
Finished Aug 05 06:12:45 PM PDT 24
Peak memory 209784 kb
Host smart-3c88ce67-aedf-43e1-b900-d4e3dee4989b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128004133 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2128004133
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.43954877
Short name T671
Test name
Test status
Simulation time 423147318 ps
CPU time 0.92 seconds
Started Aug 05 06:11:52 PM PDT 24
Finished Aug 05 06:11:53 PM PDT 24
Peak memory 201224 kb
Host smart-e768f805-ff59-40e4-95d6-a3d5f7c04931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43954877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.43954877
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1237486101
Short name T348
Test name
Test status
Simulation time 185197037359 ps
CPU time 420.47 seconds
Started Aug 05 06:11:52 PM PDT 24
Finished Aug 05 06:18:52 PM PDT 24
Peak memory 201452 kb
Host smart-759f32e7-bd6b-4fa6-be24-b428e0b16172
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237486101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1237486101
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.975200782
Short name T776
Test name
Test status
Simulation time 343204531168 ps
CPU time 424.8 seconds
Started Aug 05 06:11:51 PM PDT 24
Finished Aug 05 06:18:56 PM PDT 24
Peak memory 201460 kb
Host smart-166bef18-7cb3-4f4c-af47-e828b62a3a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975200782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.975200782
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.4164799056
Short name T685
Test name
Test status
Simulation time 494043741825 ps
CPU time 1120.43 seconds
Started Aug 05 06:11:51 PM PDT 24
Finished Aug 05 06:30:31 PM PDT 24
Peak memory 201468 kb
Host smart-2e24d019-58ff-4050-a8ad-9326f2f029c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164799056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.4164799056
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3489843228
Short name T434
Test name
Test status
Simulation time 165789580504 ps
CPU time 109.17 seconds
Started Aug 05 06:11:52 PM PDT 24
Finished Aug 05 06:13:41 PM PDT 24
Peak memory 201380 kb
Host smart-54a119c6-adb6-4e18-82c3-5af1f00621e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489843228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3489843228
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.639770622
Short name T155
Test name
Test status
Simulation time 496674950171 ps
CPU time 1052.62 seconds
Started Aug 05 06:11:51 PM PDT 24
Finished Aug 05 06:29:24 PM PDT 24
Peak memory 201416 kb
Host smart-fe3c3b6e-bb7c-4b2c-b86d-522b544cb63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639770622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.639770622
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3109362032
Short name T486
Test name
Test status
Simulation time 328654428570 ps
CPU time 782.37 seconds
Started Aug 05 06:11:50 PM PDT 24
Finished Aug 05 06:24:53 PM PDT 24
Peak memory 201464 kb
Host smart-0030690d-eec2-4cd4-8933-2605b192f269
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109362032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3109362032
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1038494440
Short name T514
Test name
Test status
Simulation time 399261770679 ps
CPU time 457.18 seconds
Started Aug 05 06:11:49 PM PDT 24
Finished Aug 05 06:19:26 PM PDT 24
Peak memory 201348 kb
Host smart-93a64ee6-d11b-4dc8-b3a6-0a4c832dc619
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038494440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1038494440
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2386525380
Short name T752
Test name
Test status
Simulation time 94881585739 ps
CPU time 368.94 seconds
Started Aug 05 06:11:49 PM PDT 24
Finished Aug 05 06:17:59 PM PDT 24
Peak memory 201808 kb
Host smart-91648d91-a201-43b2-b029-ffedde782711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386525380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2386525380
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3640109223
Short name T363
Test name
Test status
Simulation time 38885033515 ps
CPU time 83.78 seconds
Started Aug 05 06:11:51 PM PDT 24
Finished Aug 05 06:13:15 PM PDT 24
Peak memory 201384 kb
Host smart-25e9e56e-c27c-4af8-be3d-6d274595709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640109223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3640109223
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2139966540
Short name T418
Test name
Test status
Simulation time 3263998063 ps
CPU time 4.2 seconds
Started Aug 05 06:11:50 PM PDT 24
Finished Aug 05 06:11:54 PM PDT 24
Peak memory 201372 kb
Host smart-dff2aaf8-3520-48b2-bb14-ceeeb17d3505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139966540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2139966540
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.296668968
Short name T608
Test name
Test status
Simulation time 6045127085 ps
CPU time 7.65 seconds
Started Aug 05 06:11:51 PM PDT 24
Finished Aug 05 06:11:59 PM PDT 24
Peak memory 201376 kb
Host smart-7d77de70-50c9-4585-935f-0f6cdcb1335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296668968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.296668968
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2696369319
Short name T716
Test name
Test status
Simulation time 533852710 ps
CPU time 0.88 seconds
Started Aug 05 06:11:56 PM PDT 24
Finished Aug 05 06:11:57 PM PDT 24
Peak memory 201248 kb
Host smart-7526e9dc-ccaf-42d4-8368-b31aa915596d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696369319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2696369319
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.212112068
Short name T263
Test name
Test status
Simulation time 168927657783 ps
CPU time 340.89 seconds
Started Aug 05 06:11:57 PM PDT 24
Finished Aug 05 06:17:38 PM PDT 24
Peak memory 201448 kb
Host smart-9f862d4f-8512-44e3-aebe-f12e5ff92893
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212112068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.212112068
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3490049481
Short name T536
Test name
Test status
Simulation time 167497915128 ps
CPU time 179.6 seconds
Started Aug 05 06:11:58 PM PDT 24
Finished Aug 05 06:14:58 PM PDT 24
Peak memory 201496 kb
Host smart-9fc9459f-2c6a-472b-8ff4-a05aa5b13cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490049481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3490049481
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2258992961
Short name T100
Test name
Test status
Simulation time 163718225984 ps
CPU time 191.56 seconds
Started Aug 05 06:11:51 PM PDT 24
Finished Aug 05 06:15:03 PM PDT 24
Peak memory 201532 kb
Host smart-8b7bbdda-c525-4aa9-8779-5dfbe3f58ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258992961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2258992961
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2275254660
Short name T405
Test name
Test status
Simulation time 329811857472 ps
CPU time 194.27 seconds
Started Aug 05 06:11:50 PM PDT 24
Finished Aug 05 06:15:04 PM PDT 24
Peak memory 201440 kb
Host smart-c99c3f8e-30e7-436d-9acf-bb740fd798d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275254660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2275254660
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.4123291319
Short name T2
Test name
Test status
Simulation time 331811086340 ps
CPU time 539.76 seconds
Started Aug 05 06:11:51 PM PDT 24
Finished Aug 05 06:20:51 PM PDT 24
Peak memory 201440 kb
Host smart-d3412cf9-086c-40d2-bcdf-2800987af861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123291319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.4123291319
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.987475706
Short name T583
Test name
Test status
Simulation time 326501273636 ps
CPU time 670.34 seconds
Started Aug 05 06:11:49 PM PDT 24
Finished Aug 05 06:23:00 PM PDT 24
Peak memory 201460 kb
Host smart-1034e7f7-c235-4c78-bc12-d4445da2424b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=987475706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.987475706
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.91737317
Short name T141
Test name
Test status
Simulation time 562415386752 ps
CPU time 1317.32 seconds
Started Aug 05 06:11:56 PM PDT 24
Finished Aug 05 06:33:53 PM PDT 24
Peak memory 201436 kb
Host smart-e6e6d0c0-00fc-467d-a734-3de7d02351bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91737317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_w
akeup.91737317
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3298291040
Short name T693
Test name
Test status
Simulation time 612211828986 ps
CPU time 212.93 seconds
Started Aug 05 06:11:56 PM PDT 24
Finished Aug 05 06:15:29 PM PDT 24
Peak memory 201448 kb
Host smart-688eb8b6-3d47-4a1d-8bab-9d0d19e39491
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298291040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3298291040
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2349664803
Short name T214
Test name
Test status
Simulation time 97225127250 ps
CPU time 514.75 seconds
Started Aug 05 06:11:57 PM PDT 24
Finished Aug 05 06:20:32 PM PDT 24
Peak memory 201820 kb
Host smart-62843a26-d80f-4ac8-a132-7ff1f095b9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349664803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2349664803
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3525662975
Short name T778
Test name
Test status
Simulation time 23285558912 ps
CPU time 17.05 seconds
Started Aug 05 06:11:58 PM PDT 24
Finished Aug 05 06:12:15 PM PDT 24
Peak memory 201360 kb
Host smart-5484ff74-ff92-4d54-b7be-43f67892fd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525662975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3525662975
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1310641683
Short name T377
Test name
Test status
Simulation time 4475937574 ps
CPU time 3.53 seconds
Started Aug 05 06:11:58 PM PDT 24
Finished Aug 05 06:12:02 PM PDT 24
Peak memory 201324 kb
Host smart-8296fee1-c0df-4bec-bf20-47bd2b575d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310641683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1310641683
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2972709505
Short name T694
Test name
Test status
Simulation time 5859455370 ps
CPU time 8.11 seconds
Started Aug 05 06:11:49 PM PDT 24
Finished Aug 05 06:11:58 PM PDT 24
Peak memory 201380 kb
Host smart-08cac833-cb4e-4f06-8272-16c2f7031951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972709505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2972709505
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2679492479
Short name T175
Test name
Test status
Simulation time 292867521103 ps
CPU time 585.09 seconds
Started Aug 05 06:11:57 PM PDT 24
Finished Aug 05 06:21:43 PM PDT 24
Peak memory 212832 kb
Host smart-addea682-6eee-48c9-800a-2e31e0905775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679492479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2679492479
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1642267589
Short name T22
Test name
Test status
Simulation time 65682229713 ps
CPU time 36.11 seconds
Started Aug 05 06:11:56 PM PDT 24
Finished Aug 05 06:12:32 PM PDT 24
Peak memory 201548 kb
Host smart-ea8111f4-0f0a-4a97-84f9-e266ef577ab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642267589 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1642267589
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3432794334
Short name T639
Test name
Test status
Simulation time 515631997 ps
CPU time 1.83 seconds
Started Aug 05 06:12:04 PM PDT 24
Finished Aug 05 06:12:06 PM PDT 24
Peak memory 201128 kb
Host smart-d61a2c23-3213-44a1-a1f6-c1288e3005f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432794334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3432794334
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3837827775
Short name T618
Test name
Test status
Simulation time 431003943400 ps
CPU time 242.28 seconds
Started Aug 05 06:11:57 PM PDT 24
Finished Aug 05 06:15:59 PM PDT 24
Peak memory 201396 kb
Host smart-dcf0bdff-ae66-4641-986f-d96246734c4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837827775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3837827775
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3413589960
Short name T762
Test name
Test status
Simulation time 493338005213 ps
CPU time 1121.29 seconds
Started Aug 05 06:11:57 PM PDT 24
Finished Aug 05 06:30:38 PM PDT 24
Peak memory 201444 kb
Host smart-69ec4b83-0f0b-48e7-9422-ebc856620e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413589960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3413589960
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4162979792
Short name T385
Test name
Test status
Simulation time 324230180983 ps
CPU time 150.99 seconds
Started Aug 05 06:11:58 PM PDT 24
Finished Aug 05 06:14:29 PM PDT 24
Peak memory 201500 kb
Host smart-8a125079-326d-48d7-8b56-cf6e36c2dde5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162979792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.4162979792
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3898624484
Short name T459
Test name
Test status
Simulation time 496424684818 ps
CPU time 275.31 seconds
Started Aug 05 06:11:56 PM PDT 24
Finished Aug 05 06:16:31 PM PDT 24
Peak memory 201456 kb
Host smart-ea842259-4c9d-49dc-bba5-07604291034d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898624484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3898624484
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1905200206
Short name T568
Test name
Test status
Simulation time 324124013131 ps
CPU time 314.57 seconds
Started Aug 05 06:11:56 PM PDT 24
Finished Aug 05 06:17:11 PM PDT 24
Peak memory 201444 kb
Host smart-4c3bc66c-c0d9-4f7a-81bd-014907dd6a18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905200206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1905200206
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3514695909
Short name T544
Test name
Test status
Simulation time 187886139544 ps
CPU time 116.9 seconds
Started Aug 05 06:11:56 PM PDT 24
Finished Aug 05 06:13:53 PM PDT 24
Peak memory 201412 kb
Host smart-74ca1600-f76e-4e71-a60c-9c93e01bba4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514695909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3514695909
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3433882018
Short name T630
Test name
Test status
Simulation time 603928180399 ps
CPU time 1413.96 seconds
Started Aug 05 06:11:56 PM PDT 24
Finished Aug 05 06:35:30 PM PDT 24
Peak memory 201396 kb
Host smart-ccdac66b-4b6f-4e89-86e5-7e3d29cb106f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433882018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3433882018
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.158624545
Short name T494
Test name
Test status
Simulation time 119988332960 ps
CPU time 517.4 seconds
Started Aug 05 06:12:02 PM PDT 24
Finished Aug 05 06:20:39 PM PDT 24
Peak memory 201836 kb
Host smart-f34e95e2-945d-4eb0-b9c8-50ecc893e497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158624545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.158624545
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2591361301
Short name T431
Test name
Test status
Simulation time 23808133221 ps
CPU time 55.46 seconds
Started Aug 05 06:12:02 PM PDT 24
Finished Aug 05 06:12:57 PM PDT 24
Peak memory 201332 kb
Host smart-f4204b30-ec20-452a-bce9-cdbdbbaf2dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591361301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2591361301
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.356831505
Short name T611
Test name
Test status
Simulation time 3258120367 ps
CPU time 4.05 seconds
Started Aug 05 06:12:05 PM PDT 24
Finished Aug 05 06:12:10 PM PDT 24
Peak memory 201352 kb
Host smart-2f691e97-4888-46c7-845a-e3f05f0849c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356831505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.356831505
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.4066592060
Short name T386
Test name
Test status
Simulation time 5942528735 ps
CPU time 7.34 seconds
Started Aug 05 06:11:56 PM PDT 24
Finished Aug 05 06:12:03 PM PDT 24
Peak memory 201380 kb
Host smart-b2473143-8693-464c-9262-a7c33f672cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066592060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4066592060
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.632352480
Short name T466
Test name
Test status
Simulation time 175050579309 ps
CPU time 39.52 seconds
Started Aug 05 06:12:02 PM PDT 24
Finished Aug 05 06:12:42 PM PDT 24
Peak memory 201440 kb
Host smart-135791d2-8f8e-4f86-8c33-78dd298a1fe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632352480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
632352480
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.666079369
Short name T18
Test name
Test status
Simulation time 60347640137 ps
CPU time 72 seconds
Started Aug 05 06:12:03 PM PDT 24
Finished Aug 05 06:13:15 PM PDT 24
Peak memory 209852 kb
Host smart-e19bb8fa-0a18-4aaf-83d2-3c0d1f49aa92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666079369 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.666079369
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.580812876
Short name T416
Test name
Test status
Simulation time 600543263 ps
CPU time 0.74 seconds
Started Aug 05 06:12:07 PM PDT 24
Finished Aug 05 06:12:08 PM PDT 24
Peak memory 201240 kb
Host smart-ac65fafc-cdf2-451a-9fcd-c15b1df0a53e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580812876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.580812876
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.272501179
Short name T577
Test name
Test status
Simulation time 335891338341 ps
CPU time 597.08 seconds
Started Aug 05 06:12:00 PM PDT 24
Finished Aug 05 06:21:57 PM PDT 24
Peak memory 201452 kb
Host smart-f065dff9-171e-4b91-b2b9-1d6d01854e5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272501179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.272501179
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2659964772
Short name T766
Test name
Test status
Simulation time 169978913072 ps
CPU time 374.57 seconds
Started Aug 05 06:12:02 PM PDT 24
Finished Aug 05 06:18:17 PM PDT 24
Peak memory 201468 kb
Host smart-84102071-010f-40ab-afa0-1dda07d77fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659964772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2659964772
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2307728281
Short name T585
Test name
Test status
Simulation time 494999244359 ps
CPU time 314.84 seconds
Started Aug 05 06:12:02 PM PDT 24
Finished Aug 05 06:17:17 PM PDT 24
Peak memory 201512 kb
Host smart-3baa68fb-9108-4b41-aa79-ee0635ed7bcc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307728281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2307728281
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2556900665
Short name T323
Test name
Test status
Simulation time 162214346066 ps
CPU time 354.36 seconds
Started Aug 05 06:12:02 PM PDT 24
Finished Aug 05 06:17:56 PM PDT 24
Peak memory 201424 kb
Host smart-706af553-3d32-4fd6-8748-f8773522dc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556900665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2556900665
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1632420857
Short name T179
Test name
Test status
Simulation time 335342706357 ps
CPU time 78.1 seconds
Started Aug 05 06:12:04 PM PDT 24
Finished Aug 05 06:13:22 PM PDT 24
Peak memory 201404 kb
Host smart-9e548cd7-5205-484d-88f7-e30ff0989f42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632420857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1632420857
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3901917221
Short name T645
Test name
Test status
Simulation time 388846873053 ps
CPU time 648.03 seconds
Started Aug 05 06:12:03 PM PDT 24
Finished Aug 05 06:22:51 PM PDT 24
Peak memory 201448 kb
Host smart-a17ee011-db35-40fa-969e-6385f6ceb165
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901917221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3901917221
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1495977482
Short name T115
Test name
Test status
Simulation time 78800238045 ps
CPU time 390.04 seconds
Started Aug 05 06:12:06 PM PDT 24
Finished Aug 05 06:18:37 PM PDT 24
Peak memory 201828 kb
Host smart-3e0ce311-0a32-4dd3-b226-6f20e3c73752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495977482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1495977482
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2177062768
Short name T720
Test name
Test status
Simulation time 28901590007 ps
CPU time 14.14 seconds
Started Aug 05 06:12:09 PM PDT 24
Finished Aug 05 06:12:23 PM PDT 24
Peak memory 201244 kb
Host smart-d5d259fa-7357-4e95-99f7-c751b1c6214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177062768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2177062768
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1022202831
Short name T425
Test name
Test status
Simulation time 2665296447 ps
CPU time 6.96 seconds
Started Aug 05 06:12:06 PM PDT 24
Finished Aug 05 06:12:13 PM PDT 24
Peak memory 201328 kb
Host smart-b733eede-ce6b-4886-8441-4fcc9aa4e4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022202831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1022202831
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3688523831
Short name T751
Test name
Test status
Simulation time 5768568004 ps
CPU time 6.96 seconds
Started Aug 05 06:12:02 PM PDT 24
Finished Aug 05 06:12:09 PM PDT 24
Peak memory 201360 kb
Host smart-990872a8-b8c4-486e-9896-6d8a5bd6e901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688523831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3688523831
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3263817893
Short name T672
Test name
Test status
Simulation time 177862837140 ps
CPU time 362.49 seconds
Started Aug 05 06:12:10 PM PDT 24
Finished Aug 05 06:18:12 PM PDT 24
Peak memory 201392 kb
Host smart-93b6ec55-ac19-4f29-b789-a177e2ba63e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263817893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3263817893
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2800756750
Short name T711
Test name
Test status
Simulation time 257966034930 ps
CPU time 536.93 seconds
Started Aug 05 06:12:07 PM PDT 24
Finished Aug 05 06:21:04 PM PDT 24
Peak memory 217628 kb
Host smart-9ce39683-9a66-41af-96e8-b09105ecfef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800756750 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2800756750
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2263127845
Short name T438
Test name
Test status
Simulation time 526403367 ps
CPU time 0.89 seconds
Started Aug 05 06:12:16 PM PDT 24
Finished Aug 05 06:12:17 PM PDT 24
Peak memory 201248 kb
Host smart-14ca5094-54f8-4216-8640-9e830c319197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263127845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2263127845
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3832574121
Short name T335
Test name
Test status
Simulation time 181960960393 ps
CPU time 211.63 seconds
Started Aug 05 06:12:11 PM PDT 24
Finished Aug 05 06:15:43 PM PDT 24
Peak memory 201448 kb
Host smart-d31eb227-5b74-4e8a-8c6c-caf701337602
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832574121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3832574121
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.609661896
Short name T220
Test name
Test status
Simulation time 324732810072 ps
CPU time 769.75 seconds
Started Aug 05 06:12:07 PM PDT 24
Finished Aug 05 06:24:57 PM PDT 24
Peak memory 201468 kb
Host smart-50dbe0ab-bc70-447a-a669-625d2ab3202f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609661896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.609661896
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1513986388
Short name T546
Test name
Test status
Simulation time 323339520346 ps
CPU time 721.04 seconds
Started Aug 05 06:12:13 PM PDT 24
Finished Aug 05 06:24:14 PM PDT 24
Peak memory 201432 kb
Host smart-2ccc339a-1e41-49e0-94ca-80608688ba0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513986388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1513986388
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1749964523
Short name T328
Test name
Test status
Simulation time 497061859360 ps
CPU time 1096.93 seconds
Started Aug 05 06:12:07 PM PDT 24
Finished Aug 05 06:30:24 PM PDT 24
Peak memory 201464 kb
Host smart-49c64f2f-67f7-4193-99b8-4d461e441577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749964523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1749964523
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1977066272
Short name T753
Test name
Test status
Simulation time 164710254146 ps
CPU time 379.96 seconds
Started Aug 05 06:12:08 PM PDT 24
Finished Aug 05 06:18:28 PM PDT 24
Peak memory 201464 kb
Host smart-4ad18742-6f9f-4627-9c1c-0ec41dad66df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977066272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1977066272
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.266162037
Short name T288
Test name
Test status
Simulation time 230954434855 ps
CPU time 539.24 seconds
Started Aug 05 06:12:13 PM PDT 24
Finished Aug 05 06:21:12 PM PDT 24
Peak memory 201408 kb
Host smart-4a22a953-7ec1-4f8d-a84f-1ec19e37eab0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266162037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.266162037
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1937703947
Short name T493
Test name
Test status
Simulation time 412303525435 ps
CPU time 244.42 seconds
Started Aug 05 06:12:12 PM PDT 24
Finished Aug 05 06:16:17 PM PDT 24
Peak memory 201428 kb
Host smart-37004696-7661-4355-a335-d0b8f9b07767
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937703947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1937703947
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1402869757
Short name T207
Test name
Test status
Simulation time 92959692310 ps
CPU time 330.12 seconds
Started Aug 05 06:12:12 PM PDT 24
Finished Aug 05 06:17:43 PM PDT 24
Peak memory 201844 kb
Host smart-63ad4c07-9bc4-4eb0-a539-b4429ba7712a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402869757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1402869757
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2060957329
Short name T701
Test name
Test status
Simulation time 30761687539 ps
CPU time 19.04 seconds
Started Aug 05 06:12:13 PM PDT 24
Finished Aug 05 06:12:32 PM PDT 24
Peak memory 201384 kb
Host smart-ac3d1a2c-9d42-4e09-865b-874bccfd459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060957329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2060957329
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1625020358
Short name T513
Test name
Test status
Simulation time 4517927590 ps
CPU time 1.52 seconds
Started Aug 05 06:12:12 PM PDT 24
Finished Aug 05 06:12:14 PM PDT 24
Peak memory 201360 kb
Host smart-047f59de-9e00-41ed-ad57-1de59d89fd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625020358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1625020358
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.904184303
Short name T745
Test name
Test status
Simulation time 5827164072 ps
CPU time 15.03 seconds
Started Aug 05 06:12:08 PM PDT 24
Finished Aug 05 06:12:23 PM PDT 24
Peak memory 201364 kb
Host smart-b4c8a157-c1c3-4044-bf3b-30233d126c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904184303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.904184303
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1709899206
Short name T21
Test name
Test status
Simulation time 121704697950 ps
CPU time 143.37 seconds
Started Aug 05 06:12:10 PM PDT 24
Finished Aug 05 06:14:34 PM PDT 24
Peak memory 209812 kb
Host smart-3161c91e-a7fb-47a2-8bee-c19187c6e93a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709899206 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1709899206
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1721331655
Short name T457
Test name
Test status
Simulation time 375965902 ps
CPU time 0.96 seconds
Started Aug 05 06:12:32 PM PDT 24
Finished Aug 05 06:12:33 PM PDT 24
Peak memory 201128 kb
Host smart-d98dfd85-99aa-44b7-8f08-f049ff40e88a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721331655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1721331655
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2038764620
Short name T332
Test name
Test status
Simulation time 162305024754 ps
CPU time 168.17 seconds
Started Aug 05 06:12:25 PM PDT 24
Finished Aug 05 06:15:13 PM PDT 24
Peak memory 201432 kb
Host smart-5204c9e5-1890-41a0-9627-f76dfcdd7926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038764620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2038764620
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.760202892
Short name T253
Test name
Test status
Simulation time 492441835467 ps
CPU time 1069.43 seconds
Started Aug 05 06:12:19 PM PDT 24
Finished Aug 05 06:30:09 PM PDT 24
Peak memory 201452 kb
Host smart-57124105-8ab1-4dc8-9c4b-359718ff5452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760202892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.760202892
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.601013405
Short name T687
Test name
Test status
Simulation time 322256651391 ps
CPU time 198.72 seconds
Started Aug 05 06:12:19 PM PDT 24
Finished Aug 05 06:15:38 PM PDT 24
Peak memory 201512 kb
Host smart-c612bbc9-e09b-4ace-a59c-cc8c2309b703
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=601013405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.601013405
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2183241457
Short name T267
Test name
Test status
Simulation time 487973443968 ps
CPU time 524.55 seconds
Started Aug 05 06:12:19 PM PDT 24
Finished Aug 05 06:21:04 PM PDT 24
Peak memory 201444 kb
Host smart-e8527b65-bb0c-460b-a228-436b6262efb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183241457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2183241457
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1788504148
Short name T444
Test name
Test status
Simulation time 165038264639 ps
CPU time 369.71 seconds
Started Aug 05 06:12:17 PM PDT 24
Finished Aug 05 06:18:27 PM PDT 24
Peak memory 201404 kb
Host smart-6b527417-14b9-4ae0-8e58-91ffd9a1c5b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788504148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1788504148
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3692748711
Short name T268
Test name
Test status
Simulation time 542597279746 ps
CPU time 312.46 seconds
Started Aug 05 06:12:24 PM PDT 24
Finished Aug 05 06:17:37 PM PDT 24
Peak memory 201452 kb
Host smart-362e7978-5730-446c-95e1-c9ea91a2fe7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692748711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3692748711
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.262191375
Short name T537
Test name
Test status
Simulation time 595168656182 ps
CPU time 408.78 seconds
Started Aug 05 06:12:24 PM PDT 24
Finished Aug 05 06:19:13 PM PDT 24
Peak memory 201412 kb
Host smart-78c23b94-8846-470a-a6b3-15ca1a45e1f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262191375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.262191375
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3140616773
Short name T204
Test name
Test status
Simulation time 76101524724 ps
CPU time 313.78 seconds
Started Aug 05 06:12:25 PM PDT 24
Finished Aug 05 06:17:38 PM PDT 24
Peak memory 201860 kb
Host smart-f5d41991-14f5-4b88-aa23-82c35fe43cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140616773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3140616773
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3611538613
Short name T644
Test name
Test status
Simulation time 44624671399 ps
CPU time 98.45 seconds
Started Aug 05 06:12:22 PM PDT 24
Finished Aug 05 06:14:01 PM PDT 24
Peak memory 201376 kb
Host smart-6a7874db-04d7-4138-a0ea-3f4582c50edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611538613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3611538613
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.4127609890
Short name T790
Test name
Test status
Simulation time 3093149549 ps
CPU time 8.08 seconds
Started Aug 05 06:12:23 PM PDT 24
Finished Aug 05 06:12:31 PM PDT 24
Peak memory 201380 kb
Host smart-779dac02-b8a5-447c-b26c-a7f05e7db699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127609890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.4127609890
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.726632526
Short name T408
Test name
Test status
Simulation time 6065056629 ps
CPU time 3.62 seconds
Started Aug 05 06:12:17 PM PDT 24
Finished Aug 05 06:12:20 PM PDT 24
Peak memory 201332 kb
Host smart-f6b91e1f-f7a4-499a-b0d6-ab28406a8361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726632526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.726632526
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3270608950
Short name T35
Test name
Test status
Simulation time 258235630743 ps
CPU time 125.62 seconds
Started Aug 05 06:12:24 PM PDT 24
Finished Aug 05 06:14:30 PM PDT 24
Peak memory 201444 kb
Host smart-9995994a-af68-4749-8329-9f6d4766320e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270608950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3270608950
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.399353839
Short name T12
Test name
Test status
Simulation time 64197428534 ps
CPU time 79.46 seconds
Started Aug 05 06:12:24 PM PDT 24
Finished Aug 05 06:13:43 PM PDT 24
Peak memory 210148 kb
Host smart-62df6e2b-f0c9-41e8-8397-929c60bdac54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399353839 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.399353839
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2039975026
Short name T410
Test name
Test status
Simulation time 497202278 ps
CPU time 0.8 seconds
Started Aug 05 06:12:37 PM PDT 24
Finished Aug 05 06:12:38 PM PDT 24
Peak memory 201236 kb
Host smart-57c237e3-9abf-482b-ae46-1100411a8341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039975026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2039975026
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4216576573
Short name T333
Test name
Test status
Simulation time 163935409106 ps
CPU time 99.77 seconds
Started Aug 05 06:12:31 PM PDT 24
Finished Aug 05 06:14:11 PM PDT 24
Peak memory 201448 kb
Host smart-9965eb4a-7520-47db-a4c6-630e310e609f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216576573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4216576573
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3854980097
Short name T343
Test name
Test status
Simulation time 337192258460 ps
CPU time 207.1 seconds
Started Aug 05 06:12:32 PM PDT 24
Finished Aug 05 06:16:00 PM PDT 24
Peak memory 201480 kb
Host smart-3c5286aa-df09-4de2-951e-594a1e84e242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854980097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3854980097
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.4203524001
Short name T709
Test name
Test status
Simulation time 165933743094 ps
CPU time 49.4 seconds
Started Aug 05 06:12:31 PM PDT 24
Finished Aug 05 06:13:20 PM PDT 24
Peak memory 201476 kb
Host smart-dddf684d-f1e3-4642-a63d-d39bdd4d1894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203524001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.4203524001
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1718650258
Short name T647
Test name
Test status
Simulation time 489896003493 ps
CPU time 897.73 seconds
Started Aug 05 06:12:31 PM PDT 24
Finished Aug 05 06:27:28 PM PDT 24
Peak memory 201508 kb
Host smart-2be46f94-b405-4d34-a4b5-2c048beb6cf2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718650258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1718650258
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.418868973
Short name T462
Test name
Test status
Simulation time 166243437750 ps
CPU time 183.7 seconds
Started Aug 05 06:12:31 PM PDT 24
Finished Aug 05 06:15:35 PM PDT 24
Peak memory 201448 kb
Host smart-46f6a124-e79a-46e8-8227-db11738a2d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418868973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.418868973
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3396107778
Short name T758
Test name
Test status
Simulation time 162655457390 ps
CPU time 371.98 seconds
Started Aug 05 06:12:32 PM PDT 24
Finished Aug 05 06:18:44 PM PDT 24
Peak memory 201444 kb
Host smart-f9a2c926-5ddb-4e5d-9780-03dadef60ce3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396107778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3396107778
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1444702629
Short name T591
Test name
Test status
Simulation time 273919989807 ps
CPU time 303.62 seconds
Started Aug 05 06:12:31 PM PDT 24
Finished Aug 05 06:17:35 PM PDT 24
Peak memory 201516 kb
Host smart-a6ebd9a5-65a1-41c6-ba80-12ab95cac70a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444702629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1444702629
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3236100567
Short name T401
Test name
Test status
Simulation time 397599368094 ps
CPU time 240.19 seconds
Started Aug 05 06:12:30 PM PDT 24
Finished Aug 05 06:16:30 PM PDT 24
Peak memory 201428 kb
Host smart-a376813c-b313-4586-8838-d92402e72acb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236100567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3236100567
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1297524065
Short name T534
Test name
Test status
Simulation time 84015729024 ps
CPU time 435.93 seconds
Started Aug 05 06:12:34 PM PDT 24
Finished Aug 05 06:19:50 PM PDT 24
Peak memory 201824 kb
Host smart-827e1e59-787b-4f0c-81ce-8663143c7950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297524065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1297524065
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.133315101
Short name T727
Test name
Test status
Simulation time 22948814228 ps
CPU time 12.92 seconds
Started Aug 05 06:12:36 PM PDT 24
Finished Aug 05 06:12:50 PM PDT 24
Peak memory 201360 kb
Host smart-a9078130-5267-4273-b3f3-2b82315ab999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133315101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.133315101
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2917116809
Short name T561
Test name
Test status
Simulation time 3741494133 ps
CPU time 1.5 seconds
Started Aug 05 06:12:32 PM PDT 24
Finished Aug 05 06:12:33 PM PDT 24
Peak memory 201380 kb
Host smart-838d7a70-46b6-4608-9ee5-9dc88883a625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917116809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2917116809
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1712833054
Short name T475
Test name
Test status
Simulation time 5651881188 ps
CPU time 14.23 seconds
Started Aug 05 06:12:32 PM PDT 24
Finished Aug 05 06:12:47 PM PDT 24
Peak memory 201384 kb
Host smart-d67098a2-eccc-4c71-b2c4-126a30327998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712833054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1712833054
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1393243838
Short name T287
Test name
Test status
Simulation time 497154229127 ps
CPU time 663.63 seconds
Started Aug 05 06:12:37 PM PDT 24
Finished Aug 05 06:23:41 PM PDT 24
Peak memory 210080 kb
Host smart-4ba71ce8-0ae7-426a-8bde-b9bab8ad7001
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393243838 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1393243838
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1615012513
Short name T404
Test name
Test status
Simulation time 513659603 ps
CPU time 0.85 seconds
Started Aug 05 06:12:43 PM PDT 24
Finished Aug 05 06:12:44 PM PDT 24
Peak memory 201252 kb
Host smart-f8883622-46fb-49d2-a195-02d3bc661128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615012513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1615012513
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1290089539
Short name T151
Test name
Test status
Simulation time 487917048346 ps
CPU time 289.97 seconds
Started Aug 05 06:12:36 PM PDT 24
Finished Aug 05 06:17:27 PM PDT 24
Peak memory 201444 kb
Host smart-360d6fd2-46a5-4b4b-9f0d-188a09211041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290089539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1290089539
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.712698534
Short name T447
Test name
Test status
Simulation time 486482578144 ps
CPU time 1128.21 seconds
Started Aug 05 06:12:38 PM PDT 24
Finished Aug 05 06:31:26 PM PDT 24
Peak memory 201472 kb
Host smart-9f9a0d2f-f4dc-4c3c-8ea2-b2ee3430aefc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=712698534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.712698534
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3697230588
Short name T217
Test name
Test status
Simulation time 160374866304 ps
CPU time 268.97 seconds
Started Aug 05 06:12:37 PM PDT 24
Finished Aug 05 06:17:06 PM PDT 24
Peak memory 201424 kb
Host smart-ebd00bba-2bad-4efe-8cc4-6e2aa7d2fd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697230588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3697230588
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.648553128
Short name T85
Test name
Test status
Simulation time 164819836213 ps
CPU time 347.42 seconds
Started Aug 05 06:12:38 PM PDT 24
Finished Aug 05 06:18:25 PM PDT 24
Peak memory 201404 kb
Host smart-c919a641-3add-4dcc-b1cf-a8f848947d97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=648553128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.648553128
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.206095711
Short name T262
Test name
Test status
Simulation time 229386192919 ps
CPU time 240.87 seconds
Started Aug 05 06:12:37 PM PDT 24
Finished Aug 05 06:16:38 PM PDT 24
Peak memory 201448 kb
Host smart-dcfa89e0-9989-4d10-aa05-5395f0bed569
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206095711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.206095711
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.505369980
Short name T674
Test name
Test status
Simulation time 400576343850 ps
CPU time 876.98 seconds
Started Aug 05 06:12:38 PM PDT 24
Finished Aug 05 06:27:15 PM PDT 24
Peak memory 201420 kb
Host smart-492c2fd5-4ba8-4fd2-a06b-4452fde09af4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505369980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.505369980
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3596567386
Short name T609
Test name
Test status
Simulation time 124238359783 ps
CPU time 419.69 seconds
Started Aug 05 06:12:45 PM PDT 24
Finished Aug 05 06:19:45 PM PDT 24
Peak memory 201728 kb
Host smart-7aeb6cc0-79b0-43f0-9c34-01399c76ccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596567386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3596567386
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1153805308
Short name T659
Test name
Test status
Simulation time 28314886105 ps
CPU time 11.26 seconds
Started Aug 05 06:12:43 PM PDT 24
Finished Aug 05 06:12:54 PM PDT 24
Peak memory 201360 kb
Host smart-1e68a820-bad2-428a-924f-2a02a19c9044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153805308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1153805308
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.284356002
Short name T397
Test name
Test status
Simulation time 3409028310 ps
CPU time 8.83 seconds
Started Aug 05 06:12:43 PM PDT 24
Finished Aug 05 06:12:52 PM PDT 24
Peak memory 201360 kb
Host smart-252fb19e-5e98-49b9-b4e2-d5be3a8353a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284356002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.284356002
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1652968418
Short name T756
Test name
Test status
Simulation time 5936787650 ps
CPU time 9.83 seconds
Started Aug 05 06:12:36 PM PDT 24
Finished Aug 05 06:12:46 PM PDT 24
Peak memory 201380 kb
Host smart-41fd2bcd-9879-49f4-89d6-1a49bf563888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652968418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1652968418
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3086443537
Short name T307
Test name
Test status
Simulation time 178344593623 ps
CPU time 412.88 seconds
Started Aug 05 06:12:44 PM PDT 24
Finished Aug 05 06:19:37 PM PDT 24
Peak memory 201512 kb
Host smart-ba16b5f2-3e66-4a32-b55a-5b54fdd02020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086443537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3086443537
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3190208524
Short name T41
Test name
Test status
Simulation time 122721853610 ps
CPU time 67.15 seconds
Started Aug 05 06:12:41 PM PDT 24
Finished Aug 05 06:13:49 PM PDT 24
Peak memory 209992 kb
Host smart-40a03a2e-15bd-4392-8234-77aaded03b4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190208524 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3190208524
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3697102365
Short name T673
Test name
Test status
Simulation time 346304715 ps
CPU time 1.34 seconds
Started Aug 05 06:12:48 PM PDT 24
Finished Aug 05 06:12:49 PM PDT 24
Peak memory 201232 kb
Host smart-9eb078e7-30b7-4d40-9e67-50a95d68e485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697102365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3697102365
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3178733670
Short name T173
Test name
Test status
Simulation time 353984754464 ps
CPU time 173.24 seconds
Started Aug 05 06:12:50 PM PDT 24
Finished Aug 05 06:15:43 PM PDT 24
Peak memory 201460 kb
Host smart-82125d8a-2f3d-44d5-836c-13de8a3b5c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178733670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3178733670
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1293253888
Short name T174
Test name
Test status
Simulation time 502523851769 ps
CPU time 105.57 seconds
Started Aug 05 06:12:45 PM PDT 24
Finished Aug 05 06:14:31 PM PDT 24
Peak memory 201464 kb
Host smart-56bdcca7-e148-4609-92f2-33acb05ebae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293253888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1293253888
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3295900591
Short name T388
Test name
Test status
Simulation time 168579448162 ps
CPU time 396.48 seconds
Started Aug 05 06:12:45 PM PDT 24
Finished Aug 05 06:19:21 PM PDT 24
Peak memory 201460 kb
Host smart-3d922549-4b3a-4c56-8359-ff7d01c30462
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295900591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3295900591
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.47211637
Short name T1
Test name
Test status
Simulation time 168355546554 ps
CPU time 83.2 seconds
Started Aug 05 06:12:43 PM PDT 24
Finished Aug 05 06:14:06 PM PDT 24
Peak memory 201428 kb
Host smart-0ce1f1de-bf9d-460b-ae47-30dd7affcd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47211637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.47211637
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3370447942
Short name T541
Test name
Test status
Simulation time 490821910599 ps
CPU time 554.72 seconds
Started Aug 05 06:12:42 PM PDT 24
Finished Aug 05 06:21:57 PM PDT 24
Peak memory 201464 kb
Host smart-74e2b2f0-5e59-41e5-bb6c-b78864be2b96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370447942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3370447942
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2140087718
Short name T678
Test name
Test status
Simulation time 405502827210 ps
CPU time 176.19 seconds
Started Aug 05 06:12:49 PM PDT 24
Finished Aug 05 06:15:46 PM PDT 24
Peak memory 201456 kb
Host smart-b62bd846-e078-4651-8f80-083f63730236
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140087718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2140087718
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3220215787
Short name T718
Test name
Test status
Simulation time 72357848553 ps
CPU time 261.49 seconds
Started Aug 05 06:12:47 PM PDT 24
Finished Aug 05 06:17:08 PM PDT 24
Peak memory 201844 kb
Host smart-e71437c1-4a59-4e39-b3f8-22a8bc8926c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220215787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3220215787
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1284760899
Short name T549
Test name
Test status
Simulation time 32737878221 ps
CPU time 37.57 seconds
Started Aug 05 06:12:48 PM PDT 24
Finished Aug 05 06:13:26 PM PDT 24
Peak memory 201384 kb
Host smart-a61abbdf-05fa-4b99-9f12-7c0c251f3318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284760899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1284760899
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3762689585
Short name T488
Test name
Test status
Simulation time 5027245243 ps
CPU time 11.24 seconds
Started Aug 05 06:12:48 PM PDT 24
Finished Aug 05 06:13:00 PM PDT 24
Peak memory 201304 kb
Host smart-c34a83c9-b3a8-4bd6-a620-927a7499719e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762689585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3762689585
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3921845986
Short name T420
Test name
Test status
Simulation time 6019394449 ps
CPU time 4.68 seconds
Started Aug 05 06:12:42 PM PDT 24
Finished Aug 05 06:12:47 PM PDT 24
Peak memory 201372 kb
Host smart-6c140250-3ae7-4f24-9aab-acc107a799b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921845986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3921845986
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.590844979
Short name T34
Test name
Test status
Simulation time 495625136332 ps
CPU time 78.63 seconds
Started Aug 05 06:12:46 PM PDT 24
Finished Aug 05 06:14:05 PM PDT 24
Peak memory 201468 kb
Host smart-4da6348a-2433-4138-8ed8-67c809ebbc45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590844979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
590844979
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2201851300
Short name T19
Test name
Test status
Simulation time 40038503925 ps
CPU time 84.8 seconds
Started Aug 05 06:12:48 PM PDT 24
Finished Aug 05 06:14:13 PM PDT 24
Peak memory 209876 kb
Host smart-baa651e2-959e-42f7-86b6-2f5a4540aa09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201851300 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2201851300
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2449004035
Short name T679
Test name
Test status
Simulation time 499058101 ps
CPU time 1.14 seconds
Started Aug 05 06:10:50 PM PDT 24
Finished Aug 05 06:10:51 PM PDT 24
Peak memory 201236 kb
Host smart-7fc1db24-88eb-41a1-9e83-fe2bf7613fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449004035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2449004035
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3486068559
Short name T144
Test name
Test status
Simulation time 158197209720 ps
CPU time 363.55 seconds
Started Aug 05 06:10:21 PM PDT 24
Finished Aug 05 06:16:25 PM PDT 24
Peak memory 201468 kb
Host smart-d0cb5178-73e3-4a8c-a559-1fe86b45f71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486068559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3486068559
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2680574454
Short name T557
Test name
Test status
Simulation time 162080397552 ps
CPU time 181.67 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:13:56 PM PDT 24
Peak memory 201440 kb
Host smart-b379fd2c-8b7b-4f1b-b10c-b4dc374e3427
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680574454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2680574454
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2884839908
Short name T27
Test name
Test status
Simulation time 494878881157 ps
CPU time 300.38 seconds
Started Aug 05 06:10:25 PM PDT 24
Finished Aug 05 06:15:26 PM PDT 24
Peak memory 201444 kb
Host smart-b424f2ea-1f59-4e37-af7f-3b50d77c6196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884839908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2884839908
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2669640469
Short name T499
Test name
Test status
Simulation time 495840023357 ps
CPU time 279.01 seconds
Started Aug 05 06:10:48 PM PDT 24
Finished Aug 05 06:15:27 PM PDT 24
Peak memory 201468 kb
Host smart-8f1dc696-3b29-4115-8f83-4d862da9be37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669640469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2669640469
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3356800501
Short name T799
Test name
Test status
Simulation time 193348761187 ps
CPU time 385 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:16:58 PM PDT 24
Peak memory 201444 kb
Host smart-4b862c99-141a-4886-a830-fbc77f684aa5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356800501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3356800501
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2084312104
Short name T352
Test name
Test status
Simulation time 77267120816 ps
CPU time 296.35 seconds
Started Aug 05 06:10:23 PM PDT 24
Finished Aug 05 06:15:20 PM PDT 24
Peak memory 201904 kb
Host smart-4364c2f0-b0c0-43f3-b396-92a71b0f79ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084312104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2084312104
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1269629795
Short name T443
Test name
Test status
Simulation time 26031441521 ps
CPU time 14.45 seconds
Started Aug 05 06:10:49 PM PDT 24
Finished Aug 05 06:11:04 PM PDT 24
Peak memory 201332 kb
Host smart-289a1564-d286-49a3-8a8b-28a6348bdd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269629795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1269629795
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3617312320
Short name T365
Test name
Test status
Simulation time 3124207877 ps
CPU time 2.53 seconds
Started Aug 05 06:10:27 PM PDT 24
Finished Aug 05 06:10:30 PM PDT 24
Peak memory 201360 kb
Host smart-a35a9b57-9f53-43d0-a177-8b13f711b198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617312320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3617312320
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3599033036
Short name T62
Test name
Test status
Simulation time 3993489459 ps
CPU time 3.62 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:10:58 PM PDT 24
Peak memory 217160 kb
Host smart-0daa6966-76e9-4600-a814-cc6bf6bd5b12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599033036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3599033036
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1924952032
Short name T516
Test name
Test status
Simulation time 5623323515 ps
CPU time 13.14 seconds
Started Aug 05 06:10:20 PM PDT 24
Finished Aug 05 06:10:33 PM PDT 24
Peak memory 201304 kb
Host smart-2e882590-90ec-43f2-8fa4-81eb69da3545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924952032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1924952032
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4271930974
Short name T724
Test name
Test status
Simulation time 79359103553 ps
CPU time 411.4 seconds
Started Aug 05 06:10:45 PM PDT 24
Finished Aug 05 06:17:37 PM PDT 24
Peak memory 201768 kb
Host smart-09c6ff08-4807-413d-bf16-16874da1ea91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271930974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4271930974
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2626565948
Short name T662
Test name
Test status
Simulation time 122176759914 ps
CPU time 68.45 seconds
Started Aug 05 06:10:40 PM PDT 24
Finished Aug 05 06:11:49 PM PDT 24
Peak memory 209872 kb
Host smart-775a7763-6e7c-439d-8aff-8099d8c55fd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626565948 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2626565948
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3148258106
Short name T364
Test name
Test status
Simulation time 320113162 ps
CPU time 1.39 seconds
Started Aug 05 06:13:01 PM PDT 24
Finished Aug 05 06:13:03 PM PDT 24
Peak memory 201148 kb
Host smart-2a40fb7d-e175-4a37-9453-995a25c751ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148258106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3148258106
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2726879592
Short name T313
Test name
Test status
Simulation time 511658432412 ps
CPU time 1203.15 seconds
Started Aug 05 06:12:52 PM PDT 24
Finished Aug 05 06:32:56 PM PDT 24
Peak memory 201336 kb
Host smart-a88d15d4-ed6a-4127-b03a-29d3b3bbbe23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726879592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2726879592
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3101084002
Short name T247
Test name
Test status
Simulation time 525399278130 ps
CPU time 1091.05 seconds
Started Aug 05 06:12:53 PM PDT 24
Finished Aug 05 06:31:04 PM PDT 24
Peak memory 201564 kb
Host smart-4ab0b84e-7299-4388-9713-35481e608413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101084002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3101084002
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.269773614
Short name T616
Test name
Test status
Simulation time 334197877143 ps
CPU time 288.04 seconds
Started Aug 05 06:12:56 PM PDT 24
Finished Aug 05 06:17:44 PM PDT 24
Peak memory 201452 kb
Host smart-a8c0c9ec-1bc0-477d-b292-a95248894040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269773614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.269773614
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3794275745
Short name T511
Test name
Test status
Simulation time 162912062103 ps
CPU time 194.94 seconds
Started Aug 05 06:12:54 PM PDT 24
Finished Aug 05 06:16:09 PM PDT 24
Peak memory 201388 kb
Host smart-e43a5f8d-b3cf-4775-8e64-869240b9fa9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794275745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3794275745
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.412663851
Short name T342
Test name
Test status
Simulation time 327855042066 ps
CPU time 504.77 seconds
Started Aug 05 06:12:55 PM PDT 24
Finished Aug 05 06:21:20 PM PDT 24
Peak memory 201584 kb
Host smart-2d366205-1623-491f-b036-a02e9a8690a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412663851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.412663851
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.889647266
Short name T82
Test name
Test status
Simulation time 488462594058 ps
CPU time 171.8 seconds
Started Aug 05 06:12:53 PM PDT 24
Finished Aug 05 06:15:44 PM PDT 24
Peak memory 201436 kb
Host smart-8105ba69-590b-4d7c-a302-43679640eef1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=889647266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.889647266
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4062916549
Short name T435
Test name
Test status
Simulation time 612653687418 ps
CPU time 1422.62 seconds
Started Aug 05 06:12:55 PM PDT 24
Finished Aug 05 06:36:38 PM PDT 24
Peak memory 201424 kb
Host smart-503c5337-4fbb-4626-831e-e374488c28ba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062916549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4062916549
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.906605632
Short name T615
Test name
Test status
Simulation time 72242488163 ps
CPU time 232.91 seconds
Started Aug 05 06:13:01 PM PDT 24
Finished Aug 05 06:16:54 PM PDT 24
Peak memory 201744 kb
Host smart-d22ba89a-e4cd-4a55-98aa-2613f787c25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906605632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.906605632
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.783997095
Short name T367
Test name
Test status
Simulation time 39658837796 ps
CPU time 22.17 seconds
Started Aug 05 06:12:53 PM PDT 24
Finished Aug 05 06:13:16 PM PDT 24
Peak memory 201376 kb
Host smart-9ebc64e6-7aa8-4a8f-b608-9a17b33c1f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783997095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.783997095
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3529682685
Short name T490
Test name
Test status
Simulation time 4166644702 ps
CPU time 2.29 seconds
Started Aug 05 06:12:54 PM PDT 24
Finished Aug 05 06:12:56 PM PDT 24
Peak memory 201332 kb
Host smart-8422c216-24fd-4745-9e0d-6e714dadfc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529682685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3529682685
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1877592143
Short name T571
Test name
Test status
Simulation time 5685338555 ps
CPU time 7.09 seconds
Started Aug 05 06:12:49 PM PDT 24
Finished Aug 05 06:12:57 PM PDT 24
Peak memory 201376 kb
Host smart-60959779-0d85-4299-b7ea-643ee134eefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877592143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1877592143
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3232993436
Short name T501
Test name
Test status
Simulation time 474921170 ps
CPU time 1.14 seconds
Started Aug 05 06:13:08 PM PDT 24
Finished Aug 05 06:13:09 PM PDT 24
Peak memory 201128 kb
Host smart-766da4a6-79b0-4c5f-bacc-7228150e93cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232993436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3232993436
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2553109130
Short name T248
Test name
Test status
Simulation time 160635208332 ps
CPU time 355.96 seconds
Started Aug 05 06:13:00 PM PDT 24
Finished Aug 05 06:18:57 PM PDT 24
Peak memory 201476 kb
Host smart-b75c77a6-a0c7-42bb-aa9e-4736dc4f3ccf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553109130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2553109130
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.236753935
Short name T734
Test name
Test status
Simulation time 506960346805 ps
CPU time 282.05 seconds
Started Aug 05 06:13:00 PM PDT 24
Finished Aug 05 06:17:43 PM PDT 24
Peak memory 201332 kb
Host smart-d5d8de9d-3d4a-477f-a668-1ffc10f4ec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236753935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.236753935
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2467166508
Short name T505
Test name
Test status
Simulation time 322577444807 ps
CPU time 397.26 seconds
Started Aug 05 06:13:01 PM PDT 24
Finished Aug 05 06:19:39 PM PDT 24
Peak memory 201444 kb
Host smart-28657beb-736a-4d7f-b653-f447da93b2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467166508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2467166508
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.812379301
Short name T360
Test name
Test status
Simulation time 485970985950 ps
CPU time 1057.46 seconds
Started Aug 05 06:13:00 PM PDT 24
Finished Aug 05 06:30:38 PM PDT 24
Peak memory 201448 kb
Host smart-5208df37-6b08-48b7-9978-c14c3a904f94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=812379301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.812379301
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3063965454
Short name T726
Test name
Test status
Simulation time 486411737463 ps
CPU time 1031.4 seconds
Started Aug 05 06:13:00 PM PDT 24
Finished Aug 05 06:30:12 PM PDT 24
Peak memory 201448 kb
Host smart-b9bce9ba-c652-442d-a7b5-31c8dfa1c94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063965454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3063965454
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.835882883
Short name T502
Test name
Test status
Simulation time 488650300180 ps
CPU time 1024.17 seconds
Started Aug 05 06:12:59 PM PDT 24
Finished Aug 05 06:30:03 PM PDT 24
Peak memory 201420 kb
Host smart-f493f444-3deb-47bc-a33e-be338e313433
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=835882883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.835882883
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2637799905
Short name T761
Test name
Test status
Simulation time 174479821141 ps
CPU time 190.01 seconds
Started Aug 05 06:13:03 PM PDT 24
Finished Aug 05 06:16:13 PM PDT 24
Peak memory 201456 kb
Host smart-3ab0e0f3-70f5-4a9f-a98f-5470eafeda43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637799905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2637799905
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1433018400
Short name T157
Test name
Test status
Simulation time 582152292612 ps
CPU time 79.31 seconds
Started Aug 05 06:13:04 PM PDT 24
Finished Aug 05 06:14:23 PM PDT 24
Peak memory 201516 kb
Host smart-24a40812-d388-4754-8364-4510ccd92c8d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433018400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1433018400
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3706931280
Short name T203
Test name
Test status
Simulation time 88965154625 ps
CPU time 480.43 seconds
Started Aug 05 06:13:06 PM PDT 24
Finished Aug 05 06:21:06 PM PDT 24
Peak memory 201840 kb
Host smart-0c163864-8085-42e9-9073-6f8abddb657c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706931280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3706931280
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1870411557
Short name T30
Test name
Test status
Simulation time 23525949151 ps
CPU time 15.01 seconds
Started Aug 05 06:13:09 PM PDT 24
Finished Aug 05 06:13:24 PM PDT 24
Peak memory 201384 kb
Host smart-7c683916-ce56-4656-a535-1400500aefa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870411557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1870411557
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3119542689
Short name T582
Test name
Test status
Simulation time 4382114171 ps
CPU time 10.84 seconds
Started Aug 05 06:13:08 PM PDT 24
Finished Aug 05 06:13:19 PM PDT 24
Peak memory 201392 kb
Host smart-f2ecfd38-df7e-47f1-9a61-8c550bbd69a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119542689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3119542689
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2010018377
Short name T787
Test name
Test status
Simulation time 5722981986 ps
CPU time 2.84 seconds
Started Aug 05 06:13:03 PM PDT 24
Finished Aug 05 06:13:06 PM PDT 24
Peak memory 201384 kb
Host smart-a6e07ff5-b895-4a62-9840-80c035b08c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010018377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2010018377
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2933772592
Short name T255
Test name
Test status
Simulation time 400949131188 ps
CPU time 942.24 seconds
Started Aug 05 06:13:08 PM PDT 24
Finished Aug 05 06:28:51 PM PDT 24
Peak memory 201448 kb
Host smart-af8c36d6-2230-4b2d-bd3e-e56727a48626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933772592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2933772592
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2111580416
Short name T298
Test name
Test status
Simulation time 85635545806 ps
CPU time 127.14 seconds
Started Aug 05 06:13:08 PM PDT 24
Finished Aug 05 06:15:15 PM PDT 24
Peak memory 210464 kb
Host smart-8e16d7ac-c955-4984-bede-a417ea570e5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111580416 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2111580416
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1811715417
Short name T469
Test name
Test status
Simulation time 451592779 ps
CPU time 0.9 seconds
Started Aug 05 06:13:13 PM PDT 24
Finished Aug 05 06:13:14 PM PDT 24
Peak memory 201312 kb
Host smart-bdb869b7-25d9-40c5-85f5-062090c7bfc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811715417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1811715417
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2247936287
Short name T219
Test name
Test status
Simulation time 175539003020 ps
CPU time 185.12 seconds
Started Aug 05 06:13:13 PM PDT 24
Finished Aug 05 06:16:19 PM PDT 24
Peak memory 201448 kb
Host smart-b931a887-a6c8-4a6a-902c-b92eee3cbd03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247936287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2247936287
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2770497215
Short name T565
Test name
Test status
Simulation time 164681992505 ps
CPU time 221.26 seconds
Started Aug 05 06:13:13 PM PDT 24
Finished Aug 05 06:16:55 PM PDT 24
Peak memory 201336 kb
Host smart-d9618936-e467-457d-ae1c-4523f8df2129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770497215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2770497215
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3739431849
Short name T237
Test name
Test status
Simulation time 331689273926 ps
CPU time 754.47 seconds
Started Aug 05 06:13:07 PM PDT 24
Finished Aug 05 06:25:41 PM PDT 24
Peak memory 201464 kb
Host smart-e5164426-53d0-4dfd-9ade-105cd1779421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739431849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3739431849
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4120323705
Short name T419
Test name
Test status
Simulation time 490080107557 ps
CPU time 1110.73 seconds
Started Aug 05 06:13:13 PM PDT 24
Finished Aug 05 06:31:44 PM PDT 24
Peak memory 201528 kb
Host smart-b5a87a60-1cf3-402f-bda1-302232e50e9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120323705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.4120323705
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.857596421
Short name T627
Test name
Test status
Simulation time 159506094428 ps
CPU time 97.4 seconds
Started Aug 05 06:13:06 PM PDT 24
Finished Aug 05 06:14:44 PM PDT 24
Peak memory 201528 kb
Host smart-a119b736-f89f-432e-9815-499ff0c659b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857596421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.857596421
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2960024375
Short name T587
Test name
Test status
Simulation time 166479848240 ps
CPU time 396.34 seconds
Started Aug 05 06:13:08 PM PDT 24
Finished Aug 05 06:19:44 PM PDT 24
Peak memory 201444 kb
Host smart-6ed6baa4-014d-4b9d-ac52-4f14bdc16c80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960024375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2960024375
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.584353674
Short name T597
Test name
Test status
Simulation time 361372657047 ps
CPU time 209.89 seconds
Started Aug 05 06:13:13 PM PDT 24
Finished Aug 05 06:16:43 PM PDT 24
Peak memory 201504 kb
Host smart-95a085f5-0cfa-4ced-a1a7-d1674a8ce2e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584353674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.584353674
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3920996241
Short name T540
Test name
Test status
Simulation time 394902070775 ps
CPU time 917.56 seconds
Started Aug 05 06:13:14 PM PDT 24
Finished Aug 05 06:28:32 PM PDT 24
Peak memory 201440 kb
Host smart-1f1ac015-4be6-46c9-9b2a-f62f51e41cbe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920996241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3920996241
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2969552032
Short name T759
Test name
Test status
Simulation time 23933491268 ps
CPU time 6.85 seconds
Started Aug 05 06:13:14 PM PDT 24
Finished Aug 05 06:13:21 PM PDT 24
Peak memory 201384 kb
Host smart-a4bf575f-ed1e-4252-b8c5-ee0f6d121e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969552032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2969552032
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1436940565
Short name T406
Test name
Test status
Simulation time 5285431498 ps
CPU time 3.71 seconds
Started Aug 05 06:13:13 PM PDT 24
Finished Aug 05 06:13:17 PM PDT 24
Peak memory 201360 kb
Host smart-43ab4484-1465-4088-ad14-0dfb3f8493e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436940565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1436940565
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1592749979
Short name T453
Test name
Test status
Simulation time 5669630438 ps
CPU time 3.82 seconds
Started Aug 05 06:13:06 PM PDT 24
Finished Aug 05 06:13:10 PM PDT 24
Peak memory 201380 kb
Host smart-e91c5e95-1a77-4600-93d2-624046e7e543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592749979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1592749979
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.934417890
Short name T648
Test name
Test status
Simulation time 1563415643239 ps
CPU time 2019.9 seconds
Started Aug 05 06:13:12 PM PDT 24
Finished Aug 05 06:46:53 PM PDT 24
Peak memory 201808 kb
Host smart-378ca93f-451d-47fa-a437-1e13bfb23c2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934417890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
934417890
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3623769573
Short name T37
Test name
Test status
Simulation time 192513715922 ps
CPU time 356.96 seconds
Started Aug 05 06:13:12 PM PDT 24
Finished Aug 05 06:19:10 PM PDT 24
Peak memory 210084 kb
Host smart-577722da-adb4-42b7-b816-749bc908c8df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623769573 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3623769573
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2907008232
Short name T655
Test name
Test status
Simulation time 520822007 ps
CPU time 1.75 seconds
Started Aug 05 06:13:26 PM PDT 24
Finished Aug 05 06:13:28 PM PDT 24
Peak memory 201252 kb
Host smart-5be7d0dc-7c4f-4530-a07f-86b6cdf53eb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907008232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2907008232
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1721641113
Short name T172
Test name
Test status
Simulation time 323581485746 ps
CPU time 133.22 seconds
Started Aug 05 06:13:20 PM PDT 24
Finished Aug 05 06:15:34 PM PDT 24
Peak memory 201396 kb
Host smart-eaf03880-2051-4f06-b0ab-99ef8da86cc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721641113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1721641113
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1485606562
Short name T291
Test name
Test status
Simulation time 515715321321 ps
CPU time 1147.82 seconds
Started Aug 05 06:13:19 PM PDT 24
Finished Aug 05 06:32:27 PM PDT 24
Peak memory 201460 kb
Host smart-43317126-6efb-47b9-b67a-19ffbd2a4e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485606562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1485606562
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1333008974
Short name T336
Test name
Test status
Simulation time 162444236546 ps
CPU time 366.9 seconds
Started Aug 05 06:13:20 PM PDT 24
Finished Aug 05 06:19:27 PM PDT 24
Peak memory 201392 kb
Host smart-1b7486be-a0cf-4bb9-9e73-6929f232ec9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333008974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1333008974
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1521683203
Short name T188
Test name
Test status
Simulation time 496143912076 ps
CPU time 259.86 seconds
Started Aug 05 06:13:18 PM PDT 24
Finished Aug 05 06:17:38 PM PDT 24
Peak memory 201424 kb
Host smart-c984ece0-977d-41f2-82fc-0ea157cce8d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521683203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1521683203
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2172946038
Short name T592
Test name
Test status
Simulation time 164372090404 ps
CPU time 347.94 seconds
Started Aug 05 06:13:20 PM PDT 24
Finished Aug 05 06:19:08 PM PDT 24
Peak memory 201440 kb
Host smart-cdb61dba-981f-4b91-bf0d-ebb4b96cd662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172946038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2172946038
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.232222489
Short name T517
Test name
Test status
Simulation time 169608568206 ps
CPU time 189.66 seconds
Started Aug 05 06:13:20 PM PDT 24
Finished Aug 05 06:16:29 PM PDT 24
Peak memory 201436 kb
Host smart-5324d0a4-4556-4060-aa18-1271dc0e5b2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=232222489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.232222489
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3643255477
Short name T321
Test name
Test status
Simulation time 521811816387 ps
CPU time 287.36 seconds
Started Aug 05 06:13:18 PM PDT 24
Finished Aug 05 06:18:05 PM PDT 24
Peak memory 201452 kb
Host smart-94cfd412-aaa4-4ab5-a9d3-9cb3db934e58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643255477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3643255477
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1519831532
Short name T387
Test name
Test status
Simulation time 580657657069 ps
CPU time 349.71 seconds
Started Aug 05 06:13:17 PM PDT 24
Finished Aug 05 06:19:07 PM PDT 24
Peak memory 201360 kb
Host smart-fdf939b9-a743-432f-8c15-4b9958dab8f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519831532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1519831532
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.921625846
Short name T523
Test name
Test status
Simulation time 97510430973 ps
CPU time 516.93 seconds
Started Aug 05 06:13:20 PM PDT 24
Finished Aug 05 06:21:57 PM PDT 24
Peak memory 201844 kb
Host smart-d9149004-bcb7-4e79-a331-744c828c35c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921625846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.921625846
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.737167169
Short name T456
Test name
Test status
Simulation time 33614718737 ps
CPU time 26.31 seconds
Started Aug 05 06:13:19 PM PDT 24
Finished Aug 05 06:13:45 PM PDT 24
Peak memory 201392 kb
Host smart-97e8cfd1-74f4-438d-ab1f-3c051a423bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737167169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.737167169
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3317167167
Short name T437
Test name
Test status
Simulation time 3887773936 ps
CPU time 9.55 seconds
Started Aug 05 06:13:20 PM PDT 24
Finished Aug 05 06:13:30 PM PDT 24
Peak memory 201244 kb
Host smart-eab5a900-b4b8-4200-8a87-32dbff4b3f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317167167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3317167167
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3293938391
Short name T370
Test name
Test status
Simulation time 5896427948 ps
CPU time 15.29 seconds
Started Aug 05 06:13:18 PM PDT 24
Finished Aug 05 06:13:33 PM PDT 24
Peak memory 201364 kb
Host smart-918c0939-e7d1-466c-97a5-30de5c547b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293938391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3293938391
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1907294217
Short name T302
Test name
Test status
Simulation time 171102311800 ps
CPU time 255.62 seconds
Started Aug 05 06:13:25 PM PDT 24
Finished Aug 05 06:17:41 PM PDT 24
Peak memory 201444 kb
Host smart-2bf4a8fa-c38b-4b17-998a-2cef59f6c2be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907294217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1907294217
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.918453635
Short name T14
Test name
Test status
Simulation time 53668916019 ps
CPU time 55.23 seconds
Started Aug 05 06:13:18 PM PDT 24
Finished Aug 05 06:14:13 PM PDT 24
Peak memory 217972 kb
Host smart-125f318d-2e19-4728-ad6c-7f17fe5c5729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918453635 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.918453635
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3253679158
Short name T710
Test name
Test status
Simulation time 365415244 ps
CPU time 1.53 seconds
Started Aug 05 06:13:32 PM PDT 24
Finished Aug 05 06:13:34 PM PDT 24
Peak memory 201244 kb
Host smart-9c23a0d4-919e-4f25-b4b8-c0ec5cb7957b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253679158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3253679158
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2594571632
Short name T231
Test name
Test status
Simulation time 338809864428 ps
CPU time 386.62 seconds
Started Aug 05 06:13:31 PM PDT 24
Finished Aug 05 06:19:58 PM PDT 24
Peak memory 201524 kb
Host smart-5328ccc2-8ff5-4551-9240-4fd3361a8c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594571632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2594571632
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3291498725
Short name T622
Test name
Test status
Simulation time 332602709927 ps
CPU time 739.36 seconds
Started Aug 05 06:13:25 PM PDT 24
Finished Aug 05 06:25:45 PM PDT 24
Peak memory 201416 kb
Host smart-65c5f436-3ea2-4a35-bf74-b7920f4c2373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291498725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3291498725
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2334171853
Short name T381
Test name
Test status
Simulation time 331536103483 ps
CPU time 253.21 seconds
Started Aug 05 06:13:25 PM PDT 24
Finished Aug 05 06:17:38 PM PDT 24
Peak memory 201512 kb
Host smart-b925e315-03bf-46c2-94a0-866a2cea50a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334171853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2334171853
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1831042023
Short name T198
Test name
Test status
Simulation time 328068287263 ps
CPU time 762.68 seconds
Started Aug 05 06:13:25 PM PDT 24
Finished Aug 05 06:26:08 PM PDT 24
Peak memory 201444 kb
Host smart-799a98bc-28ca-4e1d-9bf9-077d1ab6b661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831042023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1831042023
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2525595441
Short name T651
Test name
Test status
Simulation time 484557530659 ps
CPU time 959.36 seconds
Started Aug 05 06:13:25 PM PDT 24
Finished Aug 05 06:29:24 PM PDT 24
Peak memory 201460 kb
Host smart-a05766e3-62ed-4a1b-b748-42bcdd2ff2d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525595441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2525595441
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2337158053
Short name T589
Test name
Test status
Simulation time 380523806248 ps
CPU time 907.35 seconds
Started Aug 05 06:13:24 PM PDT 24
Finished Aug 05 06:28:32 PM PDT 24
Peak memory 201440 kb
Host smart-65a4b9ca-5212-48cc-b7a3-3ae6e94ffee5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337158053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2337158053
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2812893770
Short name T84
Test name
Test status
Simulation time 609435580180 ps
CPU time 742.77 seconds
Started Aug 05 06:13:25 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201448 kb
Host smart-4dc05d56-920d-4216-a9ac-d488de78def8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812893770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2812893770
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1232182120
Short name T210
Test name
Test status
Simulation time 83539671003 ps
CPU time 413.46 seconds
Started Aug 05 06:13:32 PM PDT 24
Finished Aug 05 06:20:26 PM PDT 24
Peak memory 201836 kb
Host smart-8fe29151-2a3d-41a4-87e0-da0b1f342c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232182120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1232182120
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3029291337
Short name T623
Test name
Test status
Simulation time 24881794541 ps
CPU time 53.57 seconds
Started Aug 05 06:13:31 PM PDT 24
Finished Aug 05 06:14:25 PM PDT 24
Peak memory 201360 kb
Host smart-11c4d379-ea16-47b3-934c-12a56503bf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029291337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3029291337
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2370005430
Short name T677
Test name
Test status
Simulation time 4454149772 ps
CPU time 9.67 seconds
Started Aug 05 06:13:31 PM PDT 24
Finished Aug 05 06:13:41 PM PDT 24
Peak memory 201380 kb
Host smart-3d20b5a4-d496-4638-a212-661997119ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370005430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2370005430
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3936785255
Short name T461
Test name
Test status
Simulation time 5688488412 ps
CPU time 12.23 seconds
Started Aug 05 06:13:26 PM PDT 24
Finished Aug 05 06:13:38 PM PDT 24
Peak memory 201380 kb
Host smart-e2632682-c5a8-4160-a5a8-494e237a0fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936785255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3936785255
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3143214897
Short name T676
Test name
Test status
Simulation time 161456927572 ps
CPU time 341.94 seconds
Started Aug 05 06:13:34 PM PDT 24
Finished Aug 05 06:19:16 PM PDT 24
Peak memory 201492 kb
Host smart-d5fc501d-9856-4a39-9811-5ac0beaf8fe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143214897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3143214897
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1509494746
Short name T636
Test name
Test status
Simulation time 33123006692 ps
CPU time 68.87 seconds
Started Aug 05 06:13:31 PM PDT 24
Finished Aug 05 06:14:40 PM PDT 24
Peak memory 209884 kb
Host smart-954336e5-4b1a-4411-bd1d-724f7713f45d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509494746 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1509494746
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1087954361
Short name T43
Test name
Test status
Simulation time 423070809 ps
CPU time 1.47 seconds
Started Aug 05 06:13:38 PM PDT 24
Finished Aug 05 06:13:40 PM PDT 24
Peak memory 201168 kb
Host smart-6d3a2cef-f81d-45a0-b3d7-dbb75793e9b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087954361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1087954361
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3531940941
Short name T341
Test name
Test status
Simulation time 183401429278 ps
CPU time 110.73 seconds
Started Aug 05 06:13:35 PM PDT 24
Finished Aug 05 06:15:26 PM PDT 24
Peak memory 201536 kb
Host smart-bc7a7b99-d5ba-441f-b72a-5b6d30cdf34a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531940941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3531940941
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1280555
Short name T719
Test name
Test status
Simulation time 161075244900 ps
CPU time 87.61 seconds
Started Aug 05 06:13:31 PM PDT 24
Finished Aug 05 06:14:59 PM PDT 24
Peak memory 201508 kb
Host smart-fef8e941-6bf2-477d-becc-26a690832eb3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt_
fixed.1280555
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1804831351
Short name T183
Test name
Test status
Simulation time 485072598372 ps
CPU time 206.69 seconds
Started Aug 05 06:13:32 PM PDT 24
Finished Aug 05 06:16:59 PM PDT 24
Peak memory 201440 kb
Host smart-81f5a5f0-fdc6-48a2-954c-7ef7dc819440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804831351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1804831351
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1116688871
Short name T105
Test name
Test status
Simulation time 491282351306 ps
CPU time 1102.82 seconds
Started Aug 05 06:13:29 PM PDT 24
Finished Aug 05 06:31:52 PM PDT 24
Peak memory 201424 kb
Host smart-f4f4c55a-2824-4533-85f5-941ebfb6ead3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116688871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1116688871
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1971507269
Short name T620
Test name
Test status
Simulation time 187207860132 ps
CPU time 34.12 seconds
Started Aug 05 06:13:31 PM PDT 24
Finished Aug 05 06:14:05 PM PDT 24
Peak memory 201412 kb
Host smart-2a3ca9ea-0fc1-4624-a472-a66cc03392fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971507269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1971507269
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1659504943
Short name T3
Test name
Test status
Simulation time 92593353842 ps
CPU time 340.89 seconds
Started Aug 05 06:13:39 PM PDT 24
Finished Aug 05 06:19:20 PM PDT 24
Peak memory 201852 kb
Host smart-7e6b5259-2263-4e9d-a78a-262339ceac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659504943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1659504943
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1844852938
Short name T704
Test name
Test status
Simulation time 30495520311 ps
CPU time 73.01 seconds
Started Aug 05 06:13:37 PM PDT 24
Finished Aug 05 06:14:50 PM PDT 24
Peak memory 201344 kb
Host smart-571e98a8-9a72-4427-bed5-77e3d02a6847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844852938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1844852938
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.851420732
Short name T728
Test name
Test status
Simulation time 3964598021 ps
CPU time 2.99 seconds
Started Aug 05 06:13:30 PM PDT 24
Finished Aug 05 06:13:33 PM PDT 24
Peak memory 201364 kb
Host smart-e539b86b-145a-420b-bfab-5e6b93cec6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851420732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.851420732
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.556794839
Short name T390
Test name
Test status
Simulation time 5899610428 ps
CPU time 13.44 seconds
Started Aug 05 06:13:31 PM PDT 24
Finished Aug 05 06:13:44 PM PDT 24
Peak memory 201372 kb
Host smart-33186816-ec1b-4d53-86d4-6ca03cd7dfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556794839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.556794839
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1705154682
Short name T286
Test name
Test status
Simulation time 220222515039 ps
CPU time 131.75 seconds
Started Aug 05 06:13:39 PM PDT 24
Finished Aug 05 06:15:51 PM PDT 24
Peak memory 201428 kb
Host smart-035a2a4a-5d70-433c-bc36-a8e618e5518e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705154682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1705154682
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1294958790
Short name T292
Test name
Test status
Simulation time 67303713766 ps
CPU time 249.67 seconds
Started Aug 05 06:13:35 PM PDT 24
Finished Aug 05 06:17:45 PM PDT 24
Peak memory 211236 kb
Host smart-67112ed5-52d4-41ec-b107-d64ccc4cd04a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294958790 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1294958790
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3503808079
Short name T409
Test name
Test status
Simulation time 518265442 ps
CPU time 1.81 seconds
Started Aug 05 06:13:53 PM PDT 24
Finished Aug 05 06:13:55 PM PDT 24
Peak memory 201236 kb
Host smart-48682ac6-cf84-4d21-8978-5d47b759b02b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503808079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3503808079
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3671393521
Short name T294
Test name
Test status
Simulation time 175357906883 ps
CPU time 399 seconds
Started Aug 05 06:13:44 PM PDT 24
Finished Aug 05 06:20:23 PM PDT 24
Peak memory 201448 kb
Host smart-67c7bd2b-b47a-41dc-a6b7-fca47c974c1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671393521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3671393521
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2610293718
Short name T654
Test name
Test status
Simulation time 326808960592 ps
CPU time 61.34 seconds
Started Aug 05 06:13:44 PM PDT 24
Finished Aug 05 06:14:45 PM PDT 24
Peak memory 201468 kb
Host smart-723dc311-5c4a-44cd-a712-fe38e9da476b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610293718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2610293718
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2915737150
Short name T421
Test name
Test status
Simulation time 502007995840 ps
CPU time 1111.98 seconds
Started Aug 05 06:13:44 PM PDT 24
Finished Aug 05 06:32:16 PM PDT 24
Peak memory 201436 kb
Host smart-a10e3a44-01ad-4297-a05f-cb1ab6aa1f2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915737150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2915737150
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3759050222
Short name T189
Test name
Test status
Simulation time 163130389868 ps
CPU time 378.58 seconds
Started Aug 05 06:13:44 PM PDT 24
Finished Aug 05 06:20:03 PM PDT 24
Peak memory 201424 kb
Host smart-5f4afc48-5ba3-4807-bfb9-1c22447806c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759050222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3759050222
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2495662873
Short name T781
Test name
Test status
Simulation time 576185521607 ps
CPU time 1349.67 seconds
Started Aug 05 06:13:45 PM PDT 24
Finished Aug 05 06:36:14 PM PDT 24
Peak memory 201440 kb
Host smart-d4a960e2-0620-485a-8837-82e78c413fb7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495662873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2495662873
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.784866011
Short name T641
Test name
Test status
Simulation time 201590025584 ps
CPU time 450.6 seconds
Started Aug 05 06:13:44 PM PDT 24
Finished Aug 05 06:21:14 PM PDT 24
Peak memory 201464 kb
Host smart-4ff67b8f-bf91-46f1-a8ce-9ea1bfa71aa5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784866011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.784866011
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.4071733331
Short name T455
Test name
Test status
Simulation time 71032716895 ps
CPU time 410.64 seconds
Started Aug 05 06:13:43 PM PDT 24
Finished Aug 05 06:20:34 PM PDT 24
Peak memory 201908 kb
Host smart-e5e7ecde-4892-4ef0-8648-51d188932c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071733331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.4071733331
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.159664260
Short name T394
Test name
Test status
Simulation time 29299834461 ps
CPU time 70.34 seconds
Started Aug 05 06:13:43 PM PDT 24
Finished Aug 05 06:14:54 PM PDT 24
Peak memory 201324 kb
Host smart-48288b14-0d84-409a-808f-0610f5077928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159664260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.159664260
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.4101993153
Short name T176
Test name
Test status
Simulation time 3108710310 ps
CPU time 4.48 seconds
Started Aug 05 06:13:44 PM PDT 24
Finished Aug 05 06:13:49 PM PDT 24
Peak memory 201384 kb
Host smart-1a0c20cb-acde-4d88-a41b-d7a02b63bbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101993153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.4101993153
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2790004696
Short name T584
Test name
Test status
Simulation time 5640697713 ps
CPU time 13.57 seconds
Started Aug 05 06:13:39 PM PDT 24
Finished Aug 05 06:13:52 PM PDT 24
Peak memory 201372 kb
Host smart-708eb7c2-4a84-4e4d-a300-c6779f7dee92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790004696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2790004696
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3548782925
Short name T713
Test name
Test status
Simulation time 38309556466 ps
CPU time 77.16 seconds
Started Aug 05 06:13:44 PM PDT 24
Finished Aug 05 06:15:01 PM PDT 24
Peak memory 210164 kb
Host smart-06b0cd0d-9b41-4d90-9520-9a5e4a05d44c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548782925 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3548782925
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.218965656
Short name T473
Test name
Test status
Simulation time 398398215 ps
CPU time 1.1 seconds
Started Aug 05 06:13:56 PM PDT 24
Finished Aug 05 06:13:57 PM PDT 24
Peak memory 201256 kb
Host smart-2c477a00-8387-4b86-adca-a9ea6ba30f4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218965656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.218965656
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2146815945
Short name T184
Test name
Test status
Simulation time 329259561851 ps
CPU time 97.38 seconds
Started Aug 05 06:13:55 PM PDT 24
Finished Aug 05 06:15:32 PM PDT 24
Peak memory 201452 kb
Host smart-26bc743d-82e8-47f0-ad23-293f1b9262aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146815945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2146815945
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1156671730
Short name T306
Test name
Test status
Simulation time 164978573636 ps
CPU time 58.38 seconds
Started Aug 05 06:14:00 PM PDT 24
Finished Aug 05 06:14:58 PM PDT 24
Peak memory 201408 kb
Host smart-7f6b2be3-2048-4ae0-9152-33b0a7706426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156671730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1156671730
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3611657074
Short name T575
Test name
Test status
Simulation time 161086136327 ps
CPU time 188.72 seconds
Started Aug 05 06:13:49 PM PDT 24
Finished Aug 05 06:16:58 PM PDT 24
Peak memory 201604 kb
Host smart-255f625f-f7cf-4394-a08e-40fb2c5528b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611657074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3611657074
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2732177689
Short name T631
Test name
Test status
Simulation time 169565596791 ps
CPU time 402 seconds
Started Aug 05 06:13:51 PM PDT 24
Finished Aug 05 06:20:33 PM PDT 24
Peak memory 201500 kb
Host smart-fde8f24b-2726-4865-a352-471b961e26c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732177689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2732177689
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1417848434
Short name T98
Test name
Test status
Simulation time 333792119087 ps
CPU time 385.98 seconds
Started Aug 05 06:13:51 PM PDT 24
Finished Aug 05 06:20:17 PM PDT 24
Peak memory 201464 kb
Host smart-6f3400ad-ef62-41e7-bab9-f46c0048165d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417848434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1417848434
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1994069153
Short name T243
Test name
Test status
Simulation time 399854891660 ps
CPU time 940.7 seconds
Started Aug 05 06:13:48 PM PDT 24
Finished Aug 05 06:29:29 PM PDT 24
Peak memory 201440 kb
Host smart-73802ea3-df52-4a75-80c2-d4a47534c34d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994069153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1994069153
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2519932375
Short name T524
Test name
Test status
Simulation time 612970901291 ps
CPU time 1412.75 seconds
Started Aug 05 06:13:55 PM PDT 24
Finished Aug 05 06:37:28 PM PDT 24
Peak memory 201448 kb
Host smart-cf60acfe-d642-4bae-bc5b-661194bda76a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519932375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2519932375
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3043928578
Short name T211
Test name
Test status
Simulation time 86895197890 ps
CPU time 344.05 seconds
Started Aug 05 06:14:00 PM PDT 24
Finished Aug 05 06:19:44 PM PDT 24
Peak memory 201808 kb
Host smart-0b6a5323-e6da-4c0c-9932-80c0d6317087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043928578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3043928578
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2067858843
Short name T746
Test name
Test status
Simulation time 45099371383 ps
CPU time 48.16 seconds
Started Aug 05 06:13:55 PM PDT 24
Finished Aug 05 06:14:43 PM PDT 24
Peak memory 201360 kb
Host smart-ea3198d4-133c-4d14-934f-e0cc16e55b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067858843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2067858843
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.36733436
Short name T763
Test name
Test status
Simulation time 5009014609 ps
CPU time 3.47 seconds
Started Aug 05 06:13:54 PM PDT 24
Finished Aug 05 06:13:58 PM PDT 24
Peak memory 201448 kb
Host smart-639c0573-e4e6-4d8b-a6ad-26fe9127258c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36733436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.36733436
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.61097924
Short name T393
Test name
Test status
Simulation time 6096890608 ps
CPU time 14.94 seconds
Started Aug 05 06:13:51 PM PDT 24
Finished Aug 05 06:14:06 PM PDT 24
Peak memory 201364 kb
Host smart-9daae8b6-ad0c-4d03-8f6a-53eb9b5f5372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61097924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.61097924
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1206017828
Short name T610
Test name
Test status
Simulation time 71437447076 ps
CPU time 90.04 seconds
Started Aug 05 06:13:55 PM PDT 24
Finished Aug 05 06:15:25 PM PDT 24
Peak memory 210152 kb
Host smart-34e37359-1deb-4423-a961-6c792018c32d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206017828 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1206017828
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2206144305
Short name T414
Test name
Test status
Simulation time 487120435 ps
CPU time 0.81 seconds
Started Aug 05 06:14:13 PM PDT 24
Finished Aug 05 06:14:14 PM PDT 24
Peak memory 201232 kb
Host smart-df4a28a7-2830-40dc-b4db-4a94aca8d626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206144305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2206144305
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3485134629
Short name T275
Test name
Test status
Simulation time 551399177969 ps
CPU time 1181.56 seconds
Started Aug 05 06:14:01 PM PDT 24
Finished Aug 05 06:33:43 PM PDT 24
Peak memory 201532 kb
Host smart-9205a7da-51c8-43b6-b87f-e2b6368942e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485134629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3485134629
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2991771461
Short name T170
Test name
Test status
Simulation time 343835941696 ps
CPU time 68.7 seconds
Started Aug 05 06:14:07 PM PDT 24
Finished Aug 05 06:15:16 PM PDT 24
Peak memory 201472 kb
Host smart-b954e303-ccf0-442b-a39b-9e67658b9c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991771461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2991771461
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.4165743991
Short name T338
Test name
Test status
Simulation time 327343722934 ps
CPU time 616.1 seconds
Started Aug 05 06:14:02 PM PDT 24
Finished Aug 05 06:24:19 PM PDT 24
Peak memory 201384 kb
Host smart-3a264648-3492-489d-9ee3-a57ca614d0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165743991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.4165743991
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1741463172
Short name T147
Test name
Test status
Simulation time 329796478370 ps
CPU time 76.7 seconds
Started Aug 05 06:14:01 PM PDT 24
Finished Aug 05 06:15:18 PM PDT 24
Peak memory 201460 kb
Host smart-d634d807-f6c1-4a98-bd20-6d7821905e69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741463172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1741463172
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1211308401
Short name T218
Test name
Test status
Simulation time 482648848821 ps
CPU time 1013.69 seconds
Started Aug 05 06:13:55 PM PDT 24
Finished Aug 05 06:30:49 PM PDT 24
Peak memory 201440 kb
Host smart-cc0eda48-c4a9-4056-b7e4-0c875ccc8224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211308401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1211308401
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1616721678
Short name T117
Test name
Test status
Simulation time 492518239958 ps
CPU time 218.74 seconds
Started Aug 05 06:14:04 PM PDT 24
Finished Aug 05 06:17:43 PM PDT 24
Peak memory 201468 kb
Host smart-c510e75d-1421-4c15-a623-40b718c377dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616721678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1616721678
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1189235537
Short name T177
Test name
Test status
Simulation time 391868965899 ps
CPU time 210.53 seconds
Started Aug 05 06:14:00 PM PDT 24
Finished Aug 05 06:17:31 PM PDT 24
Peak memory 201456 kb
Host smart-5a60a076-c0ba-48f9-958d-3a46bb474c22
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189235537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1189235537
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1544396365
Short name T566
Test name
Test status
Simulation time 73989318163 ps
CPU time 348.17 seconds
Started Aug 05 06:14:06 PM PDT 24
Finished Aug 05 06:19:55 PM PDT 24
Peak memory 201852 kb
Host smart-a80bc2a9-62aa-40c7-9d5d-13b746a8d4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544396365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1544396365
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.761297683
Short name T467
Test name
Test status
Simulation time 27168704167 ps
CPU time 32.82 seconds
Started Aug 05 06:14:08 PM PDT 24
Finished Aug 05 06:14:41 PM PDT 24
Peak memory 201380 kb
Host smart-c99afc76-93a2-4c97-898f-c71949a32600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761297683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.761297683
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.983518325
Short name T479
Test name
Test status
Simulation time 3055524843 ps
CPU time 2.27 seconds
Started Aug 05 06:14:07 PM PDT 24
Finished Aug 05 06:14:10 PM PDT 24
Peak memory 201356 kb
Host smart-e37b1d16-b8da-4041-9672-77d144ee161f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983518325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.983518325
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1639538999
Short name T625
Test name
Test status
Simulation time 6070332529 ps
CPU time 7.72 seconds
Started Aug 05 06:14:00 PM PDT 24
Finished Aug 05 06:14:08 PM PDT 24
Peak memory 201336 kb
Host smart-990a0a31-860d-4b36-ab49-4255958e3a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639538999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1639538999
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1683792029
Short name T274
Test name
Test status
Simulation time 262063929325 ps
CPU time 876.26 seconds
Started Aug 05 06:14:07 PM PDT 24
Finished Aug 05 06:28:43 PM PDT 24
Peak memory 211976 kb
Host smart-03d08d31-755c-4050-a919-a0477d182495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683792029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1683792029
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.4167392969
Short name T607
Test name
Test status
Simulation time 135800249333 ps
CPU time 241.76 seconds
Started Aug 05 06:14:06 PM PDT 24
Finished Aug 05 06:18:08 PM PDT 24
Peak memory 217592 kb
Host smart-d3b9b8f9-ca5b-4562-8f2b-80d679d1c962
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167392969 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.4167392969
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1309271356
Short name T504
Test name
Test status
Simulation time 485666600 ps
CPU time 1.68 seconds
Started Aug 05 06:14:18 PM PDT 24
Finished Aug 05 06:14:19 PM PDT 24
Peak memory 201244 kb
Host smart-392e3f39-f094-4f09-bce7-1aa8792f0cee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309271356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1309271356
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2219580327
Short name T314
Test name
Test status
Simulation time 534286926534 ps
CPU time 221.99 seconds
Started Aug 05 06:14:17 PM PDT 24
Finished Aug 05 06:17:59 PM PDT 24
Peak memory 201468 kb
Host smart-229fd788-e9a5-4d3c-9230-a33697e6c27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219580327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2219580327
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1071737224
Short name T145
Test name
Test status
Simulation time 168652176516 ps
CPU time 413.86 seconds
Started Aug 05 06:14:14 PM PDT 24
Finished Aug 05 06:21:08 PM PDT 24
Peak memory 201456 kb
Host smart-afda40b6-78de-4bdf-bc8f-66efa5149ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071737224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1071737224
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.605135332
Short name T527
Test name
Test status
Simulation time 490849442733 ps
CPU time 102.97 seconds
Started Aug 05 06:14:18 PM PDT 24
Finished Aug 05 06:16:01 PM PDT 24
Peak memory 201432 kb
Host smart-513eb799-292b-48e5-bac7-43c051eef9bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=605135332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.605135332
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.479923269
Short name T329
Test name
Test status
Simulation time 496700136339 ps
CPU time 1163.4 seconds
Started Aug 05 06:14:13 PM PDT 24
Finished Aug 05 06:33:37 PM PDT 24
Peak memory 201448 kb
Host smart-7880b2b3-de65-46bc-a9b0-2f004a482014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479923269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.479923269
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1687717798
Short name T478
Test name
Test status
Simulation time 493428971538 ps
CPU time 969.04 seconds
Started Aug 05 06:14:14 PM PDT 24
Finished Aug 05 06:30:23 PM PDT 24
Peak memory 201456 kb
Host smart-6f4fca4a-aa06-43a7-b22b-78fda857abd9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687717798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1687717798
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.415648207
Short name T796
Test name
Test status
Simulation time 376964852265 ps
CPU time 225.79 seconds
Started Aug 05 06:14:20 PM PDT 24
Finished Aug 05 06:18:06 PM PDT 24
Peak memory 201476 kb
Host smart-4f0adf0f-f091-4bd2-b422-755d25cc947e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415648207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.415648207
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1718559592
Short name T383
Test name
Test status
Simulation time 387133413784 ps
CPU time 918.75 seconds
Started Aug 05 06:14:20 PM PDT 24
Finished Aug 05 06:29:38 PM PDT 24
Peak memory 201520 kb
Host smart-bf12aea3-d323-47a1-be6b-8e293a50679a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718559592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1718559592
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3350463121
Short name T548
Test name
Test status
Simulation time 87179139165 ps
CPU time 379.99 seconds
Started Aug 05 06:14:18 PM PDT 24
Finished Aug 05 06:20:38 PM PDT 24
Peak memory 201844 kb
Host smart-b630ccf5-b5ba-4a63-89f1-c46efd8a4d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350463121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3350463121
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1017911987
Short name T663
Test name
Test status
Simulation time 21821053766 ps
CPU time 10.09 seconds
Started Aug 05 06:14:19 PM PDT 24
Finished Aug 05 06:14:29 PM PDT 24
Peak memory 201372 kb
Host smart-11812724-0b34-4076-8775-98c9319ec1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017911987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1017911987
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2338697305
Short name T495
Test name
Test status
Simulation time 2547776478 ps
CPU time 6.85 seconds
Started Aug 05 06:14:18 PM PDT 24
Finished Aug 05 06:14:25 PM PDT 24
Peak memory 201384 kb
Host smart-36f62f61-0d2d-4263-bee1-30a5f6a914a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338697305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2338697305
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2988395791
Short name T747
Test name
Test status
Simulation time 5726016145 ps
CPU time 4.28 seconds
Started Aug 05 06:14:10 PM PDT 24
Finished Aug 05 06:14:15 PM PDT 24
Peak memory 201408 kb
Host smart-f3839bf3-e69b-4962-ba7b-96edf7ad0339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988395791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2988395791
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1022432741
Short name T161
Test name
Test status
Simulation time 457126021809 ps
CPU time 917.52 seconds
Started Aug 05 06:14:18 PM PDT 24
Finished Aug 05 06:29:36 PM PDT 24
Peak memory 210036 kb
Host smart-07159ea5-67a0-4493-907a-f0d5b888780d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022432741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1022432741
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3883218858
Short name T40
Test name
Test status
Simulation time 62541533526 ps
CPU time 125.96 seconds
Started Aug 05 06:14:20 PM PDT 24
Finished Aug 05 06:16:26 PM PDT 24
Peak memory 217568 kb
Host smart-b43bdc85-7b15-45ce-93eb-9b03424e6143
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883218858 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3883218858
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.343259758
Short name T653
Test name
Test status
Simulation time 485330018 ps
CPU time 1.77 seconds
Started Aug 05 06:10:51 PM PDT 24
Finished Aug 05 06:10:53 PM PDT 24
Peak memory 201284 kb
Host smart-95bb3002-63f4-4ed8-b583-9d50eeae46f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343259758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.343259758
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3655537211
Short name T325
Test name
Test status
Simulation time 332920174946 ps
CPU time 769.8 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:23:18 PM PDT 24
Peak memory 201456 kb
Host smart-4b75e229-659d-400b-bfcf-364c6854ffa6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655537211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3655537211
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3959064836
Short name T681
Test name
Test status
Simulation time 203515782861 ps
CPU time 128.52 seconds
Started Aug 05 06:10:49 PM PDT 24
Finished Aug 05 06:12:57 PM PDT 24
Peak memory 201460 kb
Host smart-7242e691-01f8-4ef7-8634-54896e0711da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959064836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3959064836
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3885603797
Short name T712
Test name
Test status
Simulation time 157931557010 ps
CPU time 380.12 seconds
Started Aug 05 06:10:48 PM PDT 24
Finished Aug 05 06:17:08 PM PDT 24
Peak memory 201448 kb
Host smart-a7c10ac5-3eac-4cd1-9136-891f463304fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885603797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3885603797
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1433994858
Short name T554
Test name
Test status
Simulation time 327935766791 ps
CPU time 136.39 seconds
Started Aug 05 06:10:49 PM PDT 24
Finished Aug 05 06:13:05 PM PDT 24
Peak memory 201448 kb
Host smart-50f1fcb9-2c9b-4358-81ad-cf7ed9e2205f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433994858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1433994858
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3796974605
Short name T773
Test name
Test status
Simulation time 161285828104 ps
CPU time 71.97 seconds
Started Aug 05 06:10:53 PM PDT 24
Finished Aug 05 06:12:05 PM PDT 24
Peak memory 201468 kb
Host smart-c3dc05d6-883e-4f51-9904-6d7f7e33b757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796974605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3796974605
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.468811522
Short name T626
Test name
Test status
Simulation time 495280451923 ps
CPU time 534.64 seconds
Started Aug 05 06:10:28 PM PDT 24
Finished Aug 05 06:19:23 PM PDT 24
Peak memory 201448 kb
Host smart-b7ae6f5e-af9c-46e5-867e-dce22b2957e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=468811522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.468811522
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2643471692
Short name T331
Test name
Test status
Simulation time 447372338842 ps
CPU time 268.37 seconds
Started Aug 05 06:10:44 PM PDT 24
Finished Aug 05 06:15:12 PM PDT 24
Peak memory 201472 kb
Host smart-30b51307-7f0d-4393-aae2-62acfb8c0093
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643471692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2643471692
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1253477670
Short name T485
Test name
Test status
Simulation time 202115878443 ps
CPU time 116.97 seconds
Started Aug 05 06:10:30 PM PDT 24
Finished Aug 05 06:12:28 PM PDT 24
Peak memory 201440 kb
Host smart-ca279ccc-5d12-439b-87eb-7f929a2792dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253477670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1253477670
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2077672662
Short name T215
Test name
Test status
Simulation time 89365835766 ps
CPU time 377.6 seconds
Started Aug 05 06:10:53 PM PDT 24
Finished Aug 05 06:17:11 PM PDT 24
Peak memory 201928 kb
Host smart-cd02de8a-5f8b-4af3-91f2-986e77afc7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077672662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2077672662
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2679905459
Short name T649
Test name
Test status
Simulation time 44603467448 ps
CPU time 75.55 seconds
Started Aug 05 06:10:45 PM PDT 24
Finished Aug 05 06:12:00 PM PDT 24
Peak memory 201388 kb
Host smart-ea188521-830c-4b66-b949-f605fa791792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679905459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2679905459
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.4011806068
Short name T744
Test name
Test status
Simulation time 3056726288 ps
CPU time 2.28 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:10:56 PM PDT 24
Peak memory 201340 kb
Host smart-9622b36a-d3cf-40d7-9b51-fd6289e2387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011806068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.4011806068
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.566992079
Short name T440
Test name
Test status
Simulation time 5660538075 ps
CPU time 6.82 seconds
Started Aug 05 06:10:53 PM PDT 24
Finished Aug 05 06:11:00 PM PDT 24
Peak memory 201364 kb
Host smart-6b925952-8af2-4fe0-8043-2beb8973b446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566992079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.566992079
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.442614515
Short name T349
Test name
Test status
Simulation time 206379869707 ps
CPU time 491.35 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:19:06 PM PDT 24
Peak memory 201476 kb
Host smart-a6175227-a898-4770-b2b6-837cdd1d92a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442614515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.442614515
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.17067926
Short name T562
Test name
Test status
Simulation time 483937615 ps
CPU time 1.15 seconds
Started Aug 05 06:10:48 PM PDT 24
Finished Aug 05 06:10:49 PM PDT 24
Peak memory 201248 kb
Host smart-350a653f-85ca-448a-86f9-e22d8b6ca6f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17067926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.17067926
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1213300985
Short name T733
Test name
Test status
Simulation time 539999738190 ps
CPU time 249.62 seconds
Started Aug 05 06:10:59 PM PDT 24
Finished Aug 05 06:15:09 PM PDT 24
Peak memory 201464 kb
Host smart-a80e597b-44ce-434e-aa66-679acd05508b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213300985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1213300985
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3670963912
Short name T324
Test name
Test status
Simulation time 488064879117 ps
CPU time 273.67 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:15:29 PM PDT 24
Peak memory 201520 kb
Host smart-b83b6e92-5303-4b96-a802-2def0205cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670963912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3670963912
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2433383512
Short name T748
Test name
Test status
Simulation time 324297799519 ps
CPU time 206.96 seconds
Started Aug 05 06:10:48 PM PDT 24
Finished Aug 05 06:14:15 PM PDT 24
Peak memory 201524 kb
Host smart-46dfe727-978c-4ac7-98b1-c4a67aebdddf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433383512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2433383512
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.472745790
Short name T506
Test name
Test status
Simulation time 163133724368 ps
CPU time 90.01 seconds
Started Aug 05 06:10:59 PM PDT 24
Finished Aug 05 06:12:29 PM PDT 24
Peak memory 201328 kb
Host smart-1501fa17-6728-4677-8119-08659a2e6cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472745790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.472745790
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1026711194
Short name T496
Test name
Test status
Simulation time 332289951980 ps
CPU time 760.35 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:23:36 PM PDT 24
Peak memory 201460 kb
Host smart-9c333046-4ba7-4236-b68f-72519f4006c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026711194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1026711194
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2802206036
Short name T661
Test name
Test status
Simulation time 203909551985 ps
CPU time 455.5 seconds
Started Aug 05 06:11:01 PM PDT 24
Finished Aug 05 06:18:37 PM PDT 24
Peak memory 201456 kb
Host smart-ff7a693b-d19f-4786-87b5-717a8ecd2fdb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802206036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2802206036
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.551135760
Short name T791
Test name
Test status
Simulation time 200898950703 ps
CPU time 107.01 seconds
Started Aug 05 06:10:47 PM PDT 24
Finished Aug 05 06:12:34 PM PDT 24
Peak memory 201436 kb
Host smart-1a838572-cd08-47b1-9bff-8949c7c1c05f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551135760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.551135760
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3100197990
Short name T49
Test name
Test status
Simulation time 114666658683 ps
CPU time 512.35 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:19:27 PM PDT 24
Peak memory 201872 kb
Host smart-643ee3e6-daaa-4d12-aa83-b1deaf48b4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100197990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3100197990
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3739982025
Short name T783
Test name
Test status
Simulation time 22923951084 ps
CPU time 12.89 seconds
Started Aug 05 06:10:48 PM PDT 24
Finished Aug 05 06:11:01 PM PDT 24
Peak memory 201388 kb
Host smart-1a794526-accd-472d-a119-2931a1a6d407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739982025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3739982025
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3991177480
Short name T452
Test name
Test status
Simulation time 4176144294 ps
CPU time 3.04 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:10:58 PM PDT 24
Peak memory 201540 kb
Host smart-ad97d1de-5a02-4d79-b000-c0fcd6dce4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991177480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3991177480
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3865688579
Short name T4
Test name
Test status
Simulation time 5651880124 ps
CPU time 3.85 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:10:58 PM PDT 24
Peak memory 201368 kb
Host smart-0bd1aab0-9c8e-4526-853f-c6ce2e365417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865688579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3865688579
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3065373119
Short name T17
Test name
Test status
Simulation time 381351331185 ps
CPU time 355.19 seconds
Started Aug 05 06:10:51 PM PDT 24
Finished Aug 05 06:16:46 PM PDT 24
Peak memory 210160 kb
Host smart-68cf7ba1-d6c9-4b3d-8b56-fa43dfa53dad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065373119 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3065373119
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1891194646
Short name T376
Test name
Test status
Simulation time 305369501 ps
CPU time 0.77 seconds
Started Aug 05 06:11:00 PM PDT 24
Finished Aug 05 06:11:01 PM PDT 24
Peak memory 201128 kb
Host smart-91fff8bb-8d90-4aa7-af89-f37700313b6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891194646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1891194646
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.606554621
Short name T312
Test name
Test status
Simulation time 335502156463 ps
CPU time 748.43 seconds
Started Aug 05 06:10:52 PM PDT 24
Finished Aug 05 06:23:20 PM PDT 24
Peak memory 201452 kb
Host smart-dff4d68a-f8c0-4bca-8721-cff16416b357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606554621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.606554621
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.588313422
Short name T797
Test name
Test status
Simulation time 160682359604 ps
CPU time 100.01 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:12:37 PM PDT 24
Peak memory 201444 kb
Host smart-98fb95d2-cdfe-4282-bf2a-e0d3fad8e4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588313422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.588313422
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.4168245935
Short name T399
Test name
Test status
Simulation time 164915174125 ps
CPU time 173.44 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:13:47 PM PDT 24
Peak memory 201432 kb
Host smart-8de3c0b5-a488-4839-a0d6-28a2854db0ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168245935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.4168245935
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1331139304
Short name T251
Test name
Test status
Simulation time 163161503530 ps
CPU time 358.4 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:16:56 PM PDT 24
Peak memory 201516 kb
Host smart-5529e67e-26c2-4e75-b00f-2c241942d526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331139304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1331139304
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3855079988
Short name T737
Test name
Test status
Simulation time 319620266809 ps
CPU time 770.69 seconds
Started Aug 05 06:10:48 PM PDT 24
Finished Aug 05 06:23:39 PM PDT 24
Peak memory 201436 kb
Host smart-67d0057b-9ad2-4280-845b-a4167ec6d641
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855079988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3855079988
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3103709563
Short name T99
Test name
Test status
Simulation time 529625384727 ps
CPU time 1273.43 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:32:08 PM PDT 24
Peak memory 201448 kb
Host smart-4fe11704-c17b-41ad-8ef8-72a129d346be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103709563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3103709563
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3021105817
Short name T389
Test name
Test status
Simulation time 414058119730 ps
CPU time 960.03 seconds
Started Aug 05 06:11:02 PM PDT 24
Finished Aug 05 06:27:03 PM PDT 24
Peak memory 201516 kb
Host smart-7e715148-ef40-45ab-ab22-330503c2fa08
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021105817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3021105817
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2174208569
Short name T775
Test name
Test status
Simulation time 124380004199 ps
CPU time 464.2 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:18:43 PM PDT 24
Peak memory 201840 kb
Host smart-14086a44-12d0-427d-998e-534eae4fb879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174208569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2174208569
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.343487197
Short name T380
Test name
Test status
Simulation time 36761933885 ps
CPU time 40.97 seconds
Started Aug 05 06:10:50 PM PDT 24
Finished Aug 05 06:11:31 PM PDT 24
Peak memory 201392 kb
Host smart-13cc99d1-d44a-445d-90e4-e7308c64d550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343487197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.343487197
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1966063472
Short name T521
Test name
Test status
Simulation time 4588670902 ps
CPU time 10.9 seconds
Started Aug 05 06:11:08 PM PDT 24
Finished Aug 05 06:11:19 PM PDT 24
Peak memory 201344 kb
Host smart-8249e725-6f42-4b61-984c-f19de028866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966063472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1966063472
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1259522568
Short name T433
Test name
Test status
Simulation time 5855990837 ps
CPU time 3.72 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:10:58 PM PDT 24
Peak memory 201380 kb
Host smart-0958d865-083a-420d-99ce-2e1ea6d773d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259522568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1259522568
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.447938203
Short name T31
Test name
Test status
Simulation time 342327928643 ps
CPU time 211.98 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:14:29 PM PDT 24
Peak memory 201472 kb
Host smart-afc49257-637d-4e83-bd2f-10518721159f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447938203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.447938203
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1468272163
Short name T13
Test name
Test status
Simulation time 365303074 ps
CPU time 1.5 seconds
Started Aug 05 06:10:50 PM PDT 24
Finished Aug 05 06:10:51 PM PDT 24
Peak memory 201144 kb
Host smart-131dba57-5071-4442-a46c-8968faa1cb0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468272163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1468272163
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2419522523
Short name T760
Test name
Test status
Simulation time 555411270441 ps
CPU time 47.39 seconds
Started Aug 05 06:10:57 PM PDT 24
Finished Aug 05 06:11:44 PM PDT 24
Peak memory 201440 kb
Host smart-594f388f-31d6-42e8-8143-86de57c2a50a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419522523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2419522523
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.4049818599
Short name T295
Test name
Test status
Simulation time 491984633623 ps
CPU time 173.45 seconds
Started Aug 05 06:10:51 PM PDT 24
Finished Aug 05 06:13:45 PM PDT 24
Peak memory 201456 kb
Host smart-b0e34c44-f109-4971-9675-b80933dd0d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049818599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.4049818599
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.497138768
Short name T708
Test name
Test status
Simulation time 166721075555 ps
CPU time 105.69 seconds
Started Aug 05 06:10:56 PM PDT 24
Finished Aug 05 06:12:42 PM PDT 24
Peak memory 201516 kb
Host smart-fd798e1f-1a2a-4893-b14a-2e24af502686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497138768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.497138768
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2377474087
Short name T691
Test name
Test status
Simulation time 330204467850 ps
CPU time 706.08 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:22:40 PM PDT 24
Peak memory 201452 kb
Host smart-6d5da947-fce4-419f-a93f-f90b9429b21c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377474087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2377474087
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1195005475
Short name T293
Test name
Test status
Simulation time 493227932143 ps
CPU time 672.94 seconds
Started Aug 05 06:10:51 PM PDT 24
Finished Aug 05 06:22:04 PM PDT 24
Peak memory 201396 kb
Host smart-c9386a42-70d3-4e18-827e-87650ec6788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195005475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1195005475
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1811535815
Short name T739
Test name
Test status
Simulation time 333920395126 ps
CPU time 234.77 seconds
Started Aug 05 06:10:48 PM PDT 24
Finished Aug 05 06:14:43 PM PDT 24
Peak memory 201424 kb
Host smart-e3c45b58-0fe1-4310-ae30-5f76428063b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811535815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1811535815
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1492139192
Short name T8
Test name
Test status
Simulation time 380794385576 ps
CPU time 201.42 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:14:19 PM PDT 24
Peak memory 201448 kb
Host smart-03c36a33-659c-4a30-8250-907a7458624b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492139192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1492139192
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.114584250
Short name T551
Test name
Test status
Simulation time 212595663459 ps
CPU time 86.25 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:12:24 PM PDT 24
Peak memory 201444 kb
Host smart-e84ee60d-24bd-4d79-986b-db77603aac30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114584250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.114584250
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.93536037
Short name T628
Test name
Test status
Simulation time 111430601683 ps
CPU time 420.92 seconds
Started Aug 05 06:11:03 PM PDT 24
Finished Aug 05 06:18:04 PM PDT 24
Peak memory 201884 kb
Host smart-13b853cf-ea21-4ef3-a439-b58973c746c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93536037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.93536037
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.268324229
Short name T508
Test name
Test status
Simulation time 36816053077 ps
CPU time 25.05 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:11:19 PM PDT 24
Peak memory 201336 kb
Host smart-403fb401-0c68-47a4-83b1-b4eec8860243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268324229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.268324229
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2273520972
Short name T683
Test name
Test status
Simulation time 5229613183 ps
CPU time 13.46 seconds
Started Aug 05 06:10:55 PM PDT 24
Finished Aug 05 06:11:08 PM PDT 24
Peak memory 201364 kb
Host smart-17283978-c174-44dc-a271-615104dd2f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273520972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2273520972
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.270764044
Short name T9
Test name
Test status
Simulation time 5807681223 ps
CPU time 14.54 seconds
Started Aug 05 06:10:59 PM PDT 24
Finished Aug 05 06:11:14 PM PDT 24
Peak memory 201332 kb
Host smart-b687b1a9-79a8-49a1-a846-09f410e6f86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270764044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.270764044
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2971202333
Short name T754
Test name
Test status
Simulation time 361514553094 ps
CPU time 205.21 seconds
Started Aug 05 06:10:56 PM PDT 24
Finished Aug 05 06:14:21 PM PDT 24
Peak memory 201468 kb
Host smart-59cd2494-0ceb-42c2-a04d-5d2d1acb408a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971202333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2971202333
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3311776296
Short name T20
Test name
Test status
Simulation time 29230609379 ps
CPU time 57.45 seconds
Started Aug 05 06:11:01 PM PDT 24
Finished Aug 05 06:11:59 PM PDT 24
Peak memory 209804 kb
Host smart-13c1e982-2268-4258-8775-b6befbe2ab16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311776296 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3311776296
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2265067779
Short name T586
Test name
Test status
Simulation time 455256293 ps
CPU time 0.75 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:10:55 PM PDT 24
Peak memory 201252 kb
Host smart-6d6b828c-17a9-4bfa-9bd1-dd87f5ca7e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265067779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2265067779
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.4243852616
Short name T309
Test name
Test status
Simulation time 444608330681 ps
CPU time 916.26 seconds
Started Aug 05 06:10:58 PM PDT 24
Finished Aug 05 06:26:15 PM PDT 24
Peak memory 201420 kb
Host smart-04427d13-53bf-4a89-b57a-6310b776f9d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243852616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.4243852616
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.989027809
Short name T228
Test name
Test status
Simulation time 529583543190 ps
CPU time 290.66 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:15:45 PM PDT 24
Peak memory 201484 kb
Host smart-e041b320-471f-49dc-bbb4-fd6865d001f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989027809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.989027809
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.257016561
Short name T317
Test name
Test status
Simulation time 494914393009 ps
CPU time 517.93 seconds
Started Aug 05 06:11:13 PM PDT 24
Finished Aug 05 06:19:51 PM PDT 24
Peak memory 201384 kb
Host smart-b1cef11d-b903-4070-9183-0783db500a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257016561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.257016561
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.4133461913
Short name T792
Test name
Test status
Simulation time 492082410863 ps
CPU time 261.5 seconds
Started Aug 05 06:10:56 PM PDT 24
Finished Aug 05 06:15:17 PM PDT 24
Peak memory 201456 kb
Host smart-e165e73a-dce8-4a7a-a63f-5fc468429cc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133461913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.4133461913
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2497042115
Short name T660
Test name
Test status
Simulation time 159916776335 ps
CPU time 79.22 seconds
Started Aug 05 06:10:56 PM PDT 24
Finished Aug 05 06:12:15 PM PDT 24
Peak memory 201456 kb
Host smart-77ad664e-82b0-4025-acc8-3bb84dc627d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497042115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2497042115
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3565459074
Short name T303
Test name
Test status
Simulation time 228289126517 ps
CPU time 237.68 seconds
Started Aug 05 06:10:59 PM PDT 24
Finished Aug 05 06:14:57 PM PDT 24
Peak memory 201452 kb
Host smart-3dc57195-af3d-43c6-a010-00ca89eb84a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565459074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3565459074
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3608361434
Short name T477
Test name
Test status
Simulation time 400812294145 ps
CPU time 949.32 seconds
Started Aug 05 06:10:49 PM PDT 24
Finished Aug 05 06:26:38 PM PDT 24
Peak memory 201408 kb
Host smart-d752befd-6310-4b6f-886a-580a642210f6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608361434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3608361434
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1069001132
Short name T675
Test name
Test status
Simulation time 111769835910 ps
CPU time 592.73 seconds
Started Aug 05 06:10:53 PM PDT 24
Finished Aug 05 06:20:46 PM PDT 24
Peak memory 201896 kb
Host smart-68bda0fd-7e36-4f54-8cb1-60dc7c5a63be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069001132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1069001132
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1255956821
Short name T445
Test name
Test status
Simulation time 47004748120 ps
CPU time 103.26 seconds
Started Aug 05 06:10:59 PM PDT 24
Finished Aug 05 06:12:43 PM PDT 24
Peak memory 201384 kb
Host smart-b244a893-ce87-4fc1-8063-48205738b34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255956821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1255956821
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1455528085
Short name T415
Test name
Test status
Simulation time 3212250595 ps
CPU time 7.86 seconds
Started Aug 05 06:10:49 PM PDT 24
Finished Aug 05 06:10:57 PM PDT 24
Peak memory 201328 kb
Host smart-55545a2b-6fb1-40dc-a056-9bc6328a3aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455528085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1455528085
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3683858819
Short name T729
Test name
Test status
Simulation time 5692106384 ps
CPU time 13.93 seconds
Started Aug 05 06:10:56 PM PDT 24
Finished Aug 05 06:11:10 PM PDT 24
Peak memory 201376 kb
Host smart-ea81f5f2-7c99-4fe5-9b2b-a2287e168c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683858819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3683858819
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2788558929
Short name T272
Test name
Test status
Simulation time 196742934389 ps
CPU time 93.64 seconds
Started Aug 05 06:10:54 PM PDT 24
Finished Aug 05 06:12:27 PM PDT 24
Peak memory 201460 kb
Host smart-a2aae9ac-5d59-4c82-9f4b-3e2b176fdcac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788558929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2788558929
Directory /workspace/9.adc_ctrl_stress_all/latest
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