Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1220618	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1195561

1

T1

455

T2

4223

T3

1412

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2120710	1			T1	819		T2	7993		T3	2558
values[0x0]	147132	1			T1	53		T2	247		T3	153
values[0x1]	148337	1			T1	46		T2	274		T3	157

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	976422	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1439757

1

T1

545

T2

5073

T3

1686

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12561	1			T2	44		T3	8		T4	19
valid_sources[0x01]	11246	1			T2	22		T3	13		T4	21
valid_sources[0x02]	8034	1			T2	40		T3	13		T4	17
valid_sources[0x03]	20007	1			T2	37		T3	3		T4	12
valid_sources[0x04]	7280	1			T2	34		T3	4		T4	21
valid_sources[0x05]	11508	1			T2	39		T3	25		T4	27
valid_sources[0x06]	7502	1			T2	26		T3	14		T4	18
valid_sources[0x07]	9978	1			T2	45		T3	2		T4	13
valid_sources[0x08]	11146	1			T2	31		T3	5		T4	30
valid_sources[0x09]	11126	1			T2	40		T3	6		T4	10
valid_sources[0x0a]	7856	1			T2	31		T3	8		T4	12
valid_sources[0x0b]	15520	1			T2	48		T3	9		T4	15
valid_sources[0x0c]	9359	1			T2	42		T3	19		T4	15
valid_sources[0x0d]	11299	1			T2	26		T3	5		T4	11
valid_sources[0x0e]	7351	1			T2	41		T3	13		T4	13
valid_sources[0x0f]	7422	1			T2	35		T3	14		T4	13
valid_sources[0x10]	6926	1			T2	42		T3	8		T4	19
valid_sources[0x11]	7007	1			T2	16		T4	20		T5	7
valid_sources[0x12]	8799	1			T2	46		T3	10		T4	14
valid_sources[0x13]	7112	1			T2	34		T3	17		T4	12
valid_sources[0x14]	6982	1			T2	31		T3	16		T4	16
valid_sources[0x15]	7410	1			T2	39		T3	3		T4	17
valid_sources[0x16]	12433	1			T2	47		T3	8		T4	20
valid_sources[0x17]	7448	1			T2	30		T3	6		T4	21
valid_sources[0x18]	11230	1			T2	32		T3	7		T4	15
valid_sources[0x19]	7040	1			T2	38		T3	5		T4	16
valid_sources[0x1a]	10176	1			T2	26		T3	7		T4	34
valid_sources[0x1b]	7207	1			T2	42		T3	9		T4	23
valid_sources[0x1c]	8191	1			T2	24		T3	4		T4	9
valid_sources[0x1d]	7170	1			T2	21		T3	6		T4	19
valid_sources[0x1e]	9200	1			T2	18		T3	5		T4	11
valid_sources[0x1f]	9051	1			T2	29		T3	21		T4	16
valid_sources[0x20]	7160	1			T2	24		T3	18		T4	12
valid_sources[0x21]	7212	1			T2	15		T3	6		T4	10
valid_sources[0x22]	14011	1			T2	50		T3	20		T4	24
valid_sources[0x23]	10525	1			T2	37		T3	8		T4	13
valid_sources[0x24]	17041	1			T2	16		T3	23		T4	27
valid_sources[0x25]	7461	1			T2	47		T3	2		T4	22
valid_sources[0x26]	7265	1			T2	36		T3	17		T4	21
valid_sources[0x27]	7866	1			T2	22		T3	12		T4	9
valid_sources[0x28]	8865	1			T2	25		T3	18		T4	16
valid_sources[0x29]	7505	1			T2	50		T3	15		T4	16
valid_sources[0x2a]	9327	1			T2	35		T3	6		T4	19
valid_sources[0x2b]	13056	1			T2	23		T3	23		T4	17
valid_sources[0x2c]	10514	1			T2	24		T3	13		T4	15
valid_sources[0x2d]	7146	1			T2	43		T3	6		T4	17
valid_sources[0x2e]	10147	1			T2	37		T3	13		T4	4
valid_sources[0x2f]	11275	1			T2	29		T3	16		T4	18
valid_sources[0x30]	8889	1			T2	22		T3	4		T4	23
valid_sources[0x31]	9471	1			T2	69		T3	5		T4	15
valid_sources[0x32]	6957	1			T2	22		T3	16		T4	16
valid_sources[0x33]	6797	1			T2	30		T3	6		T4	26
valid_sources[0x34]	8995	1			T2	42		T3	9		T4	17
valid_sources[0x35]	7282	1			T2	30		T3	13		T4	22
valid_sources[0x36]	8038	1			T2	33		T3	2		T4	15
valid_sources[0x37]	7410	1			T2	48		T3	3		T4	24
valid_sources[0x38]	11613	1			T2	49		T3	7		T4	14
valid_sources[0x39]	8247	1			T2	36		T3	4		T4	14
valid_sources[0x3a]	7437	1			T2	30		T3	4		T4	15
valid_sources[0x3b]	7777	1			T2	21		T3	40		T4	18
valid_sources[0x3c]	11435	1			T2	6		T3	26		T4	14
valid_sources[0x3d]	7448	1			T2	17		T3	5		T4	12
valid_sources[0x3e]	12691	1			T2	37		T3	15		T4	15
valid_sources[0x3f]	11499	1			T2	14		T3	12		T4	21
valid_sources[0x40]	10603	1			T2	21		T3	2		T4	26
valid_sources[0x41]	6880	1			T2	32		T3	12		T4	11
valid_sources[0x42]	15511	1			T2	33		T3	24		T4	13
valid_sources[0x43]	11479	1			T2	22		T3	20		T4	13
valid_sources[0x44]	6938	1			T2	24		T3	7		T4	16
valid_sources[0x45]	12563	1			T2	31		T3	6		T4	16
valid_sources[0x46]	15125	1			T2	46		T3	12		T4	16
valid_sources[0x47]	6974	1			T2	28		T3	5		T4	9
valid_sources[0x48]	11190	1			T2	33		T3	10		T4	21
valid_sources[0x49]	11942	1			T2	52		T3	8		T4	23
valid_sources[0x4a]	8068	1			T2	29		T3	2		T4	12
valid_sources[0x4b]	7286	1			T2	44		T3	12		T4	15
valid_sources[0x4c]	7219	1			T2	23		T3	4		T4	21
valid_sources[0x4d]	12467	1			T2	39		T3	4		T4	20
valid_sources[0x4e]	8113	1			T2	29		T3	48		T4	18
valid_sources[0x4f]	6944	1			T2	21		T3	9		T4	12
valid_sources[0x50]	7302	1			T2	28		T3	10		T4	21
valid_sources[0x51]	7920	1			T2	22		T3	4		T4	8
valid_sources[0x52]	7215	1			T2	50		T3	12		T4	18
valid_sources[0x53]	21683	1			T2	29		T3	28		T4	11
valid_sources[0x54]	7055	1			T2	27		T3	14		T4	13
valid_sources[0x55]	7926	1			T2	29		T3	9		T4	19
valid_sources[0x56]	7072	1			T2	34		T3	8		T4	17
valid_sources[0x57]	19926	1			T2	15		T3	5		T4	16
valid_sources[0x58]	7077	1			T2	32		T3	9		T4	18
valid_sources[0x59]	8967	1			T2	45		T3	16		T4	11
valid_sources[0x5a]	9530	1			T2	42		T3	35		T4	15
valid_sources[0x5b]	7411	1			T2	30		T3	11		T4	14
valid_sources[0x5c]	7261	1			T2	36		T3	4		T4	13
valid_sources[0x5d]	6955	1			T2	33		T3	8		T4	13
valid_sources[0x5e]	8675	1			T2	33		T3	22		T4	15
valid_sources[0x5f]	8115	1			T2	26		T3	8		T4	11
valid_sources[0x60]	10089	1			T2	57		T3	4		T4	9
valid_sources[0x61]	10812	1			T2	22		T3	13		T4	15
valid_sources[0x62]	7007	1			T2	27		T3	9		T4	12
valid_sources[0x63]	10524	1			T2	50		T3	5		T4	8
valid_sources[0x64]	7215	1			T2	34		T3	12		T4	16
valid_sources[0x65]	12639	1			T2	46		T3	7		T4	30
valid_sources[0x66]	8648	1			T2	25		T3	8		T4	17
valid_sources[0x67]	6883	1			T2	18		T3	6		T4	17
valid_sources[0x68]	15666	1			T2	47		T3	5		T4	19
valid_sources[0x69]	8177	1			T2	23		T3	27		T4	16
valid_sources[0x6a]	7500	1			T2	54		T3	14		T4	22
valid_sources[0x6b]	10145	1			T2	44		T3	32		T4	12
valid_sources[0x6c]	7255	1			T2	21		T3	4		T4	21
valid_sources[0x6d]	20764	1			T2	21		T3	4		T4	22
valid_sources[0x6e]	7246	1			T2	31		T3	9		T4	12
valid_sources[0x6f]	7358	1			T2	49		T3	16		T4	13
valid_sources[0x70]	8323	1			T2	25		T3	16		T4	10
valid_sources[0x71]	6805	1			T2	38		T3	13		T4	21
valid_sources[0x72]	20027	1			T2	8		T3	9		T4	15
valid_sources[0x73]	7340	1			T2	40		T3	13		T4	23
valid_sources[0x74]	12345	1			T2	20		T3	12		T4	23
valid_sources[0x75]	12026	1			T2	45		T3	13		T4	18
valid_sources[0x76]	9292	1			T2	25		T3	14		T4	21
valid_sources[0x77]	14272	1			T2	20		T3	9		T4	27
valid_sources[0x78]	7176	1			T2	28		T3	5		T4	34
valid_sources[0x79]	7129	1			T2	31		T3	21		T4	22
valid_sources[0x7a]	7147	1			T2	38		T3	5		T4	15
valid_sources[0x7b]	7081	1			T2	38		T3	23		T4	18
valid_sources[0x7c]	16942	1			T2	25		T3	7		T4	12
valid_sources[0x7d]	11164	1			T2	50		T3	5		T4	23
valid_sources[0x7e]	12482	1			T2	40		T3	7		T4	26
valid_sources[0x7f]	16729	1			T2	34		T3	17		T4	20
valid_sources[0x80]	7911	1			T2	39		T3	12		T4	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1056317

1

T1

409

T2

4037

T3

1281

values[0x0]

all_enables

biggest_size

80614

1

T1

28

T2

102

T3

76

values[0x1]

all_enables

biggest_size

58630

1

T1

18

T2

84

T3

55