Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28001	1			T1	6		T2	19		T3	27
auto[PWRUP]	109	1			T7	1		T48	3		T37	1
auto[ONEST_0]	70	1			T48	5		T52	1		T51	2
auto[ONEST_021]	15	1			T50	1		T177	1		T207	1
auto[ONEST_1]	79	1			T48	3		T52	1		T37	1
auto[ONEST_DONE]	5	1			T208	1		T209	1		T210	1
auto[LP_0]	118	1			T7	1		T48	2		T49	5
auto[LP_021]	21	1			T50	1		T208	1		T207	1
auto[LP_1]	111	1			T7	2		T48	1		T52	3
auto[LP_EVAL]	72	1			T7	1		T11	1		T52	1
auto[LP_SLP]	494	1			T7	8		T48	9		T52	4
auto[LP_PWRUP]	32	1			T48	1		T52	1		T50	1
auto[NP_0]	160	1			T7	2		T48	5		T52	5
auto[NP_021]	23	1			T49	1		T195	1		T211	1
auto[NP_1]	119	1			T7	2		T49	2		T50	2
auto[NP_EVAL]	28	1			T7	2		T49	1		T131	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T49

1

T53

1

T208

1

min

27559

1

T1

6

T2

19

T3

27

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27561	1			T1	6		T2	19		T3	27
pow[0x1]	3	1			T212	1		T213	1		T214	1
pow[0x2]	16	1			T48	1		T177	1		T215	1
pow[0x3]	37	1			T11	1		T48	1		T53	1
pow[0x4]	62	1			T7	1		T52	2		T49	1
pow[0x5]	126	1			T7	2		T48	2		T52	1
pow[0x6]	232	1			T7	7		T11	1		T48	6
pow[0x7]	492	1			T7	7		T48	6		T52	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

185

1

T7

5

T48

5

T52

3

min

27073

1

T1

6

T2

19

T3

27

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27073	1			T1	6		T2	19		T3	27
pow[0x3]	1	1			T216	1		-	-		-	-
pow[0x4]	1	1			T217	1		-	-		-	-
pow[0x7]	2	1			T51	1		T195	1		-	-
pow[0x8]	8	1			T50	1		T177	1		T218	1
pow[0x9]	8	1			T48	1		T219	1		T220	1
pow[0xa]	19	1			T49	1		T55	1		T221	1
pow[0xb]	35	1			T7	1		T48	1		T131	1
pow[0xc]	63	1			T11	1		T48	1		T52	1
pow[0xd]	132	1			T7	2		T48	2		T52	2
pow[0xe]	291	1			T7	5		T48	7		T52	4
pow[0xf]	540	1			T7	8		T48	11		T52	5