Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2224	1			T7	14		T11	18		T29	5
auto[PWRUP]	99	1			T7	2		T48	1		T52	1
auto[ONEST_0]	55	1			T7	1		T48	1		T37	1
auto[ONEST_021]	16	1			T38	1		T54	1		T208	2
auto[ONEST_1]	81	1			T7	1		T48	1		T52	1
auto[ONEST_DONE]	5	1			T41	1		T221	1		T334	1
auto[LP_0]	109	1			T49	3		T51	2		T53	1
auto[LP_021]	29	1			T50	2		T51	1		T53	1
auto[LP_1]	135	1			T7	2		T48	4		T37	1
auto[LP_EVAL]	48	1			T7	1		T11	1		T48	1
auto[LP_SLP]	441	1			T7	8		T11	2		T48	12
auto[LP_PWRUP]	29	1			T48	1		T50	1		T131	1
auto[NP_0]	219	1			T7	1		T11	2		T48	5
auto[NP_021]	38	1			T54	1		T177	2		T44	1
auto[NP_1]	216	1			T11	4		T48	4		T52	3
auto[NP_EVAL]	33	1			T11	1		T54	1		T195	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T52

1

T215

1

T355

1

min

1911

1

T7

8

T11

25

T29

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1916	1			T7	9		T11	25		T29	5
pow[0x1]	13	1			T54	1		T239	1		T93	1
pow[0x2]	11	1			T37	1		T131	2		T221	1
pow[0x3]	34	1			T7	1		T52	1		T51	1
pow[0x4]	54	1			T48	2		T49	1		T50	1
pow[0x5]	115	1			T7	2		T48	5		T49	5
pow[0x6]	226	1			T7	5		T48	7		T52	1
pow[0x7]	463	1			T7	5		T11	2		T48	13

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

177

1

T7

4

T11

1

T48

2

min

1362

1

T7

1

T11

18

T29

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1368	1			T7	1		T11	18		T29	5
pow[0x1]	36	1			T41	1		T42	4		T44	1
pow[0x2]	19	1			T37	1		T41	2		T46	1
pow[0x3]	38	1			T11	3		T40	1		T42	1
pow[0x4]	71	1			T11	4		T37	3		T38	3
pow[0x6]	1	1			T356	1		-	-		-	-
pow[0x7]	1	1			T213	1		-	-		-	-
pow[0x8]	6	1			T213	1		T357	1		T216	1
pow[0x9]	3	1			T7	1		T239	1		T358	1
pow[0xa]	24	1			T48	1		T49	1		T50	2
pow[0xb]	29	1			T7	1		T48	1		T37	1
pow[0xc]	61	1			T48	1		T52	1		T50	1
pow[0xd]	126	1			T7	1		T11	1		T48	1
pow[0xe]	280	1			T7	3		T48	11		T52	2
pow[0xf]	529	1			T7	4		T48	17		T52	5