Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1658	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1796	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1518	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1515	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1605	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1771	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1675	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1615	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1670	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1623	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1656	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1520	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1683	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1722	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1515	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1647	0	0
adc_en_ctl_rd_A	2147483647	1434	0	0
adc_fsm_rst_rd_A	2147483647	1159	0	0
adc_intr_ctl_rd_A	2147483647	1798	0	0
adc_lp_sample_ctl_rd_A	2147483647	1193	0	0
adc_pd_ctl_rd_A	2147483647	1569	0	0
adc_sample_ctl_rd_A	2147483647	1153	0	0
adc_wakeup_ctl_rd_A	2147483647	1376	0	0
intr_enable_rd_A	2147483647	1823	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1658	0	0
T11	725647	42	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	23	0	0
T18	0	23	0	0
T19	0	20	0	0
T20	0	26	0	0
T21	0	15	0	0
T22	0	43	0	0
T23	0	4	0	0
T24	0	39	0	0
T25	0	7	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1796	0	0
T11	725647	51	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	33	0	0
T18	0	23	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	0	8	0	0
T22	0	29	0	0
T23	0	3	0	0
T24	0	35	0	0
T25	0	9	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1518	0	0
T11	725647	36	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	22	0	0
T18	0	21	0	0
T19	0	21	0	0
T20	0	30	0	0
T21	0	10	0	0
T22	0	55	0	0
T23	0	8	0	0
T24	0	26	0	0
T25	0	8	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1515	0	0
T11	725647	42	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	33	0	0
T18	0	23	0	0
T19	0	18	0	0
T20	0	40	0	0
T21	0	7	0	0
T22	0	36	0	0
T24	0	11	0	0
T25	0	4	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0
T32	0	95	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1605	0	0
T11	725647	30	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	15	0	0
T18	0	26	0	0
T19	0	22	0	0
T20	0	31	0	0
T21	0	7	0	0
T22	0	52	0	0
T23	0	5	0	0
T24	0	44	0	0
T25	0	3	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1771	0	0
T11	725647	45	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	24	0	0
T18	0	21	0	0
T19	0	16	0	0
T20	0	30	0	0
T21	0	14	0	0
T22	0	52	0	0
T24	0	27	0	0
T25	0	8	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0
T32	0	117	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1675	0	0
T11	725647	61	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	29	0	0
T18	0	20	0	0
T19	0	21	0	0
T20	0	32	0	0
T21	0	12	0	0
T22	0	42	0	0
T23	0	1	0	0
T24	0	23	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0
T32	0	92	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1615	0	0
T11	725647	43	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	15	0	0
T18	0	23	0	0
T19	0	22	0	0
T20	0	28	0	0
T21	0	12	0	0
T22	0	47	0	0
T23	0	1	0	0
T24	0	34	0	0
T25	0	3	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1670	0	0
T11	725647	29	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	33	0	0
T18	0	19	0	0
T19	0	18	0	0
T20	0	59	0	0
T21	0	19	0	0
T22	0	50	0	0
T23	0	7	0	0
T24	0	38	0	0
T25	0	10	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1623	0	0
T11	725647	23	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	42	0	0
T18	0	18	0	0
T19	0	24	0	0
T20	0	22	0	0
T21	0	15	0	0
T22	0	31	0	0
T23	0	4	0	0
T24	0	33	0	0
T25	0	9	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1656	0	0
T11	725647	37	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	22	0	0
T18	0	8	0	0
T19	0	18	0	0
T20	0	28	0	0
T21	0	10	0	0
T22	0	40	0	0
T23	0	2	0	0
T24	0	26	0	0
T25	0	9	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1520	0	0
T11	725647	32	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	20	0	0
T18	0	22	0	0
T19	0	10	0	0
T20	0	26	0	0
T21	0	11	0	0
T22	0	38	0	0
T23	0	4	0	0
T24	0	20	0	0
T25	0	6	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1683	0	0
T11	725647	29	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	35	0	0
T18	0	17	0	0
T19	0	21	0	0
T20	0	32	0	0
T21	0	23	0	0
T22	0	47	0	0
T23	0	17	0	0
T24	0	22	0	0
T25	0	5	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1722	0	0
T11	725647	29	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	38	0	0
T18	0	21	0	0
T19	0	19	0	0
T20	0	27	0	0
T21	0	6	0	0
T22	0	28	0	0
T24	0	35	0	0
T25	0	5	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0
T32	0	89	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1515	0	0
T11	725647	38	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	22	0	0
T18	0	31	0	0
T19	0	7	0	0
T20	0	25	0	0
T21	0	12	0	0
T22	0	43	0	0
T23	0	9	0	0
T24	0	13	0	0
T25	0	2	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1647	0	0
T11	725647	38	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	35	0	0
T18	0	16	0	0
T19	0	21	0	0
T20	0	47	0	0
T21	0	14	0	0
T22	0	42	0	0
T23	0	13	0	0
T24	0	17	0	0
T25	0	1	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1434	0	0
T11	725647	41	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	22	0	0
T18	0	16	0	0
T19	0	17	0	0
T20	0	27	0	0
T21	0	20	0	0
T22	0	54	0	0
T23	0	11	0	0
T24	0	29	0	0
T25	0	6	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1159	0	0
T11	725647	40	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	24	0	0
T18	0	31	0	0
T19	0	13	0	0
T20	0	19	0	0
T21	0	2	0	0
T22	0	53	0	0
T23	0	8	0	0
T24	0	13	0	0
T25	0	10	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1798	0	0
T11	725647	35	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	20	0	0
T18	0	11	0	0
T19	0	31	0	0
T20	0	39	0	0
T21	0	1	0	0
T22	0	37	0	0
T23	0	3	0	0
T24	0	27	0	0
T25	0	9	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1193	0	0
T11	725647	38	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	40	0	0
T18	0	25	0	0
T19	0	10	0	0
T20	0	31	0	0
T21	0	24	0	0
T22	0	28	0	0
T23	0	1	0	0
T24	0	22	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0
T32	0	38	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1569	0	0
T11	725647	37	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	35	0	0
T18	0	16	0	0
T19	0	23	0	0
T20	0	31	0	0
T21	0	8	0	0
T22	0	29	0	0
T23	0	15	0	0
T24	0	26	0	0
T25	0	9	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1153	0	0
T11	725647	35	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	34	0	0
T18	0	13	0	0
T19	0	13	0	0
T20	0	43	0	0
T21	0	17	0	0
T22	0	38	0	0
T23	0	10	0	0
T24	0	17	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0
T32	0	33	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1376	0	0
T11	725647	47	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	22	0	0
T18	0	20	0	0
T19	0	20	0	0
T20	0	40	0	0
T21	0	2	0	0
T22	0	53	0	0
T23	0	4	0	0
T24	0	11	0	0
T25	0	2	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1823	0	0
T11	725647	48	0	0
T12	467137	0	0	0
T13	318125	0	0	0
T14	415893	0	0	0
T17	0	37	0	0
T18	0	43	0	0
T19	0	22	0	0
T20	0	39	0	0
T21	0	18	0	0
T26	89063	0	0	0
T27	312056	0	0	0
T28	281369	0	0	0
T29	105755	0	0	0
T30	468645	0	0	0
T31	163919	0	0	0
T33	0	12	0	0
T34	0	22	0	0
T35	0	16	0	0
T36	0	14	0	0