Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1181579	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1155217

1

T1

1421

T2

1410

T3

1406

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2044938	1			T1	2532		T2	2550		T3	2514
values[0x0]	145687	1			T1	153		T2	136		T3	143
values[0x1]	146171	1			T1	150		T2	120		T3	164

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	946508	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1390288

1

T1

1691

T2

1731

T3

1689

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11419	1			T1	7		T2	8		T3	6
valid_sources[0x01]	8928	1			T1	7		T2	13		T3	3
valid_sources[0x02]	10474	1			T1	4		T2	10		T3	7
valid_sources[0x03]	6839	1			T1	4		T2	13		T3	15
valid_sources[0x04]	8683	1			T1	965		T2	10		T3	10
valid_sources[0x05]	6704	1			T1	1		T2	9		T3	6
valid_sources[0x06]	6917	1			T2	6		T3	13		T4	9
valid_sources[0x07]	11668	1			T1	2		T2	21		T3	9
valid_sources[0x08]	11329	1			T1	5		T2	21		T3	22
valid_sources[0x09]	9359	1			T1	8		T2	3		T4	2
valid_sources[0x0a]	6612	1			T1	6		T2	6		T3	6
valid_sources[0x0b]	7243	1			T1	6		T2	9		T3	9
valid_sources[0x0c]	6634	1			T2	5		T3	8		T4	5
valid_sources[0x0d]	10404	1			T1	6		T2	4		T3	16
valid_sources[0x0e]	7955	1			T1	8		T2	12		T3	17
valid_sources[0x0f]	7965	1			T1	2		T2	16		T3	6
valid_sources[0x10]	6776	1			T1	8		T2	15		T3	16
valid_sources[0x11]	8741	1			T1	7		T2	14		T3	9
valid_sources[0x12]	6622	1			T1	3		T2	3		T3	9
valid_sources[0x13]	24501	1			T1	2		T2	8		T3	19
valid_sources[0x14]	7772	1			T2	17		T3	3		T4	11
valid_sources[0x15]	6846	1			T2	9		T3	10		T4	4
valid_sources[0x16]	6939	1			T1	4		T2	12		T3	7
valid_sources[0x17]	6778	1			T2	7		T3	16		T4	10
valid_sources[0x18]	7748	1			T1	1		T2	6		T3	14
valid_sources[0x19]	7486	1			T1	4		T2	5		T3	4
valid_sources[0x1a]	6812	1			T1	5		T2	18		T3	18
valid_sources[0x1b]	6977	1			T1	4		T2	11		T3	4
valid_sources[0x1c]	13154	1			T1	9		T2	10		T3	14
valid_sources[0x1d]	7778	1			T1	5		T2	8		T3	21
valid_sources[0x1e]	14086	1			T2	12		T3	6		T4	7
valid_sources[0x1f]	9563	1			T1	7		T2	16		T3	10
valid_sources[0x20]	7747	1			T1	3		T2	7		T3	9
valid_sources[0x21]	9532	1			T1	9		T2	12		T3	4
valid_sources[0x22]	12253	1			T2	7		T3	2		T4	6
valid_sources[0x23]	13209	1			T1	3		T2	9		T3	8
valid_sources[0x24]	7084	1			T1	13		T2	18		T3	9
valid_sources[0x25]	6759	1			T1	1		T2	7		T3	22
valid_sources[0x26]	11583	1			T1	3		T2	8		T3	15
valid_sources[0x27]	10970	1			T2	8		T3	11		T4	3
valid_sources[0x28]	6668	1			T1	3		T2	9		T3	15
valid_sources[0x29]	7057	1			T1	6		T2	8		T3	10
valid_sources[0x2a]	7239	1			T1	6		T2	11		T3	28
valid_sources[0x2b]	6622	1			T1	3		T2	7		T3	7
valid_sources[0x2c]	7806	1			T1	10		T2	13		T3	9
valid_sources[0x2d]	7989	1			T1	1		T2	18		T3	10
valid_sources[0x2e]	7895	1			T1	1		T2	10		T3	6
valid_sources[0x2f]	11416	1			T2	14		T3	23		T4	9
valid_sources[0x30]	11612	1			T1	6		T2	8		T3	9
valid_sources[0x31]	9814	1			T1	5		T2	20		T3	8
valid_sources[0x32]	7266	1			T2	8		T3	11		T4	10
valid_sources[0x33]	6825	1			T1	4		T2	12		T3	7
valid_sources[0x34]	6895	1			T1	4		T2	15		T3	9
valid_sources[0x35]	10712	1			T1	1		T2	18		T3	6
valid_sources[0x36]	9374	1			T1	3		T2	4		T3	5
valid_sources[0x37]	10921	1			T1	5		T2	8		T3	6
valid_sources[0x38]	7139	1			T1	6		T2	16		T3	7
valid_sources[0x39]	7664	1			T1	11		T2	15		T3	8
valid_sources[0x3a]	6515	1			T1	4		T2	7		T3	17
valid_sources[0x3b]	16743	1			T1	7		T2	11		T3	10
valid_sources[0x3c]	9675	1			T1	2		T2	13		T3	21
valid_sources[0x3d]	10240	1			T1	1		T2	12		T3	10
valid_sources[0x3e]	9591	1			T2	15		T3	15		T4	6
valid_sources[0x3f]	6625	1			T1	6		T2	7		T3	15
valid_sources[0x40]	8133	1			T1	1		T2	8		T3	10
valid_sources[0x41]	9232	1			T1	1		T2	8		T3	21
valid_sources[0x42]	18061	1			T1	2		T2	18		T3	7
valid_sources[0x43]	7311	1			T1	4		T2	9		T3	9
valid_sources[0x44]	11326	1			T2	11		T3	8		T4	5
valid_sources[0x45]	11798	1			T1	3		T2	24		T3	14
valid_sources[0x46]	11367	1			T1	8		T2	6		T3	10
valid_sources[0x47]	10857	1			T2	18		T3	13		T4	3
valid_sources[0x48]	6898	1			T1	6		T2	12		T3	11
valid_sources[0x49]	7691	1			T2	7		T3	8		T4	5
valid_sources[0x4a]	7093	1			T1	1		T2	12		T3	7
valid_sources[0x4b]	12578	1			T1	3		T2	8		T3	7
valid_sources[0x4c]	8739	1			T1	2		T2	19		T3	15
valid_sources[0x4d]	6765	1			T1	5		T2	13		T3	2
valid_sources[0x4e]	13540	1			T1	13		T2	12		T3	14
valid_sources[0x4f]	7295	1			T1	7		T2	15		T3	9
valid_sources[0x50]	6746	1			T1	1		T2	11		T3	7
valid_sources[0x51]	11818	1			T1	4		T2	17		T3	9
valid_sources[0x52]	6877	1			T1	2		T2	5		T3	8
valid_sources[0x53]	7056	1			T1	4		T2	19		T3	11
valid_sources[0x54]	7840	1			T1	6		T2	8		T3	11
valid_sources[0x55]	6805	1			T1	2		T2	6		T3	6
valid_sources[0x56]	10969	1			T1	5		T2	8		T3	4
valid_sources[0x57]	7599	1			T1	5		T2	14		T3	12
valid_sources[0x58]	6778	1			T1	8		T2	6		T3	9
valid_sources[0x59]	6982	1			T1	8		T2	8		T3	5
valid_sources[0x5a]	7051	1			T1	1		T2	16		T3	3
valid_sources[0x5b]	7533	1			T1	6		T2	8		T3	5
valid_sources[0x5c]	6744	1			T1	3		T2	16		T3	9
valid_sources[0x5d]	6601	1			T1	2		T2	8		T3	5
valid_sources[0x5e]	7388	1			T1	2		T2	9		T3	16
valid_sources[0x5f]	7816	1			T1	5		T2	6		T3	27
valid_sources[0x60]	9920	1			T1	3		T2	15		T3	23
valid_sources[0x61]	9411	1			T1	7		T2	18		T3	2
valid_sources[0x62]	8894	1			T1	3		T2	8		T3	10
valid_sources[0x63]	8912	1			T1	2		T2	7		T3	35
valid_sources[0x64]	11101	1			T1	13		T2	7		T3	15
valid_sources[0x65]	10396	1			T1	8		T2	14		T3	12
valid_sources[0x66]	11192	1			T2	20		T3	8		T4	8
valid_sources[0x67]	6714	1			T1	2		T2	19		T3	14
valid_sources[0x68]	7741	1			T1	7		T2	21		T3	19
valid_sources[0x69]	6702	1			T1	5		T2	6		T3	13
valid_sources[0x6a]	11699	1			T1	2		T2	4		T3	21
valid_sources[0x6b]	7270	1			T1	2		T2	13		T3	6
valid_sources[0x6c]	12400	1			T1	1		T2	12		T3	8
valid_sources[0x6d]	7042	1			T1	2		T2	10		T3	2
valid_sources[0x6e]	10694	1			T1	2		T2	7		T3	24
valid_sources[0x6f]	8854	1			T1	1		T2	15		T3	7
valid_sources[0x70]	11928	1			T2	15		T3	2		T4	4
valid_sources[0x71]	7012	1			T1	4		T2	6		T3	5
valid_sources[0x72]	6412	1			T1	5		T2	12		T3	10
valid_sources[0x73]	6712	1			T1	1		T2	5		T3	6
valid_sources[0x74]	7082	1			T1	1		T2	6		T3	4
valid_sources[0x75]	8522	1			T1	4		T2	14		T3	8
valid_sources[0x76]	11276	1			T1	3		T2	6		T3	21
valid_sources[0x77]	7931	1			T1	1		T2	16		T3	7
valid_sources[0x78]	9705	1			T1	2		T2	7		T3	13
valid_sources[0x79]	6458	1			T1	3		T2	9		T3	5
valid_sources[0x7a]	7129	1			T1	4		T2	15		T3	16
valid_sources[0x7b]	6824	1			T1	2		T2	7		T3	20
valid_sources[0x7c]	6779	1			T1	2		T2	6		T3	20
valid_sources[0x7d]	12504	1			T1	1		T2	3		T3	9
valid_sources[0x7e]	6597	1			T1	2		T2	10		T3	17
valid_sources[0x7f]	10544	1			T2	4		T3	12		T4	3
valid_sources[0x80]	10625	1			T1	3		T2	19		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1018404

1

T1

1273

T2

1303

T3

1256

values[0x0]

all_enables

biggest_size

79521

1

T1

87

T2

64

T3

90

values[0x1]

all_enables

biggest_size

57292

1

T1

61

T2

43

T3

60