Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
84.44	84.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	84.44	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	7	38	84.44

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	6	10	62.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30133	1			T1	27		T2	14		T3	27
auto[PWRUP]	95	1			T66	3		T69	1		T71	1
auto[ONEST_0]	72	1			T74	1		T68	1		T223	2
auto[ONEST_021]	16	1			T66	1		T67	1		T223	1
auto[ONEST_1]	83	1			T66	2		T67	1		T74	1
auto[ONEST_DONE]	5	1			T66	1		T123	1		T224	1
auto[LP_0]	114	1			T71	1		T74	1		T68	3
auto[LP_021]	21	1			T67	2		T188	2		T29	1
auto[LP_1]	128	1			T66	2		T69	1		T71	3
auto[LP_EVAL]	64	1			T66	1		T71	1		T67	2
auto[LP_SLP]	500	1			T66	5		T69	5		T71	7
auto[LP_PWRUP]	20	1			T71	1		T70	1		T188	2
auto[NP_0]	145	1			T66	1		T69	2		T71	4
auto[NP_021]	32	1			T71	4		T67	1		T188	1
auto[NP_1]	144	1			T66	2		T71	1		T74	1
auto[NP_EVAL]	33	1			T69	1		T70	1		T46	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T70

1

T53

1

T225

1

min

29621

1

T1

27

T2

14

T3

27

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29630	1			T1	27		T2	14		T3	27
pow[0x1]	7	1			T69	1		T223	1		T226	1
pow[0x2]	17	1			T71	1		T67	2		T25	1
pow[0x3]	25	1			T66	1		T188	1		T29	1
pow[0x4]	63	1			T66	1		T69	1		T68	2
pow[0x5]	127	1			T66	4		T69	3		T67	2
pow[0x6]	237	1			T11	1		T66	2		T69	1
pow[0x7]	525	1			T66	5		T69	2		T71	11

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

173

1

T66

2

T71

2

T67

2

min

29151

1

T1

27

T2

14

T3

27

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	6	10	62.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29151	1			T1	27		T2	14		T3	27
pow[0x6]	1	1			T227	1		-	-		-	-
pow[0x8]	3	1			T228	1		T224	1		T229	1
pow[0x9]	10	1			T25	1		T75	1		T230	1
pow[0xa]	16	1			T69	1		T29	1		T226	1
pow[0xb]	36	1			T74	1		T70	1		T46	1
pow[0xc]	63	1			T66	1		T71	3		T67	1
pow[0xd]	153	1			T66	4		T69	1		T71	5
pow[0xe]	285	1			T66	7		T69	2		T71	5
pow[0xf]	617	1			T66	9		T69	6		T71	11