Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg
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Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
97.78 97.78 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_hw_reset_cg_inst 97.78 1 100 1 64 64




Group Instance : adc_ctrl_hw_reset_cg_inst
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.78 1 100 1 64 64




Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 45 1 44 97.78


Variables for Group Instance adc_ctrl_hw_reset_cg_inst
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
fsm_state_cp 17 1 16 94.12 100 1 1 0
lp_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
lp_sample_cnt_pow_cp 8 0 8 100.00 100 1 1 0
np_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
np_sample_cnt_pow_cp 16 0 16 100.00 100 1 1 0


Summary for Variable fsm_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 17 1 16 94.12


Automatically Generated Bins for fsm_state_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[NP_DONE] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[PWRDN] 2214 1 T11 15 T66 16 T69 11
auto[PWRUP] 148 1 T11 1 T66 3 T69 3
auto[ONEST_0] 74 1 T69 2 T71 3 T74 1
auto[ONEST_021] 18 1 T67 1 T49 1 T188 1
auto[ONEST_1] 100 1 T74 1 T68 2 T46 3
auto[ONEST_DONE] 5 1 T29 1 T75 1 T347 1
auto[LP_0] 122 1 T66 1 T69 3 T71 2
auto[LP_021] 37 1 T69 2 T70 1 T73 2
auto[LP_1] 142 1 T66 3 T69 2 T71 6
auto[LP_EVAL] 67 1 T66 1 T67 2 T50 1
auto[LP_SLP] 528 1 T11 1 T66 5 T69 2
auto[LP_PWRUP] 23 1 T70 1 T73 1 T188 1
auto[NP_0] 240 1 T11 1 T66 3 T69 3
auto[NP_021] 57 1 T11 1 T66 1 T67 1
auto[NP_1] 226 1 T11 1 T66 3 T69 1
auto[NP_EVAL] 34 1 T50 1 T223 1 T12 1



Summary for Variable lp_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for lp_sample_cnt_min_max_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
max 10 1 T69 1 T226 1 T269 1
min 1922 1 T11 16 T66 7 T69 5



Summary for Variable lp_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for lp_sample_cnt_pow_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
pow[0x0] 1938 1 T11 16 T66 8 T69 5
pow[0x1] 14 1 T11 1 T69 1 T50 1
pow[0x2] 13 1 T69 1 T68 1 T27 1
pow[0x3] 27 1 T74 1 T188 1 T223 1
pow[0x4] 68 1 T69 1 T71 1 T67 1
pow[0x5] 136 1 T66 2 T69 1 T71 3
pow[0x6] 268 1 T11 1 T66 5 T69 3
pow[0x7] 514 1 T66 7 T69 7 T71 8



Summary for Variable np_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for np_sample_cnt_min_max_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
max 190 1 T66 5 T69 1 T71 4
min 1354 1 T11 14 T66 7 T69 4



Summary for Variable np_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 16 0 16 100.00


User Defined Bins for np_sample_cnt_pow_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
pow[0x0] 1362 1 T11 14 T66 7 T69 4
pow[0x1] 7 1 T11 1 T14 1 T15 2
pow[0x2] 23 1 T248 1 T120 2 T341 1
pow[0x3] 40 1 T27 1 T52 2 T53 1
pow[0x4] 60 1 T11 2 T49 2 T50 2
pow[0x5] 1 1 T123 1 - - - -
pow[0x6] 1 1 T314 1 - - - -
pow[0x7] 2 1 T348 1 T235 1 - -
pow[0x8] 3 1 T314 1 T349 1 T350 1
pow[0x9] 10 1 T73 1 T226 1 T351 1
pow[0xa] 11 1 T66 1 T70 1 T188 1
pow[0xb] 32 1 T67 2 T68 1 T25 1
pow[0xc] 85 1 T69 1 T71 2 T67 1
pow[0xd] 139 1 T66 2 T69 1 T71 1
pow[0xe] 287 1 T66 2 T69 4 T71 4
pow[0xf] 607 1 T11 1 T66 7 T69 9