Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1489	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1519	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1613	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1435	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1697	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1586	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1448	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1729	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1581	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1610	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1719	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1587	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1500	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1545	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1622	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1606	0	0
adc_en_ctl_rd_A	2147483647	1447	0	0
adc_fsm_rst_rd_A	2147483647	1340	0	0
adc_intr_ctl_rd_A	2147483647	1748	0	0
adc_lp_sample_ctl_rd_A	2147483647	1432	0	0
adc_pd_ctl_rd_A	2147483647	1565	0	0
adc_sample_ctl_rd_A	2147483647	1349	0	0
adc_wakeup_ctl_rd_A	2147483647	1463	0	0
intr_enable_rd_A	2147483647	2057	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1489	0	0
T12	190747	5	0	0
T13	102518	20	0	0
T14	0	14	0	0
T15	0	13	0	0
T16	0	36	0	0
T17	0	7	0	0
T18	0	32	0	0
T19	0	20	0	0
T20	0	40	0	0
T21	0	13	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1519	0	0
T12	190747	6	0	0
T13	102518	13	0	0
T14	0	21	0	0
T15	0	17	0	0
T16	0	55	0	0
T17	0	24	0	0
T18	0	27	0	0
T19	0	26	0	0
T20	0	25	0	0
T21	0	16	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1613	0	0
T12	190747	11	0	0
T13	102518	12	0	0
T14	0	7	0	0
T15	0	15	0	0
T16	0	46	0	0
T17	0	21	0	0
T18	0	38	0	0
T19	0	18	0	0
T20	0	35	0	0
T21	0	22	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1435	0	0
T12	190747	7	0	0
T13	102518	15	0	0
T14	0	16	0	0
T15	0	9	0	0
T16	0	36	0	0
T17	0	17	0	0
T18	0	31	0	0
T19	0	13	0	0
T20	0	31	0	0
T21	0	12	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1697	0	0
T12	190747	24	0	0
T13	102518	7	0	0
T14	0	16	0	0
T15	0	19	0	0
T16	0	29	0	0
T17	0	24	0	0
T18	0	31	0	0
T19	0	21	0	0
T20	0	49	0	0
T21	0	20	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1586	0	0
T12	190747	16	0	0
T13	102518	8	0	0
T14	0	33	0	0
T15	0	22	0	0
T16	0	51	0	0
T17	0	27	0	0
T18	0	34	0	0
T19	0	25	0	0
T20	0	43	0	0
T21	0	24	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1448	0	0
T13	102518	17	0	0
T14	0	44	0	0
T15	0	22	0	0
T16	0	25	0	0
T17	0	21	0	0
T18	0	45	0	0
T19	0	17	0	0
T20	0	41	0	0
T21	0	16	0	0
T28	307240	0	0	0
T29	136728	0	0	0
T30	0	14	0	0
T31	492568	0	0	0
T32	822776	0	0	0
T33	105749	0	0	0
T34	11228	0	0	0
T35	480002	0	0	0
T36	847899	0	0	0
T37	23169	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1729	0	0
T12	190747	11	0	0
T13	102518	17	0	0
T14	0	36	0	0
T15	0	21	0	0
T16	0	32	0	0
T17	0	26	0	0
T18	0	27	0	0
T19	0	26	0	0
T20	0	46	0	0
T21	0	25	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1581	0	0
T12	190747	8	0	0
T13	102518	1	0	0
T14	0	9	0	0
T15	0	26	0	0
T16	0	31	0	0
T17	0	21	0	0
T18	0	10	0	0
T19	0	17	0	0
T20	0	32	0	0
T21	0	28	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1610	0	0
T12	190747	9	0	0
T13	102518	7	0	0
T14	0	8	0	0
T15	0	22	0	0
T16	0	19	0	0
T17	0	12	0	0
T18	0	16	0	0
T19	0	19	0	0
T20	0	41	0	0
T21	0	6	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1719	0	0
T12	190747	11	0	0
T13	102518	15	0	0
T14	0	15	0	0
T15	0	23	0	0
T16	0	32	0	0
T17	0	16	0	0
T18	0	32	0	0
T19	0	22	0	0
T20	0	25	0	0
T21	0	21	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1587	0	0
T12	190747	2	0	0
T13	102518	5	0	0
T14	0	32	0	0
T15	0	19	0	0
T16	0	32	0	0
T17	0	12	0	0
T18	0	24	0	0
T19	0	23	0	0
T20	0	29	0	0
T21	0	17	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1500	0	0
T12	190747	2	0	0
T13	102518	3	0	0
T14	0	36	0	0
T15	0	14	0	0
T16	0	42	0	0
T17	0	27	0	0
T18	0	35	0	0
T19	0	21	0	0
T20	0	28	0	0
T21	0	31	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1545	0	0
T12	190747	11	0	0
T13	102518	10	0	0
T14	0	10	0	0
T15	0	18	0	0
T16	0	42	0	0
T17	0	18	0	0
T18	0	29	0	0
T19	0	26	0	0
T20	0	20	0	0
T21	0	20	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1622	0	0
T12	190747	9	0	0
T13	102518	18	0	0
T14	0	31	0	0
T15	0	33	0	0
T16	0	35	0	0
T17	0	15	0	0
T18	0	44	0	0
T19	0	19	0	0
T20	0	36	0	0
T21	0	13	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1606	0	0
T12	190747	14	0	0
T13	102518	5	0	0
T14	0	21	0	0
T15	0	17	0	0
T16	0	32	0	0
T17	0	15	0	0
T18	0	32	0	0
T19	0	24	0	0
T20	0	45	0	0
T21	0	10	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1447	0	0
T12	190747	4	0	0
T13	102518	8	0	0
T14	0	26	0	0
T15	0	8	0	0
T16	0	47	0	0
T17	0	34	0	0
T18	0	26	0	0
T19	0	22	0	0
T20	0	47	0	0
T21	0	17	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1340	0	0
T12	190747	4	0	0
T13	102518	11	0	0
T14	0	16	0	0
T15	0	24	0	0
T16	0	31	0	0
T17	0	12	0	0
T18	0	44	0	0
T19	0	16	0	0
T20	0	43	0	0
T21	0	21	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1748	0	0
T12	190747	2	0	0
T13	102518	8	0	0
T14	0	23	0	0
T15	0	12	0	0
T16	0	40	0	0
T17	0	22	0	0
T18	0	45	0	0
T19	0	13	0	0
T20	0	37	0	0
T21	0	21	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1432	0	0
T12	190747	11	0	0
T13	102518	10	0	0
T14	0	34	0	0
T15	0	21	0	0
T16	0	45	0	0
T17	0	23	0	0
T18	0	30	0	0
T19	0	24	0	0
T20	0	33	0	0
T21	0	12	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565	0	0
T12	190747	6	0	0
T13	102518	11	0	0
T14	0	40	0	0
T15	0	19	0	0
T16	0	49	0	0
T17	0	26	0	0
T18	0	39	0	0
T19	0	17	0	0
T20	0	48	0	0
T21	0	16	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1349	0	0
T12	190747	1	0	0
T13	102518	6	0	0
T14	0	28	0	0
T15	0	37	0	0
T16	0	60	0	0
T17	0	8	0	0
T18	0	26	0	0
T19	0	29	0	0
T20	0	38	0	0
T21	0	22	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1463	0	0
T12	190747	19	0	0
T13	102518	3	0	0
T14	0	18	0	0
T15	0	26	0	0
T16	0	47	0	0
T17	0	23	0	0
T18	0	40	0	0
T19	0	19	0	0
T20	0	34	0	0
T21	0	14	0	0
T22	239802	0	0	0
T23	41469	0	0	0
T24	20112	0	0	0
T25	211844	0	0	0
T26	194386	0	0	0
T27	472209	0	0	0
T28	307240	0	0	0
T29	136728	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2057	0	0
T12	0	29	0	0
T13	0	9	0	0
T14	0	35	0	0
T15	0	18	0	0
T16	0	35	0	0
T17	0	34	0	0
T18	0	75	0	0
T19	0	18	0	0
T38	104177	32	0	0
T39	0	7	0	0
T40	171308	0	0	0
T41	7998	0	0	0
T42	763768	0	0	0
T43	405036	0	0	0
T44	159641	0	0	0
T45	315713	0	0	0
T46	177105	0	0	0
T47	150207	0	0	0
T48	402240	0	0	0