Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1207142	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1180080

1

T1

4281

T2

1385

T3

2727

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2093267	1			T1	8104		T2	2474		T3	4981
values[0x0]	146949	1			T1	254		T2	146		T3	258
values[0x1]	147006	1			T1	245		T2	139		T3	285

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	967063	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1420159

1

T1

5142

T2

1642

T3

3283

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7985	1			T1	19		T2	2		T3	12
valid_sources[0x01]	9299	1			T1	11		T2	42		T3	9
valid_sources[0x02]	7197	1			T1	17		T2	5		T3	6
valid_sources[0x03]	7444	1			T1	11		T2	18		T3	15
valid_sources[0x04]	7691	1			T1	11		T2	5		T3	12
valid_sources[0x05]	7367	1			T1	4		T2	25		T3	6
valid_sources[0x06]	7334	1			T1	17		T2	4		T3	2
valid_sources[0x07]	7375	1			T1	17		T2	9		T3	14
valid_sources[0x08]	8112	1			T1	14		T2	6		T3	14
valid_sources[0x09]	13074	1			T1	7		T2	9		T3	11
valid_sources[0x0a]	7399	1			T1	21		T2	4		T3	11
valid_sources[0x0b]	16209	1			T1	17		T2	11		T3	15
valid_sources[0x0c]	9252	1			T1	23		T2	13		T3	6
valid_sources[0x0d]	14440	1			T1	20		T2	11		T3	2
valid_sources[0x0e]	7203	1			T1	13		T2	16		T3	8
valid_sources[0x0f]	7081	1			T1	19		T2	24		T3	17
valid_sources[0x10]	6969	1			T1	19		T2	19		T3	10
valid_sources[0x11]	12018	1			T1	19		T2	12		T3	16
valid_sources[0x12]	7323	1			T1	4		T2	2		T3	3
valid_sources[0x13]	6773	1			T1	12		T2	9		T3	6
valid_sources[0x14]	8427	1			T1	16		T2	2		T3	17
valid_sources[0x15]	9238	1			T1	12		T2	8		T3	5
valid_sources[0x16]	7570	1			T1	12		T2	30		T3	13
valid_sources[0x17]	7283	1			T1	9		T2	3		T3	4
valid_sources[0x18]	7256	1			T1	21		T2	8		T3	9
valid_sources[0x19]	11589	1			T1	6		T2	2		T3	7
valid_sources[0x1a]	11646	1			T1	14		T2	13		T3	6
valid_sources[0x1b]	6937	1			T1	12		T2	10		T3	3
valid_sources[0x1c]	11327	1			T1	8		T2	3		T3	10
valid_sources[0x1d]	20000	1			T1	25		T2	19		T3	18
valid_sources[0x1e]	11801	1			T1	9		T2	20		T3	4
valid_sources[0x1f]	7321	1			T1	22		T2	22		T3	3
valid_sources[0x20]	8279	1			T1	15		T2	2		T3	13
valid_sources[0x21]	15693	1			T1	6		T2	8		T3	5
valid_sources[0x22]	12118	1			T1	21		T2	16		T3	10
valid_sources[0x23]	8046	1			T1	24		T2	6		T3	23
valid_sources[0x24]	11472	1			T1	20		T2	7		T3	13
valid_sources[0x25]	8783	1			T1	16		T2	40		T3	12
valid_sources[0x26]	7642	1			T1	29		T2	6		T3	12
valid_sources[0x27]	9721	1			T1	8		T2	34		T3	12
valid_sources[0x28]	7032	1			T1	20		T2	16		T3	16
valid_sources[0x29]	8217	1			T1	18		T2	10		T3	10
valid_sources[0x2a]	10111	1			T1	17		T2	17		T3	21
valid_sources[0x2b]	8505	1			T1	12		T2	5		T3	19
valid_sources[0x2c]	7377	1			T1	14		T2	13		T3	6
valid_sources[0x2d]	8423	1			T1	28		T2	12		T3	26
valid_sources[0x2e]	21773	1			T1	29		T2	7		T3	14
valid_sources[0x2f]	7412	1			T1	24		T2	4		T3	31
valid_sources[0x30]	14399	1			T1	11		T2	11		T3	14
valid_sources[0x31]	7370	1			T1	21		T2	16		T3	16
valid_sources[0x32]	11190	1			T1	12		T2	6		T3	17
valid_sources[0x33]	6936	1			T1	8		T2	6		T3	8
valid_sources[0x34]	12816	1			T1	23		T2	20		T3	11
valid_sources[0x35]	7831	1			T1	20		T2	10		T3	8
valid_sources[0x36]	7180	1			T1	14		T2	2		T3	18
valid_sources[0x37]	9035	1			T1	23		T2	23		T3	10
valid_sources[0x38]	12138	1			T1	9		T2	7		T3	16
valid_sources[0x39]	7390	1			T1	11		T2	7		T3	13
valid_sources[0x3a]	7550	1			T1	17		T2	13		T3	14
valid_sources[0x3b]	11668	1			T1	25		T2	9		T3	25
valid_sources[0x3c]	7758	1			T1	15		T2	6		T3	10
valid_sources[0x3d]	7193	1			T1	13		T2	11		T3	9
valid_sources[0x3e]	9121	1			T1	9		T2	3		T3	4
valid_sources[0x3f]	7050	1			T1	13		T2	11		T3	7
valid_sources[0x40]	11907	1			T1	13		T2	4		T3	8
valid_sources[0x41]	20596	1			T1	16		T2	16		T3	5
valid_sources[0x42]	7678	1			T1	15		T2	11		T3	13
valid_sources[0x43]	11200	1			T1	22		T2	6		T3	3
valid_sources[0x44]	16581	1			T1	14		T2	20		T3	9
valid_sources[0x45]	7282	1			T1	18		T2	13		T3	3
valid_sources[0x46]	7845	1			T1	28		T2	9		T3	22
valid_sources[0x47]	7442	1			T1	16		T2	2		T3	4
valid_sources[0x48]	7384	1			T1	14		T2	11		T3	7
valid_sources[0x49]	11501	1			T1	9		T2	11		T3	21
valid_sources[0x4a]	7412	1			T1	21		T2	5		T3	11
valid_sources[0x4b]	7409	1			T1	23		T2	10		T3	5
valid_sources[0x4c]	7164	1			T1	13		T2	11		T3	9
valid_sources[0x4d]	8178	1			T1	20		T2	4		T3	9
valid_sources[0x4e]	7054	1			T1	8		T2	11		T3	8
valid_sources[0x4f]	7032	1			T1	15		T2	2		T3	15
valid_sources[0x50]	11283	1			T1	24		T2	10		T3	11
valid_sources[0x51]	7956	1			T1	7		T2	8		T3	6
valid_sources[0x52]	8770	1			T1	13		T2	8		T3	18
valid_sources[0x53]	10189	1			T1	8		T2	2		T3	11
valid_sources[0x54]	7397	1			T1	19		T2	14		T3	13
valid_sources[0x55]	7032	1			T1	32		T2	3		T3	3
valid_sources[0x56]	13230	1			T1	21		T2	12		T3	21
valid_sources[0x57]	7442	1			T1	13		T2	7		T3	19
valid_sources[0x58]	8457	1			T1	14		T2	7		T3	14
valid_sources[0x59]	9776	1			T1	12		T2	5		T3	5
valid_sources[0x5a]	7634	1			T1	24		T2	2		T3	5
valid_sources[0x5b]	14297	1			T1	27		T2	9		T3	9
valid_sources[0x5c]	8191	1			T1	16		T2	9		T3	6
valid_sources[0x5d]	8623	1			T1	13		T2	26		T3	4
valid_sources[0x5e]	8045	1			T1	19		T2	8		T3	17
valid_sources[0x5f]	11520	1			T1	12		T2	5		T3	4
valid_sources[0x60]	11681	1			T1	22		T2	13		T4	1
valid_sources[0x61]	15744	1			T1	7		T2	16		T3	14
valid_sources[0x62]	7295	1			T1	20		T2	14		T3	19
valid_sources[0x63]	7204	1			T1	19		T2	6		T3	11
valid_sources[0x64]	11210	1			T1	23		T2	8		T3	10
valid_sources[0x65]	11252	1			T1	15		T2	13		T3	9
valid_sources[0x66]	6955	1			T1	5		T2	14		T3	15
valid_sources[0x67]	11408	1			T1	12		T2	7		T3	1
valid_sources[0x68]	7631	1			T1	7		T2	28		T3	23
valid_sources[0x69]	7348	1			T1	20		T2	6		T3	6
valid_sources[0x6a]	7266	1			T1	23		T2	19		T3	10
valid_sources[0x6b]	15706	1			T1	21		T2	13		T3	9
valid_sources[0x6c]	6896	1			T1	18		T2	2		T3	1
valid_sources[0x6d]	7823	1			T1	18		T2	26		T3	14
valid_sources[0x6e]	11912	1			T1	21		T2	26		T3	9
valid_sources[0x6f]	8038	1			T1	12		T2	5		T3	17
valid_sources[0x70]	7347	1			T1	13		T2	8		T3	12
valid_sources[0x71]	7154	1			T1	16		T2	3		T3	6
valid_sources[0x72]	8231	1			T1	25		T2	14		T3	5
valid_sources[0x73]	7555	1			T1	16		T2	6		T3	21
valid_sources[0x74]	7371	1			T1	18		T2	12		T3	19
valid_sources[0x75]	7286	1			T1	8		T2	12		T3	18
valid_sources[0x76]	7493	1			T1	28		T2	6		T3	1
valid_sources[0x77]	7697	1			T1	27		T2	7		T3	17
valid_sources[0x78]	7054	1			T1	25		T2	21		T3	4
valid_sources[0x79]	6924	1			T1	12		T2	4		T3	14
valid_sources[0x7a]	14614	1			T1	14		T2	10		T3	8
valid_sources[0x7b]	11430	1			T1	9		T2	8		T3	16
valid_sources[0x7c]	8277	1			T1	15		T3	11		T4	2
valid_sources[0x7d]	19796	1			T1	13		T2	9		T3	4
valid_sources[0x7e]	16105	1			T1	19		T2	17		T3	7
valid_sources[0x7f]	11632	1			T1	15		T2	1		T3	8
valid_sources[0x80]	14173	1			T1	13		T2	2		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1043448

1

T1

4063

T2

1244

T3

2507

values[0x0]

all_enables

biggest_size

79504

1

T1

133

T2

79

T3

133

values[0x1]

all_enables

biggest_size

57128

1

T1

85

T2

62

T3

87