Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29082	1			T1	20		T2	19		T3	21
auto[PWRUP]	127	1			T47	2		T46	2		T53	2
auto[ONEST_0]	70	1			T47	1		T57	1		T205	4
auto[ONEST_021]	20	1			T71	1		T205	1		T206	1
auto[ONEST_1]	87	1			T14	2		T57	1		T74	1
auto[ONEST_DONE]	7	1			T207	1		T208	1		T209	1
auto[LP_0]	115	1			T14	4		T47	3		T57	2
auto[LP_021]	21	1			T47	1		T46	1		T53	1
auto[LP_1]	118	1			T14	1		T47	2		T46	2
auto[LP_EVAL]	71	1			T14	1		T46	2		T39	1
auto[LP_SLP]	514	1			T14	7		T47	8		T46	4
auto[LP_PWRUP]	17	1			T210	2		T211	1		T212	1
auto[NP_0]	147	1			T14	2		T46	1		T53	2
auto[NP_021]	30	1			T47	2		T39	1		T213	1
auto[NP_1]	151	1			T14	3		T47	2		T46	4
auto[NP_EVAL]	37	1			T47	1		T46	1		T57	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

13

1

T47

1

T57

1

T210

1

min

28476

1

T1

20

T2

19

T3

21

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28483	1			T1	20		T2	19		T3	21
pow[0x1]	13	1			T47	1		T205	2		T214	1
pow[0x2]	15	1			T47	1		T53	1		T205	1
pow[0x3]	32	1			T14	1		T53	1		T74	1
pow[0x4]	60	1			T14	1		T46	1		T57	2
pow[0x5]	139	1			T14	3		T47	2		T46	2
pow[0x6]	277	1			T14	2		T46	3		T53	6
pow[0x7]	534	1			T14	10		T47	12		T46	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

185

1

T14

7

T47

1

T46

1

min

28003

1

T1

20

T2

19

T3

21

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28003	1			T1	20		T2	19		T3	21
pow[0x4]	1	1			T207	1		-	-		-	-
pow[0x5]	1	1			T204	1		-	-		-	-
pow[0x6]	1	1			T215	1		-	-		-	-
pow[0x7]	5	1			T205	1		T216	1		T209	1
pow[0x8]	5	1			T74	1		T217	1		T216	1
pow[0x9]	9	1			T14	1		T218	1		T219	1
pow[0xa]	24	1			T47	1		T57	1		T74	1
pow[0xb]	37	1			T16	1		T205	1		T220	1
pow[0xc]	77	1			T14	1		T47	1		T57	1
pow[0xd]	147	1			T14	1		T47	3		T46	1
pow[0xe]	289	1			T14	4		T47	3		T46	3
pow[0xf]	621	1			T14	12		T47	6		T46	2