Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2385	1			T5	4		T9	2		T12	2
auto[PWRUP]	134	1			T14	2		T47	2		T46	2
auto[ONEST_0]	75	1			T14	3		T47	1		T46	3
auto[ONEST_021]	23	1			T53	2		T57	1		T74	1
auto[ONEST_1]	84	1			T14	2		T47	1		T46	2
auto[ONEST_DONE]	3	1			T290	1		T345	1		T346	1
auto[LP_0]	131	1			T14	1		T47	2		T46	2
auto[LP_021]	40	1			T47	1		T46	1		T57	2
auto[LP_1]	140	1			T47	4		T53	2		T57	3
auto[LP_EVAL]	67	1			T14	2		T46	2		T53	1
auto[LP_SLP]	557	1			T14	7		T47	6		T46	14
auto[LP_PWRUP]	30	1			T46	1		T53	1		T57	1
auto[NP_0]	237	1			T14	3		T47	3		T46	1
auto[NP_021]	56	1			T14	1		T47	1		T53	2
auto[NP_1]	246	1			T14	5		T47	4		T46	3
auto[NP_EVAL]	26	1			T47	1		T46	2		T39	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T57

1

T290

1

T347

1

min

1984

1

T5

4

T9

2

T12

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1998	1			T5	4		T9	2		T12	2
pow[0x1]	13	1			T58	1		T205	1		T148	1
pow[0x2]	22	1			T47	1		T53	2		T39	1
pow[0x3]	34	1			T14	1		T47	2		T46	1
pow[0x4]	81	1			T47	3		T46	2		T53	1
pow[0x5]	150	1			T14	2		T47	2		T46	1
pow[0x6]	279	1			T14	3		T46	4		T53	6
pow[0x7]	608	1			T14	13		T47	11		T46	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

205

1

T14

9

T47

5

T46

2

min

1375

1

T5

4

T9

2

T12

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1377	1			T5	4		T9	2		T12	2
pow[0x1]	22	1			T58	1		T17	1		T70	1
pow[0x2]	31	1			T46	1		T45	1		T27	3
pow[0x3]	28	1			T17	1		T68	1		T69	3
pow[0x4]	47	1			T46	1		T45	1		T58	1
pow[0x5]	1	1			T288	1		-	-		-	-
pow[0x6]	2	1			T53	1		T347	1		-	-
pow[0x7]	1	1			T348	1		-	-		-	-
pow[0x8]	8	1			T14	1		T53	1		T349	1
pow[0x9]	17	1			T47	1		T46	1		T57	1
pow[0xa]	28	1			T39	1		T350	1		T351	1
pow[0xb]	41	1			T14	1		T46	1		T53	2
pow[0xc]	87	1			T47	3		T46	2		T68	1
pow[0xd]	160	1			T14	3		T47	3		T46	2
pow[0xe]	309	1			T14	3		T47	4		T46	8
pow[0xf]	637	1			T14	6		T47	7		T46	9