Module Definition
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Module : prim_pulse_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req 60.00 100.00 40.00 100.00 0.00
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req 60.00 100.00 40.00 100.00 0.00
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req 93.75 100.00 75.00 100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 100.00 40.00 100.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 100.00 40.00 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.29 94.12 85.71 83.33 50.00 u_adc_chn_val_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 100.00 40.00 100.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 100.00 40.00 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.29 94.12 85.71 83.33 50.00 u_adc_chn_val_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_adc_fsm_state_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_en_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_pd_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_lp_sample_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_sample_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 100.00 92.31 100.00 100.00 u_adc_fsm_rst_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn0_filter_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn0_filter_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn0_filter_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn0_filter_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn0_filter_ctl_4_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn0_filter_ctl_5_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn0_filter_ctl_6_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn0_filter_ctl_7_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn1_filter_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn1_filter_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn1_filter_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn1_filter_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn1_filter_ctl_4_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn1_filter_ctl_5_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn1_filter_ctl_6_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn1_filter_ctl_7_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_wakeup_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_filter_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_adc_ctrl_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 348993 0 0
SrcPulseCheck_M 2147483647 351252 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 348993 0 0
T1 12430098 84 0 0
T2 8320860 126 0 0
T3 16402806 126 0 0
T4 11210249 102 0 0
T5 12072205 236 0 0
T6 13644279 50 0 0
T7 10674775 102 0 0
T8 1407365 52 0 0
T9 8348644 92 0 0
T10 11160590 46 0 0
T11 941655 72 0 0
T12 170284 43 0 0
T13 123769 72 0 0
T14 0 604 0 0
T15 0 28 0 0
T16 19750 1 0 0
T26 83 0 0 0
T27 49987 1 0 0
T28 33293 0 0 0
T29 36762 0 0 0
T30 932 0 0 0
T31 98300 0 0 0
T32 42131 0 0 0
T47 0 509 0 0
T48 0 56 0 0
T125 0 20 0 0
T147 0 5 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 351252 0 0
T1 12430098 84 0 0
T2 8320860 126 0 0
T3 16402806 126 0 0
T4 10622526 102 0 0
T5 11532389 236 0 0
T6 12937261 50 0 0
T7 10115192 102 0 0
T8 1334483 52 0 0
T9 7972870 92 0 0
T10 10582645 46 0 0
T11 65365 72 0 0
T12 35475 43 0 0
T13 95206 72 0 0
T14 0 604 0 0
T15 0 28 0 0
T45 0 5 0 0
T46 556741 8 0 0
T47 0 509 0 0
T48 0 56 0 0
T49 156448 0 0 0
T50 241363 0 0 0
T51 342508 0 0 0
T52 143047 0 0 0
T53 843972 0 0 0
T54 521368 0 0 0
T55 538370 0 0 0
T125 0 20 0 0
T147 0 5 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions5240.00
Logical5240.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01Unreachable
10Excluded VC_COV_UNR
11Unreachable

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 0 0 0
SrcPulseCheck_M 2147483647 0 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions5240.00
Logical5240.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01Unreachable
10Excluded VC_COV_UNR
11Unreachable

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 0 0 0
SrcPulseCheck_M 2147483647 0 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions8675.00
Logical8675.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT46,T45,T16
10CoveredT46,T45,T16
11Not Covered

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT45,T16,T27
10Not Covered
11CoveredT45,T16,T27

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 82 0 0
SrcPulseCheck_M 2147483647 351 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 82 0 0
T16 19750 1 0 0
T17 0 1 0 0
T18 0 1 0 0
T19 0 1 0 0
T26 83 0 0 0
T27 49987 1 0 0
T28 33293 0 0 0
T29 36762 0 0 0
T30 932 0 0 0
T31 98300 0 0 0
T32 42131 0 0 0
T33 86563 0 0 0
T34 5766 0 0 0
T58 0 1 0 0
T68 0 1 0 0
T69 0 1 0 0
T70 0 1 0 0
T148 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 351 0 0
T16 0 5 0 0
T17 0 5 0 0
T18 0 9 0 0
T27 0 5 0 0
T45 0 5 0 0
T46 556741 8 0 0
T49 156448 0 0 0
T50 241363 0 0 0
T51 342508 0 0 0
T52 143047 0 0 0
T53 843972 0 0 0
T54 521368 0 0 0
T55 538370 0 0 0
T56 77197 0 0 0
T57 138692 0 0 0
T58 0 9 0 0
T68 0 10 0 0
T69 0 5 0 0
T70 0 10 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 38795 0 0
SrcPulseCheck_M 2147483647 38921 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 38795 0 0
T1 76727 6 0 0
T2 132076 9 0 0
T3 98682 9 0 0
T4 1176 41 0 0
T5 49073 96 0 0
T6 5701 25 0 0
T7 1154 41 0 0
T8 611 23 0 0
T9 32674 26 0 0
T10 4855 23 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 38921 0 0
T1 613834 6 0 0
T2 330194 9 0 0
T3 812585 9 0 0
T4 588899 41 0 0
T5 588889 96 0 0
T6 712719 25 0 0
T7 560737 41 0 0
T8 73493 23 0 0
T9 408448 26 0 0
T10 582800 23 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 38871 0 0
SrcPulseCheck_M 35368209 38891 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 38871 0 0
T1 613834 6 0 0
T2 330194 9 0 0
T3 812585 9 0 0
T4 588899 41 0 0
T5 588889 96 0 0
T6 712719 25 0 0
T7 560737 41 0 0
T8 73493 23 0 0
T9 408448 26 0 0
T10 582800 23 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 38891 0 0
T1 76727 6 0 0
T2 132076 9 0 0
T3 98682 9 0 0
T4 1176 41 0 0
T5 49073 96 0 0
T6 5701 25 0 0
T7 1154 41 0 0
T8 611 23 0 0
T9 32674 26 0 0
T10 4855 23 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 18258 0 0
SrcPulseCheck_M 2147483647 18337 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 18258 0 0
T1 76727 4 0 0
T2 132076 6 0 0
T3 98682 6 0 0
T4 1176 1 0 0
T5 49073 47 0 0
T6 5701 12 0 0
T7 1154 1 0 0
T8 611 11 0 0
T9 32674 13 0 0
T10 4855 11 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 18337 0 0
T1 613834 4 0 0
T2 330194 6 0 0
T3 812585 6 0 0
T4 588899 1 0 0
T5 588889 47 0 0
T6 712719 12 0 0
T7 560737 1 0 0
T8 73493 11 0 0
T9 408448 13 0 0
T10 582800 11 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 18327 0 0
SrcPulseCheck_M 35368209 18327 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 18327 0 0
T1 613834 4 0 0
T2 330194 6 0 0
T3 812585 6 0 0
T4 588899 1 0 0
T5 588889 47 0 0
T6 712719 12 0 0
T7 560737 1 0 0
T8 73493 11 0 0
T9 408448 13 0 0
T10 582800 11 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 18327 0 0
T1 76727 4 0 0
T2 132076 6 0 0
T3 98682 6 0 0
T4 1176 1 0 0
T5 49073 47 0 0
T6 5701 12 0 0
T7 1154 1 0 0
T8 611 11 0 0
T9 32674 13 0 0
T10 4855 11 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 14481 0 0
SrcPulseCheck_M 2147483647 14609 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 14481 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 188 0 0
T47 0 165 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 14609 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 188 0 0
T47 0 165 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 14568 0 0
SrcPulseCheck_M 35368209 14568 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 14568 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 188 0 0
T47 0 165 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 14568 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 188 0 0
T47 0 165 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 14512 0 0
SrcPulseCheck_M 2147483647 14643 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 14512 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 188 0 0
T47 0 165 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 14643 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 188 0 0
T47 0 165 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 14603 0 0
SrcPulseCheck_M 35368209 14603 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 14603 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 188 0 0
T47 0 165 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 14603 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 188 0 0
T47 0 165 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 20400 0 0
SrcPulseCheck_M 2147483647 20480 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 20400 0 0
T1 76727 4 0 0
T2 132076 6 0 0
T3 98682 6 0 0
T4 1176 0 0 0
T5 49073 2 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 2 0 0
T10 4855 0 0 0
T11 0 4 0 0
T12 0 2 0 0
T13 0 4 0 0
T14 0 271 0 0
T47 0 233 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 20480 0 0
T1 613834 4 0 0
T2 330194 6 0 0
T3 812585 6 0 0
T4 588899 0 0 0
T5 588889 2 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 2 0 0
T10 582800 0 0 0
T11 0 4 0 0
T12 0 2 0 0
T13 0 4 0 0
T14 0 271 0 0
T47 0 233 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 20471 0 0
SrcPulseCheck_M 35368209 20471 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 20471 0 0
T1 613834 4 0 0
T2 330194 6 0 0
T3 812585 6 0 0
T4 588899 0 0 0
T5 588889 2 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 2 0 0
T10 582800 0 0 0
T11 0 4 0 0
T12 0 2 0 0
T13 0 4 0 0
T14 0 271 0 0
T47 0 233 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 20471 0 0
T1 76727 4 0 0
T2 132076 6 0 0
T3 98682 6 0 0
T4 1176 0 0 0
T5 49073 2 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 2 0 0
T10 4855 0 0 0
T11 0 4 0 0
T12 0 2 0 0
T13 0 4 0 0
T14 0 271 0 0
T47 0 233 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1854 0 0
SrcPulseCheck_M 2147483647 1935 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1854 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 1 0 0
T47 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1935 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 1 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1927 0 0
SrcPulseCheck_M 35368209 1927 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1927 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 1 0 0
T47 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1927 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 1 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1774 0 0
SrcPulseCheck_M 2147483647 1851 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1774 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1851 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1843 0 0
SrcPulseCheck_M 35368209 1843 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1843 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1843 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1755 0 0
SrcPulseCheck_M 2147483647 1834 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1755 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1834 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1826 0 0
SrcPulseCheck_M 35368209 1826 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1826 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1826 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1788 0 0
SrcPulseCheck_M 2147483647 1868 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1788 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1868 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1860 0 0
SrcPulseCheck_M 35368209 1860 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1860 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1860 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1765 0 0
SrcPulseCheck_M 2147483647 1847 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1765 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1847 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1838 0 0
SrcPulseCheck_M 35368209 1838 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1838 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1838 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1744 0 0
SrcPulseCheck_M 2147483647 1823 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1744 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1823 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1814 0 0
SrcPulseCheck_M 35368209 1814 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1814 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1814 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1776 0 0
SrcPulseCheck_M 2147483647 1856 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1776 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1856 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1848 0 0
SrcPulseCheck_M 35368209 1848 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1848 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1848 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1762 0 0
SrcPulseCheck_M 2147483647 1840 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1762 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1840 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1833 0 0
SrcPulseCheck_M 35368209 1833 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1833 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1833 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1878 0 0
SrcPulseCheck_M 2147483647 1957 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1878 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 1 0 0
T47 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1957 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 1 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1948 0 0
SrcPulseCheck_M 35368209 1948 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1948 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 1 0 0
T47 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1948 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T14 0 1 0 0
T47 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1761 0 0
SrcPulseCheck_M 2147483647 1840 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1761 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1840 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1831 0 0
SrcPulseCheck_M 35368209 1831 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1831 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1831 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1756 0 0
SrcPulseCheck_M 2147483647 1835 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1756 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1835 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1826 0 0
SrcPulseCheck_M 35368209 1826 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1826 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1826 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1738 0 0
SrcPulseCheck_M 2147483647 1812 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1738 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1812 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1802 0 0
SrcPulseCheck_M 35368209 1802 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1802 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1802 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1758 0 0
SrcPulseCheck_M 2147483647 1839 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1758 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1839 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1830 0 0
SrcPulseCheck_M 35368209 1830 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1830 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1830 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1752 0 0
SrcPulseCheck_M 2147483647 1833 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1752 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1833 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1826 0 0
SrcPulseCheck_M 35368209 1826 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1826 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1826 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1730 0 0
SrcPulseCheck_M 2147483647 1807 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1730 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1807 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1798 0 0
SrcPulseCheck_M 35368209 1798 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1798 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1798 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1760 0 0
SrcPulseCheck_M 2147483647 1841 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1760 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1841 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1831 0 0
SrcPulseCheck_M 35368209 1831 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1831 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 1 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1831 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 1 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T15 0 1 0 0
T48 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 1258 0 0
SrcPulseCheck_M 2147483647 1332 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1258 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 0 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T46 0 3 0 0
T51 0 3 0 0
T54 0 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1332 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 0 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T46 0 3 0 0
T51 0 3 0 0
T54 0 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 1325 0 0
SrcPulseCheck_M 35368209 1325 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1325 0 0
T1 613834 2 0 0
T2 330194 3 0 0
T3 812585 3 0 0
T4 588899 0 0 0
T5 588889 1 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 0 0 0
T10 582800 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T46 0 3 0 0
T51 0 3 0 0
T54 0 3 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 1325 0 0
T1 76727 2 0 0
T2 132076 3 0 0
T3 98682 3 0 0
T4 1176 0 0 0
T5 49073 1 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 0 0 0
T10 4855 0 0 0
T11 0 2 0 0
T12 0 1 0 0
T13 0 2 0 0
T46 0 3 0 0
T51 0 3 0 0
T54 0 3 0 0

Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 35368209 68673 0 0
SrcPulseCheck_M 2147483647 68755 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35368209 68673 0 0
T1 76727 147 0 0
T2 132076 204 0 0
T3 98682 152 0 0
T4 1176 0 0 0
T5 49073 67 0 0
T6 5701 0 0 0
T7 1154 0 0 0
T8 611 0 0 0
T9 32674 76 0 0
T10 4855 0 0 0
T11 0 143 0 0
T12 0 82 0 0
T13 0 145 0 0
T15 0 61 0 0
T48 0 152 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 68755 0 0
T1 613834 147 0 0
T2 330194 204 0 0
T3 812585 152 0 0
T4 588899 0 0 0
T5 588889 67 0 0
T6 712719 0 0 0
T7 560737 0 0 0
T8 73493 0 0 0
T9 408448 76 0 0
T10 582800 0 0 0
T11 0 143 0 0
T12 0 82 0 0
T13 0 145 0 0
T15 0 61 0 0
T48 0 152 0 0

Line Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T7
10CoveredT4,T5,T7
11CoveredT4,T5,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T7
10CoveredT4,T5,T7
11CoveredT4,T5,T7

Branch Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 6537 0 0
SrcPulseCheck_M 35295714 6540 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6537 0 0
T4 588899 20 0 0
T5 588889 8 0 0
T6 712719 0 0 0
T7 560737 20 0 0
T8 73493 6 0 0
T9 408448 4 0 0
T10 582800 0 0 0
T11 941655 0 0 0
T12 170284 7 0 0
T13 123769 0 0 0
T14 0 58 0 0
T47 0 39 0 0
T125 0 20 0 0
T147 0 5 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 35295714 6540 0 0
T4 1176 20 0 0
T5 49073 8 0 0
T6 5701 0 0 0
T7 1154 20 0 0
T8 611 6 0 0
T9 32674 4 0 0
T10 4855 0 0 0
T11 65365 0 0 0
T12 35475 7 0 0
T13 95206 0 0 0
T14 0 58 0 0
T47 0 39 0 0
T125 0 20 0 0
T147 0 5 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%