Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2095	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2082	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2118	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2395	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2140	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2259	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1901	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2130	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2093	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2242	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2124	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2013	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2091	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2092	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2013	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2034	0	0
adc_en_ctl_rd_A	2147483647	1666	0	0
adc_fsm_rst_rd_A	2147483647	1473	0	0
adc_intr_ctl_rd_A	2147483647	2233	0	0
adc_lp_sample_ctl_rd_A	2147483647	1439	0	0
adc_pd_ctl_rd_A	2147483647	1817	0	0
adc_sample_ctl_rd_A	2147483647	1591	0	0
adc_wakeup_ctl_rd_A	2147483647	1849	0	0
intr_enable_rd_A	2147483647	2087	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2095	0	0
T16	572814	26	0	0
T17	0	8	0	0
T18	0	37	0	0
T19	0	21	0	0
T20	0	16	0	0
T21	0	34	0	0
T22	0	5	0	0
T23	0	32	0	0
T24	0	7	0	0
T25	0	15	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2082	0	0
T16	572814	17	0	0
T17	0	11	0	0
T18	0	27	0	0
T19	0	17	0	0
T20	0	29	0	0
T21	0	35	0	0
T22	0	22	0	0
T23	0	19	0	0
T24	0	21	0	0
T25	0	13	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2118	0	0
T16	572814	26	0	0
T17	0	15	0	0
T18	0	20	0	0
T19	0	16	0	0
T20	0	15	0	0
T21	0	22	0	0
T22	0	23	0	0
T23	0	42	0	0
T24	0	22	0	0
T25	0	5	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2395	0	0
T16	572814	28	0	0
T17	0	20	0	0
T18	0	17	0	0
T19	0	20	0	0
T20	0	23	0	0
T21	0	29	0	0
T22	0	14	0	0
T23	0	50	0	0
T24	0	7	0	0
T25	0	19	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2140	0	0
T16	572814	11	0	0
T17	0	15	0	0
T18	0	37	0	0
T19	0	19	0	0
T20	0	16	0	0
T21	0	29	0	0
T22	0	9	0	0
T23	0	40	0	0
T24	0	11	0	0
T25	0	21	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2259	0	0
T16	572814	21	0	0
T17	0	23	0	0
T18	0	25	0	0
T19	0	16	0	0
T20	0	13	0	0
T21	0	39	0	0
T22	0	12	0	0
T23	0	45	0	0
T24	0	7	0	0
T25	0	16	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1901	0	0
T16	572814	20	0	0
T17	0	19	0	0
T18	0	26	0	0
T19	0	15	0	0
T20	0	12	0	0
T21	0	39	0	0
T22	0	9	0	0
T23	0	49	0	0
T24	0	18	0	0
T25	0	12	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2130	0	0
T16	572814	16	0	0
T17	0	10	0	0
T18	0	29	0	0
T19	0	31	0	0
T20	0	22	0	0
T21	0	22	0	0
T22	0	7	0	0
T23	0	31	0	0
T24	0	1	0	0
T25	0	19	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2093	0	0
T16	572814	5	0	0
T17	0	13	0	0
T18	0	15	0	0
T19	0	20	0	0
T20	0	20	0	0
T21	0	32	0	0
T22	0	17	0	0
T23	0	30	0	0
T24	0	12	0	0
T25	0	15	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2242	0	0
T16	572814	23	0	0
T17	0	20	0	0
T18	0	38	0	0
T19	0	26	0	0
T20	0	18	0	0
T21	0	20	0	0
T22	0	12	0	0
T23	0	44	0	0
T24	0	10	0	0
T25	0	15	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2124	0	0
T16	572814	17	0	0
T17	0	15	0	0
T18	0	20	0	0
T19	0	22	0	0
T20	0	24	0	0
T21	0	18	0	0
T22	0	8	0	0
T23	0	46	0	0
T24	0	11	0	0
T25	0	9	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2013	0	0
T16	572814	17	0	0
T17	0	14	0	0
T18	0	19	0	0
T19	0	18	0	0
T20	0	25	0	0
T21	0	36	0	0
T22	0	17	0	0
T23	0	40	0	0
T24	0	17	0	0
T25	0	18	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2091	0	0
T16	572814	14	0	0
T17	0	18	0	0
T18	0	27	0	0
T19	0	22	0	0
T20	0	32	0	0
T21	0	19	0	0
T22	0	7	0	0
T23	0	24	0	0
T24	0	13	0	0
T25	0	25	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2092	0	0
T16	572814	19	0	0
T17	0	17	0	0
T18	0	41	0	0
T19	0	25	0	0
T20	0	15	0	0
T21	0	32	0	0
T22	0	19	0	0
T23	0	49	0	0
T24	0	20	0	0
T25	0	16	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2013	0	0
T16	572814	5	0	0
T17	0	8	0	0
T18	0	37	0	0
T19	0	13	0	0
T20	0	19	0	0
T21	0	25	0	0
T22	0	15	0	0
T23	0	29	0	0
T24	0	14	0	0
T25	0	18	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2034	0	0
T16	572814	20	0	0
T17	0	29	0	0
T18	0	25	0	0
T19	0	27	0	0
T20	0	20	0	0
T21	0	34	0	0
T22	0	10	0	0
T23	0	28	0	0
T24	0	11	0	0
T25	0	18	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1666	0	0
T16	572814	15	0	0
T17	0	11	0	0
T18	0	16	0	0
T19	0	24	0	0
T20	0	21	0	0
T21	0	27	0	0
T22	0	20	0	0
T23	0	43	0	0
T24	0	13	0	0
T25	0	21	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1473	0	0
T16	572814	19	0	0
T17	0	11	0	0
T18	0	18	0	0
T19	0	32	0	0
T20	0	20	0	0
T21	0	46	0	0
T22	0	8	0	0
T23	0	55	0	0
T24	0	5	0	0
T25	0	12	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2233	0	0
T16	572814	22	0	0
T17	0	27	0	0
T18	0	33	0	0
T19	0	13	0	0
T20	0	20	0	0
T21	0	32	0	0
T22	0	10	0	0
T23	0	27	0	0
T24	0	8	0	0
T25	0	27	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1439	0	0
T16	572814	11	0	0
T17	0	15	0	0
T18	0	44	0	0
T19	0	23	0	0
T20	0	3	0	0
T21	0	28	0	0
T22	0	16	0	0
T23	0	26	0	0
T24	0	10	0	0
T25	0	15	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1817	0	0
T16	572814	17	0	0
T17	0	16	0	0
T18	0	32	0	0
T19	0	15	0	0
T20	0	14	0	0
T21	0	24	0	0
T22	0	12	0	0
T23	0	44	0	0
T24	0	13	0	0
T25	0	14	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1591	0	0
T16	572814	13	0	0
T17	0	8	0	0
T18	0	45	0	0
T19	0	14	0	0
T20	0	15	0	0
T21	0	44	0	0
T22	0	8	0	0
T23	0	41	0	0
T24	0	12	0	0
T25	0	15	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1849	0	0
T16	572814	17	0	0
T17	0	19	0	0
T18	0	27	0	0
T19	0	18	0	0
T20	0	18	0	0
T21	0	35	0	0
T22	0	6	0	0
T23	0	53	0	0
T24	0	12	0	0
T25	0	15	0	0
T26	20653	0	0	0
T27	296083	0	0	0
T28	832383	0	0	0
T29	181979	0	0	0
T30	452575	0	0	0
T31	176942	0	0	0
T32	103225	0	0	0
T33	168799	0	0	0
T34	141308	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2087	0	0
T16	0	15	0	0
T17	0	7	0	0
T18	0	59	0	0
T19	0	19	0	0
T20	0	19	0	0
T21	0	123	0	0
T22	0	19	0	0
T23	0	25	0	0
T35	161763	13	0	0
T36	0	5	0	0
T37	385224	0	0	0
T38	423266	0	0	0
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