Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7044	1			T1	33		T3	7		T4	20
testmodes[AdcCtrlTestmodeNormal]	5314	1			T1	30		T3	9		T8	11
testmodes[AdcCtrlTestmodeLowpower]	5494	1			T1	37		T2	3		T5	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3924	1			T1	12		T3	3		T4	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1720	1			T1	6		T3	4		T8	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1302	1			T1	15		T10	17		T53	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1665	1			T1	6		T3	4		T8	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1982	1			T1	13		T3	4		T8	7
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1320	1			T1	11		T10	8		T53	22
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1334	1			T1	15		T10	16		T53	20
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1282	1			T1	10		T10	9		T53	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2626	1			T1	11		T2	2		T5	1