---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.adc_ctrl_csr_assert.TlulOOBAddrErr_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.BusySrcReqChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcAckBusyChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.BusySrcReqChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcAckBusyChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	35229414	0	0	916

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AdcKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.AlertsKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	2147483647	90	0	0
tb.dut.IntrKnown	0	0	2147483647	2147483647	0	0
tb.dut.TlOAReadyKnown	0	0	2147483647	2147483647	0	0
tb.dut.TlODValidKnown	0	0	2147483647	2147483647	0	0
tb.dut.WakeKnown	0	0	2147483647	2147483647	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_0_rd_A	0	0	2147483647	1870	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_1_rd_A	0	0	2147483647	1907	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_2_rd_A	0	0	2147483647	1809	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_3_rd_A	0	0	2147483647	1782	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_4_rd_A	0	0	2147483647	1918	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_5_rd_A	0	0	2147483647	1768	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_6_rd_A	0	0	2147483647	1912	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_7_rd_A	0	0	2147483647	1738	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_0_rd_A	0	0	2147483647	1777	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_1_rd_A	0	0	2147483647	1835	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_2_rd_A	0	0	2147483647	1725	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_3_rd_A	0	0	2147483647	1810	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_4_rd_A	0	0	2147483647	1743	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_5_rd_A	0	0	2147483647	1733	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_6_rd_A	0	0	2147483647	1990	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_7_rd_A	0	0	2147483647	1602	0	0
tb.dut.adc_ctrl_csr_assert.adc_en_ctl_rd_A	0	0	2147483647	1502	0	0
tb.dut.adc_ctrl_csr_assert.adc_fsm_rst_rd_A	0	0	2147483647	1324	0	0
tb.dut.adc_ctrl_csr_assert.adc_intr_ctl_rd_A	0	0	2147483647	1588	0	0
tb.dut.adc_ctrl_csr_assert.adc_lp_sample_ctl_rd_A	0	0	2147483647	1373	0	0
tb.dut.adc_ctrl_csr_assert.adc_pd_ctl_rd_A	0	0	2147483647	1823	0	0
tb.dut.adc_ctrl_csr_assert.adc_sample_ctl_rd_A	0	0	2147483647	1412	0	0
tb.dut.adc_ctrl_csr_assert.adc_wakeup_ctl_rd_A	0	0	2147483647	1428	0	0
tb.dut.adc_ctrl_csr_assert.intr_enable_rd_A	0	0	2147483647	2318	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	2147483647	25149690	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	2147483647	4771652	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	917	917	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	2147483647	15837273	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	2147483647	3321	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	2147483647	15724797	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	2147483647	3859603	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	2147483647	3115	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	2147483647	25149764	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	2147483647	4771721	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	2147483647	25149764	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	2147483647	4771721	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	2147483647	4771721	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	2147483647	4771721	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	2147483647	2969	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	2147483647	3203	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	917	917	0	0
tb.dut.u_adc_ctrl_core.MaxFilters_A	0	0	35158441	34854432	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck00_A	0	0	35158441	10258401	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck01_A	0	0	35158441	2528619	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck10_A	0	0	35158441	2797243	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck11_A	0	0	35158441	19270169	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck00_A	0	0	35158441	10910928	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck01_A	0	0	35158441	1264736	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck10_A	0	0	35158441	1565965	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck11_A	0	0	35158441	21112803	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck00_A	0	0	35158441	12641254	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck01_A	0	0	35158441	655739	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck10_A	0	0	35158441	412905	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck11_A	0	0	35158441	21144534	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck00_A	0	0	35158441	12619656	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck01_A	0	0	35158441	256228	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck10_A	0	0	35158441	360725	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck11_A	0	0	35158441	21617823	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck00_A	0	0	35158441	12489486	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck01_A	0	0	35158441	32983	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck10_A	0	0	35158441	89	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck11_A	0	0	35158441	22331874	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck00_A	0	0	35158441	13544066	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck01_A	0	0	35158441	122920	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck10_A	0	0	35158441	32795	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck11_A	0	0	35158441	21154651	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck00_A	0	0	35158441	13407186	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck01_A	0	0	35158441	66370	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck10_A	0	0	35158441	185772	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck11_A	0	0	35158441	21195104	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck00_A	0	0	35158441	13597548	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck01_A	0	0	35158441	201795	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck10_A	0	0	35158441	263091	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck11_A	0	0	35158441	20791998	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M	0	0	32702326	32621718	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrMisMatch_A	0	0	32702326	169158	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A	0	0	32702326	94908	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpSampleCntCfg_M	0	0	32702326	32621718	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmDebugOut_A	0	0	32702326	32621718	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateHwReset_A	0	0	1160	1160	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateSwReset_A	0	0	32702326	6685	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntHwReset_A	0	0	1160	1160	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntSwReset_A	0	0	32702326	6685	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntHwReset_A	0	0	1160	1160	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntSwReset_A	0	0	32702326	6685	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntHwReset_A	0	0	1160	1160	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntSwReset_A	0	0	32702326	6685	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntHwReset_A	0	0	1160	1160	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntSwReset_A	0	0	32702326	6685	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o.IntrTKind_A	0	0	752	752	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckAckNeedsReq	0	0	2147483647	17748	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckHoldReq	0	0	35158441	17748	0	0
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.DstPulseCheck_A	0	0	2147483647	6600	0	0
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.SrcPulseCheck_M	0	0	35158441	6601	0	0
tb.dut.u_reg.en2addrHit	0	0	2147483647	2370685	0	0
tb.dut.u_reg.reAfterRv	0	0	2147483647	2370684	0	0
tb.dut.u_reg.rePulse	0	0	2147483647	2087272	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.BusySrcReqChk_A	0	0	2147483647	1890915	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcAckBusyChk_A	0	0	2147483647	1964	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1964	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1964	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1852	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1974	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.BusySrcReqChk_A	0	0	2147483647	1836730	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcAckBusyChk_A	0	0	2147483647	1902	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1902	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1902	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1788	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1911	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.BusySrcReqChk_A	0	0	2147483647	1771334	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcAckBusyChk_A	0	0	2147483647	1832	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1832	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1832	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1718	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1841	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.BusySrcReqChk_A	0	0	2147483647	1795912	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcAckBusyChk_A	0	0	2147483647	1875	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1875	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1875	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1765	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1885	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.BusySrcReqChk_A	0	0	2147483647	1754511	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcAckBusyChk_A	0	0	2147483647	1833	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1833	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1833	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1719	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1841	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.BusySrcReqChk_A	0	0	2147483647	1763143	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcAckBusyChk_A	0	0	2147483647	1852	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1852	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1852	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1741	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1862	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.BusySrcReqChk_A	0	0	2147483647	1709790	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcAckBusyChk_A	0	0	2147483647	1826	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1826	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1826	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1717	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1835	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.BusySrcReqChk_A	0	0	2147483647	1734622	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcAckBusyChk_A	0	0	2147483647	1842	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1842	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1842	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1727	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1850	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.BusySrcReqChk_A	0	0	2147483647	1824666	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcAckBusyChk_A	0	0	2147483647	1949	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1949	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1949	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1839	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1959	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.BusySrcReqChk_A	0	0	2147483647	1711967	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcAckBusyChk_A	0	0	2147483647	1828	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1828	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1828	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1715	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1838	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.BusySrcReqChk_A	0	0	2147483647	1710169	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcAckBusyChk_A	0	0	2147483647	1836	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1836	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1836	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1722	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1843	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.BusySrcReqChk_A	0	0	2147483647	1736310	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcAckBusyChk_A	0	0	2147483647	1841	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1841	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1841	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1727	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1852	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.BusySrcReqChk_A	0	0	2147483647	1712140	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcAckBusyChk_A	0	0	2147483647	1823	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1823	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1823	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1710	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1831	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.BusySrcReqChk_A	0	0	2147483647	1721159	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcAckBusyChk_A	0	0	2147483647	1818	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1818	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1818	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1704	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1828	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.BusySrcReqChk_A	0	0	2147483647	1684046	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcAckBusyChk_A	0	0	2147483647	1811	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1811	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1811	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1700	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1817	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.BusySrcReqChk_A	0	0	2147483647	1739010	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcAckBusyChk_A	0	0	2147483647	1870	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1870	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1870	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1756	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1878	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	35229414	650592	0	916
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	35229414	650771	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	650780	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	35229414	650461	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	35229414	634994	0	916
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	35229414	642842	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	642847	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	35229414	632315	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	31829805	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	37637	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	37637	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	37650	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	37523	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	37686	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.BusySrcReqChk_A	0	0	2147483647	15612979	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcAckBusyChk_A	0	0	2147483647	19256	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	19256	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	19256	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	19139	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	19268	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.BusySrcReqChk_A	0	0	2147483647	99127	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcAckBusyChk_A	0	0	2147483647	92	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	35229414	3293277	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	3293402	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	35229414	1721262	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	80	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	392	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	10866706	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	13692	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	13692	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	13692	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	13564	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	13732	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	14128671	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	17495	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	17495	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	17495	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	17377	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	17505	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	10920866	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	13674	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	13674	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	13674	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	13544	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	13714	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	1251229	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	1325	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1325	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	35229414	1325	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	1214	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1334	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	917	917	0	0
tb.dut.u_reg.u_filter_status_cdc.BusySrcReqChk_A	0	0	2147483647	64051879	0	0
tb.dut.u_reg.u_filter_status_cdc.DstReqKnown_A	0	0	35229414	34893442	0	0
tb.dut.u_reg.u_filter_status_cdc.SrcAckBusyChk_A	0	0	2147483647	68381	0	0
tb.dut.u_reg.u_filter_status_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	35229414	15867	0	916
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	35229414	15936	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	84317	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	35229414	83586	0	0
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	35229414	68265	0	0
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	68390	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	917	917	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	917	917	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	917	917	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	917	917	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	917	917	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	917	917	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	917	917	0	0
tb.dut.u_reg.wePulse	0	0	2147483647	283412	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	35229414	650592	0	916
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	35229414	634994	0	916
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	35229414	0	0	916
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	35229414	15867	0	916

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	1435096	1435096	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	1539	1539	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	3326	3326	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	2075	2075	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	2896	2896	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	1660	1660	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	1550	1550	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	4353	4353	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	8470	8470	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	1272311	1272311	848

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	1435096	1435096	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	1539	1539	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	3326	3326	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	2075	2075	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	2896	2896	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	1660	1660	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	1550	1550	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	4353	4353	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	8470	8470	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	1272311	1272311	848