CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 26212 | 1 | T1 | 100 | T2 | 49 | T3 | 30 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[ADC_CTRL_FILTER_COND_IN] | 22846 | 1 | T1 | 100 | T2 | 49 | T3 | 16 | ||||
auto[ADC_CTRL_FILTER_COND_OUT] | 3366 | 1 | T3 | 14 | T5 | 30 | T9 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 20375 | 1 | T1 | 100 | T3 | 30 | T4 | 20 | ||||
auto[1] | 5837 | 1 | T2 | 49 | T5 | 22 | T6 | 40 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22209 | 1 | T1 | 100 | T2 | 49 | T3 | 22 | ||||
auto[1] | 4003 | 1 | T3 | 8 | T11 | 17 | T52 | 26 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 0 | 12 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
maximum | 58 | 1 | T148 | 10 | T192 | 19 | T193 | 29 | ||||
values[0] | 39 | 1 | T12 | 8 | T82 | 17 | T163 | 14 | ||||
values[1] | 717 | 1 | T5 | 22 | T9 | 1 | T194 | 18 | ||||
values[2] | 637 | 1 | T11 | 1 | T44 | 13 | T25 | 20 | ||||
values[3] | 679 | 1 | T5 | 8 | T28 | 1 | T63 | 22 | ||||
values[4] | 432 | 1 | T84 | 2 | T63 | 22 | T130 | 2 | ||||
values[5] | 622 | 1 | T11 | 8 | T42 | 28 | T195 | 1 | ||||
values[6] | 860 | 1 | T37 | 5 | T39 | 11 | T29 | 20 | ||||
values[7] | 884 | 1 | T9 | 1 | T51 | 14 | T39 | 4 | ||||
values[8] | 844 | 1 | T3 | 7 | T37 | 4 | T16 | 9 | ||||
values[9] | 3529 | 1 | T2 | 49 | T3 | 7 | T6 | 40 | ||||
minimum | 16911 | 1 | T1 | 100 | T3 | 16 | T4 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 817 | 1 | T5 | 22 | T9 | 1 | T11 | 1 | ||||
values[1] | 780 | 1 | T5 | 8 | T44 | 13 | T25 | 20 | ||||
values[2] | 488 | 1 | T28 | 1 | T63 | 22 | T130 | 1 | ||||
values[3] | 515 | 1 | T84 | 2 | T63 | 22 | T130 | 1 | ||||
values[4] | 868 | 1 | T11 | 8 | T37 | 5 | T42 | 28 | ||||
values[5] | 868 | 1 | T39 | 11 | T32 | 8 | T82 | 12 | ||||
values[6] | 3128 | 1 | T2 | 49 | T3 | 7 | T6 | 40 | ||||
values[7] | 787 | 1 | T15 | 11 | T26 | 2 | T28 | 3 | ||||
values[8] | 885 | 1 | T3 | 7 | T42 | 3 | T84 | 1 | ||||
values[9] | 160 | 1 | T9 | 1 | T11 | 11 | T149 | 19 | ||||
minimum | 16916 | 1 | T1 | 100 | T3 | 16 | T4 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 21855 | 1 | T1 | 100 | T2 | 3 | T3 | 24 | ||||
auto[1] | 4357 | 1 | T2 | 46 | T3 | 6 | T5 | 28 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 237 | 1 | T9 | 1 | T11 | 1 | T12 | 8 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 233 | 1 | T5 | 22 | T29 | 11 | T63 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 315 | 1 | T44 | 10 | T26 | 4 | T48 | 2 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 119 | 1 | T5 | 8 | T25 | 11 | T32 | 3 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 117 | 1 | T28 | 1 | T92 | 3 | T50 | 4 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 123 | 1 | T63 | 11 | T130 | 1 | T168 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 120 | 1 | T84 | 1 | T130 | 1 | T171 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 191 | 1 | T84 | 1 | T63 | 9 | T195 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 220 | 1 | T11 | 1 | T37 | 3 | T42 | 15 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 239 | 1 | T29 | 10 | T89 | 9 | T196 | 16 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 233 | 1 | T32 | 8 | T82 | 12 | T197 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 277 | 1 | T39 | 6 | T83 | 1 | T127 | 14 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 1769 | 1 | T2 | 49 | T6 | 40 | T7 | 28 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 180 | 1 | T3 | 3 | T9 | 1 | T51 | 14 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 206 | 1 | T15 | 8 | T26 | 1 | T28 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 234 | 1 | T16 | 7 | T82 | 9 | T83 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 294 | 1 | T148 | 10 | T198 | 1 | T199 | 4 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 212 | 1 | T3 | 5 | T42 | 1 | T84 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 76 | 1 | T200 | 8 | T201 | 1 | T202 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 37 | 1 | T9 | 1 | T11 | 1 | T149 | 10 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16776 | 1 | T1 | 100 | T3 | 14 | T4 | 20 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 1 | 1 | T203 | 1 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 202 | 1 | T31 | 9 | T127 | 11 | T48 | 1 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 145 | 1 | T29 | 2 | T63 | 3 | T168 | 7 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 240 | 1 | T44 | 3 | T26 | 3 | T87 | 11 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 106 | 1 | T25 | 9 | T49 | 12 | T128 | 5 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 108 | 1 | T92 | 6 | T50 | 1 | T204 | 7 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 140 | 1 | T63 | 11 | T168 | 8 | T92 | 14 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 76 | 1 | T133 | 11 | T205 | 4 | T206 | 4 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 128 | 1 | T63 | 13 | T87 | 5 | T207 | 16 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 204 | 1 | T11 | 7 | T37 | 2 | T42 | 13 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 205 | 1 | T29 | 10 | T89 | 12 | T146 | 2 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 160 | 1 | T197 | 10 | T55 | 13 | T128 | 7 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 198 | 1 | T39 | 5 | T127 | 10 | T208 | 2 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 989 | 1 | T52 | 26 | T45 | 11 | T31 | 33 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 190 | 1 | T3 | 4 | T37 | 1 | T39 | 1 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 158 | 1 | T15 | 3 | T26 | 1 | T28 | 2 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 189 | 1 | T16 | 2 | T34 | 1 | T88 | 21 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 200 | 1 | T148 | 16 | T204 | 4 | T137 | 11 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 179 | 1 | T3 | 2 | T42 | 2 | T17 | 2 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 10 | 1 | T209 | 4 | T210 | 3 | T211 | 3 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 37 | 1 | T11 | 10 | T149 | 9 | T212 | 7 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 136 | 1 | T3 | 2 | T15 | 1 | T17 | 2 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 3 | 1 | T203 | 3 | - | - | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 7 | 41 | 85.42 | 7 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [values[0]] | * | -- | -- | 2 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [maximum] | [auto[ADC_CTRL_FILTER_COND_IN]] | 0 | 1 | 1 | |
[auto[0]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [maximum] | [auto[ADC_CTRL_FILTER_COND_IN]] | 0 | 1 | 1 | |
[auto[1]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 26 | 1 | T148 | 1 | T192 | 10 | T193 | 15 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 39 | 1 | T12 | 8 | T82 | 17 | T163 | 14 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 209 | 1 | T9 | 1 | T194 | 18 | T31 | 8 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 176 | 1 | T5 | 22 | T63 | 1 | T168 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 225 | 1 | T11 | 1 | T44 | 10 | T26 | 4 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 137 | 1 | T25 | 11 | T29 | 11 | T32 | 3 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 170 | 1 | T28 | 1 | T50 | 4 | T213 | 3 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 188 | 1 | T5 | 8 | T63 | 11 | T48 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 112 | 1 | T84 | 1 | T130 | 1 | T92 | 3 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 144 | 1 | T84 | 1 | T63 | 9 | T130 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 226 | 1 | T11 | 1 | T42 | 15 | T17 | 5 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 135 | 1 | T195 | 1 | T146 | 15 | T214 | 4 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 184 | 1 | T37 | 3 | T32 | 8 | T131 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 268 | 1 | T39 | 6 | T29 | 10 | T83 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 198 | 1 | T82 | 12 | T63 | 1 | T197 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 309 | 1 | T9 | 1 | T51 | 14 | T39 | 3 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 253 | 1 | T31 | 25 | T167 | 15 | T215 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 211 | 1 | T3 | 3 | T37 | 3 | T16 | 7 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 1972 | 1 | T2 | 49 | T6 | 40 | T7 | 28 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 252 | 1 | T3 | 5 | T9 | 1 | T11 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16775 | 1 | T1 | 100 | T3 | 14 | T4 | 20 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 32 | 1 | T148 | 9 | T192 | 9 | T193 | 14 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 206 | 1 | T31 | 9 | T127 | 11 | T48 | 1 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 126 | 1 | T63 | 3 | T168 | 7 | T88 | 2 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 186 | 1 | T44 | 3 | T26 | 3 | T89 | 12 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 89 | 1 | T25 | 9 | T29 | 2 | T216 | 1 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 137 | 1 | T50 | 1 | T213 | 2 | T204 | 7 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 184 | 1 | T63 | 11 | T168 | 8 | T49 | 12 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 71 | 1 | T92 | 6 | T217 | 11 | T218 | 6 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 105 | 1 | T63 | 13 | T87 | 5 | T219 | 14 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 160 | 1 | T11 | 7 | T42 | 13 | T17 | 3 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 101 | 1 | T146 | 2 | T220 | 15 | T207 | 13 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 196 | 1 | T37 | 2 | T55 | 13 | T203 | 9 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 212 | 1 | T39 | 5 | T29 | 10 | T127 | 10 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 80 | 1 | T197 | 10 | T171 | 2 | T128 | 7 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 297 | 1 | T39 | 1 | T221 | 7 | T222 | 15 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 227 | 1 | T31 | 33 | T167 | 20 | T19 | 2 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 153 | 1 | T3 | 4 | T37 | 1 | T16 | 2 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 1084 | 1 | T52 | 26 | T45 | 11 | T15 | 3 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 221 | 1 | T3 | 2 | T11 | 10 | T42 | 2 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 136 | 1 | T3 | 2 | T15 | 1 | T17 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 6 | 42 | 87.50 | 6 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [maximum] | * | -- | -- | 2 | |
[auto[1]] | [maximum] | * | -- | -- | 2 | |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 263 | 1 | T9 | 1 | T11 | 1 | T12 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T5 | 1 | T29 | 3 | T63 | 4 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 283 | 1 | T44 | 4 | T26 | 6 | T48 | 2 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 143 | 1 | T5 | 1 | T25 | 10 | T32 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 150 | 1 | T28 | 1 | T92 | 7 | T50 | 3 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 166 | 1 | T63 | 12 | T130 | 1 | T168 | 9 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 102 | 1 | T84 | 1 | T130 | 1 | T171 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 158 | 1 | T84 | 1 | T63 | 14 | T195 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 247 | 1 | T11 | 8 | T37 | 3 | T42 | 15 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 241 | 1 | T29 | 11 | T89 | 13 | T196 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 201 | 1 | T32 | 1 | T82 | 1 | T197 | 11 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 243 | 1 | T39 | 6 | T83 | 1 | T127 | 11 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 1352 | 1 | T2 | 3 | T6 | 3 | T7 | 2 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 230 | 1 | T3 | 5 | T9 | 1 | T51 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 202 | 1 | T15 | 9 | T26 | 2 | T28 | 3 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 231 | 1 | T16 | 7 | T82 | 1 | T83 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 244 | 1 | T148 | 17 | T198 | 1 | T199 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 225 | 1 | T3 | 3 | T42 | 3 | T84 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 22 | 1 | T200 | 1 | T201 | 1 | T202 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 44 | 1 | T9 | 1 | T11 | 11 | T149 | 10 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16912 | 1 | T1 | 100 | T3 | 16 | T4 | 20 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 4 | 1 | T203 | 4 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 176 | 1 | T12 | 7 | T194 | 17 | T31 | 7 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 186 | 1 | T5 | 21 | T29 | 10 | T88 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 272 | 1 | T44 | 9 | T26 | 1 | T87 | 9 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 82 | 1 | T5 | 7 | T25 | 10 | T32 | 2 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 75 | 1 | T92 | 2 | T50 | 2 | T204 | 4 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 97 | 1 | T63 | 10 | T92 | 16 | T128 | 12 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 94 | 1 | T145 | 14 | T206 | 17 | T155 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 161 | 1 | T63 | 8 | T87 | 3 | T199 | 15 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 177 | 1 | T37 | 2 | T42 | 13 | T17 | 2 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 203 | 1 | T29 | 9 | T89 | 8 | T196 | 15 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 192 | 1 | T32 | 7 | T82 | 11 | T55 | 12 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 232 | 1 | T39 | 5 | T127 | 13 | T159 | 17 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 1406 | 1 | T2 | 46 | T6 | 37 | T7 | 26 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 140 | 1 | T3 | 2 | T51 | 13 | T37 | 1 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 162 | 1 | T15 | 2 | T167 | 11 | T136 | 15 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T16 | 2 | T82 | 8 | T88 | 10 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 250 | 1 | T148 | 9 | T199 | 3 | T204 | 15 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 166 | 1 | T3 | 4 | T17 | 2 | T199 | 7 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 64 | 1 | T200 | 7 | T223 | 13 | T224 | 12 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 30 | 1 | T149 | 9 | T225 | 6 | T226 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 7 | 41 | 85.42 | 7 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [maximum] | [auto[ADC_CTRL_FILTER_COND_IN]] | 0 | 1 | 1 | |
[auto[0]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [maximum] | [auto[ADC_CTRL_FILTER_COND_IN]] | 0 | 1 | 1 | |
[auto[1]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 35 | 1 | T148 | 10 | T192 | 10 | T193 | 15 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 3 | 1 | T12 | 1 | T82 | 1 | T163 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 259 | 1 | T9 | 1 | T194 | 1 | T31 | 10 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 164 | 1 | T5 | 1 | T63 | 4 | T168 | 8 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 225 | 1 | T11 | 1 | T44 | 4 | T26 | 6 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 122 | 1 | T25 | 10 | T29 | 3 | T32 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 177 | 1 | T28 | 1 | T50 | 3 | T213 | 3 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 222 | 1 | T5 | 1 | T63 | 12 | T48 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 102 | 1 | T84 | 1 | T130 | 1 | T92 | 7 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 130 | 1 | T84 | 1 | T63 | 14 | T130 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 200 | 1 | T11 | 8 | T42 | 15 | T17 | 6 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 131 | 1 | T195 | 1 | T146 | 3 | T214 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 240 | 1 | T37 | 3 | T32 | 1 | T131 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 250 | 1 | T39 | 6 | T29 | 11 | T83 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 122 | 1 | T82 | 1 | T63 | 1 | T197 | 11 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 350 | 1 | T9 | 1 | T51 | 1 | T39 | 3 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 269 | 1 | T31 | 35 | T167 | 22 | T215 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 191 | 1 | T3 | 5 | T37 | 3 | T16 | 7 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 1470 | 1 | T2 | 3 | T6 | 3 | T7 | 2 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 282 | 1 | T3 | 3 | T9 | 1 | T11 | 11 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16911 | 1 | T1 | 100 | T3 | 16 | T4 | 20 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 23 | 1 | T192 | 9 | T193 | 14 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 36 | 1 | T12 | 7 | T82 | 16 | T163 | 13 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 156 | 1 | T194 | 17 | T31 | 7 | T127 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 138 | 1 | T5 | 21 | T88 | 2 | T128 | 2 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 186 | 1 | T44 | 9 | T26 | 1 | T89 | 14 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 104 | 1 | T25 | 10 | T29 | 10 | T32 | 2 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 130 | 1 | T50 | 2 | T213 | 2 | T204 | 4 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 150 | 1 | T5 | 7 | T63 | 10 | T49 | 8 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 81 | 1 | T92 | 2 | T145 | 14 | T155 | 8 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 119 | 1 | T63 | 8 | T87 | 3 | T199 | 15 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 186 | 1 | T42 | 13 | T17 | 2 | T127 | 8 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 105 | 1 | T146 | 14 | T214 | 3 | T207 | 14 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 140 | 1 | T37 | 2 | T32 | 7 | T55 | 12 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 230 | 1 | T39 | 5 | T29 | 9 | T127 | 13 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 156 | 1 | T82 | 11 | T128 | 2 | T129 | 4 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 256 | 1 | T51 | 13 | T39 | 1 | T159 | 17 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 211 | 1 | T31 | 23 | T167 | 13 | T136 | 15 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 173 | 1 | T3 | 2 | T37 | 1 | T16 | 2 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 1586 | 1 | T2 | 46 | T6 | 37 | T7 | 26 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 191 | 1 | T3 | 4 | T17 | 2 | T199 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 4 | 2 | 2 | 50.00 | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [auto[1]] | -- | -- | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | auto[0] | 21855 | 1 | T1 | 100 | T2 | 3 | T3 | 24 | ||||
auto[1] | auto[0] | 4357 | 1 | T2 | 46 | T3 | 6 | T5 | 28 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 26212 | 1 | T1 | 100 | T2 | 49 | T3 | 30 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[ADC_CTRL_FILTER_COND_IN] | 22773 | 1 | T1 | 100 | T2 | 49 | T3 | 23 | ||||
auto[ADC_CTRL_FILTER_COND_OUT] | 3439 | 1 | T3 | 7 | T9 | 1 | T11 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 20125 | 1 | T1 | 100 | T3 | 23 | T4 | 20 | ||||
auto[1] | 6087 | 1 | T2 | 49 | T3 | 7 | T5 | 22 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 22209 | 1 | T1 | 100 | T2 | 49 | T3 | 22 | ||||
auto[1] | 4003 | 1 | T3 | 8 | T11 | 17 | T52 | 26 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 116 | 1 | T88 | 32 | T173 | 13 | T162 | 5 | ||||
values[1] | 719 | 1 | T9 | 1 | T26 | 7 | T29 | 13 | ||||
values[2] | 3006 | 1 | T2 | 49 | T6 | 40 | T7 | 28 | ||||
values[3] | 721 | 1 | T5 | 22 | T9 | 1 | T37 | 5 | ||||
values[4] | 646 | 1 | T37 | 4 | T42 | 27 | T39 | 11 | ||||
values[5] | 672 | 1 | T39 | 4 | T44 | 13 | T31 | 29 | ||||
values[6] | 759 | 1 | T26 | 2 | T32 | 8 | T82 | 17 | ||||
values[7] | 616 | 1 | T5 | 8 | T11 | 1 | T15 | 11 | ||||
values[8] | 783 | 1 | T3 | 14 | T11 | 8 | T51 | 14 | ||||
values[9] | 1263 | 1 | T9 | 1 | T11 | 11 | T194 | 18 | ||||
minimum | 16911 | 1 | T1 | 100 | T3 | 16 | T4 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 990 | 1 | T9 | 1 | T26 | 7 | T29 | 13 | ||||
values[1] | 3065 | 1 | T2 | 49 | T6 | 40 | T7 | 28 | ||||
values[2] | 643 | 1 | T5 | 22 | T42 | 1 | T148 | 26 | ||||
values[3] | 580 | 1 | T37 | 4 | T42 | 27 | T39 | 11 | ||||
values[4] | 687 | 1 | T39 | 4 | T82 | 17 | T83 | 1 | ||||
values[5] | 668 | 1 | T11 | 1 | T44 | 13 | T26 | 2 | ||||
values[6] | 798 | 1 | T3 | 7 | T5 | 8 | T15 | 11 | ||||
values[7] | 667 | 1 | T3 | 7 | T11 | 8 | T51 | 14 | ||||
values[8] | 915 | 1 | T9 | 1 | T194 | 18 | T32 | 3 | ||||
values[9] | 258 | 1 | T11 | 11 | T129 | 16 | T203 | 4 | ||||
minimum | 16941 | 1 | T1 | 100 | T3 | 16 | T4 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 21855 | 1 | T1 | 100 | T2 | 3 | T3 | 24 | ||||
auto[1] | 4357 | 1 | T2 | 46 | T3 | 6 | T5 | 28 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 246 | 1 | T9 | 1 | T26 | 4 | T31 | 14 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 291 | 1 | T29 | 11 | T17 | 5 | T167 | 12 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 1789 | 1 | T2 | 49 | T6 | 40 | T7 | 28 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 157 | 1 | T9 | 1 | T12 | 8 | T82 | 12 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 234 | 1 | T5 | 22 | T42 | 1 | T171 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 168 | 1 | T148 | 10 | T221 | 1 | T227 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 124 | 1 | T42 | 14 | T28 | 1 | T63 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 174 | 1 | T37 | 3 | T39 | 6 | T29 | 10 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 188 | 1 | T83 | 1 | T63 | 1 | T197 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 165 | 1 | T39 | 3 | T82 | 17 | T130 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 197 | 1 | T11 | 1 | T44 | 10 | T26 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 233 | 1 | T48 | 2 | T49 | 2 | T92 | 3 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 221 | 1 | T3 | 3 | T5 | 8 | T28 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 204 | 1 | T15 | 8 | T16 | 7 | T128 | 16 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 153 | 1 | T51 | 14 | T31 | 8 | T83 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 187 | 1 | T3 | 5 | T11 | 1 | T25 | 11 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 248 | 1 | T9 | 1 | T32 | 3 | T17 | 3 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 300 | 1 | T194 | 18 | T84 | 1 | T215 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 128 | 1 | T11 | 1 | T129 | 16 | T203 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 24 | 1 | T190 | 3 | T228 | 1 | T229 | 12 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16776 | 1 | T1 | 100 | T3 | 14 | T4 | 20 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 2 | 1 | T132 | 1 | T141 | 1 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 172 | 1 | T26 | 3 | T31 | 15 | T204 | 13 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 281 | 1 | T29 | 2 | T17 | 3 | T167 | 10 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 1011 | 1 | T52 | 26 | T37 | 2 | T42 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 108 | 1 | T168 | 7 | T87 | 5 | T221 | 2 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 123 | 1 | T171 | 2 | T50 | 1 | T230 | 5 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 118 | 1 | T148 | 16 | T221 | 7 | T227 | 2 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 105 | 1 | T42 | 13 | T28 | 2 | T63 | 3 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 177 | 1 | T37 | 1 | T39 | 5 | T29 | 10 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 172 | 1 | T197 | 10 | T55 | 13 | T214 | 5 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 162 | 1 | T39 | 1 | T167 | 10 | T128 | 5 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 96 | 1 | T44 | 3 | T26 | 1 | T63 | 11 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 142 | 1 | T92 | 6 | T146 | 2 | T203 | 3 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 217 | 1 | T3 | 4 | T49 | 12 | T213 | 14 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 156 | 1 | T15 | 3 | T16 | 2 | T128 | 18 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 140 | 1 | T31 | 9 | T63 | 13 | T168 | 8 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 187 | 1 | T3 | 2 | T11 | 7 | T25 | 9 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 201 | 1 | T17 | 2 | T148 | 9 | T92 | 21 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 166 | 1 | T19 | 2 | T204 | 4 | T137 | 11 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 82 | 1 | T11 | 10 | T203 | 3 | T231 | 24 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 24 | 1 | T190 | 3 | T229 | 7 | T96 | 2 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 150 | 1 | T3 | 2 | T15 | 1 | T17 | 2 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 13 | 1 | T141 | 13 | - | - | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 6 | 42 | 87.50 | 6 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 | |
* | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | -- | -- | 2 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 37 | 1 | T162 | 1 | T232 | 7 | T233 | 12 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 28 | 1 | T88 | 11 | T173 | 13 | T211 | 4 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 148 | 1 | T9 | 1 | T26 | 4 | T31 | 14 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 211 | 1 | T29 | 11 | T17 | 5 | T167 | 12 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 1740 | 1 | T2 | 49 | T6 | 40 | T7 | 28 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 177 | 1 | T12 | 8 | T127 | 9 | T168 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 275 | 1 | T5 | 22 | T37 | 3 | T42 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T9 | 1 | T82 | 12 | T221 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 193 | 1 | T42 | 14 | T28 | 1 | T63 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 171 | 1 | T37 | 3 | T39 | 6 | T29 | 10 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 176 | 1 | T44 | 10 | T63 | 1 | T234 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 162 | 1 | T39 | 3 | T31 | 11 | T82 | 9 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 178 | 1 | T26 | 1 | T32 | 8 | T83 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 261 | 1 | T82 | 17 | T49 | 2 | T92 | 3 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 181 | 1 | T5 | 8 | T11 | 1 | T28 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 182 | 1 | T15 | 8 | T16 | 7 | T48 | 2 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 212 | 1 | T3 | 3 | T51 | 14 | T31 | 8 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 188 | 1 | T3 | 5 | T11 | 1 | T25 | 11 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 389 | 1 | T9 | 1 | T11 | 1 | T32 | 3 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 350 | 1 | T194 | 18 | T89 | 15 | T215 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16775 | 1 | T1 | 100 | T3 | 14 | T4 | 20 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 27 | 1 | T162 | 4 | T233 | 14 | T235 | 9 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 24 | 1 | T88 | 21 | T211 | 3 | - | - | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 132 | 1 | T26 | 3 | T31 | 15 | T204 | 13 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 228 | 1 | T29 | 2 | T17 | 3 | T167 | 10 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 946 | 1 | T52 | 26 | T42 | 2 | T45 | 11 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 143 | 1 | T168 | 7 | T20 | 1 | T216 | 13 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 165 | 1 | T37 | 2 | T48 | 1 | T87 | 11 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 106 | 1 | T221 | 7 | T236 | 4 | T237 | 1 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 139 | 1 | T42 | 13 | T28 | 2 | T63 | 3 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 143 | 1 | T37 | 1 | T39 | 5 | T29 | 10 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 157 | 1 | T44 | 3 | T149 | 9 | T238 | 1 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 177 | 1 | T39 | 1 | T31 | 18 | T167 | 10 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 141 | 1 | T26 | 1 | T63 | 11 | T197 | 10 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 179 | 1 | T92 | 6 | T203 | 3 | T18 | 3 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 131 | 1 | T239 | 8 | T240 | 10 | T241 | 5 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 122 | 1 | T15 | 3 | T16 | 2 | T128 | 11 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 208 | 1 | T3 | 4 | T31 | 9 | T63 | 13 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T3 | 2 | T11 | 7 | T25 | 9 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 287 | 1 | T11 | 10 | T17 | 2 | T148 | 9 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 237 | 1 | T89 | 12 | T242 | 8 | T19 | 2 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 136 | 1 | T3 | 2 | T15 | 1 | T17 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |