Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T1

100

T2

49

T3

30

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22369

1

T1

100

T2

49

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3843

1

T3

7

T5

22

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20142

1

T1

100

T3

30

T4

20

auto[1]

6070

1

T2

49

T5

30

T6

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22209

1

T1

100

T2

49

T3

22

auto[1]

4003

1

T3

8

T11

17

T52

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	65	1			T207	29		T285	18		T290	16
values[0]	61	1			T17	5		T168	8		T291	1
values[1]	764	1			T32	8		T84	1		T63	22
values[2]	571	1			T5	22		T9	1		T82	17
values[3]	905	1			T5	8		T42	27		T39	11
values[4]	3235	1			T2	49		T6	40		T7	28
values[5]	671	1			T29	33		T31	29		T130	1
values[6]	583	1			T16	9		T83	1		T63	26
values[7]	720	1			T3	7		T11	11		T42	1
values[8]	673	1			T37	5		T39	4		T26	9
values[9]	1053	1			T3	7		T9	1		T11	1
minimum	16911	1			T1	100		T3	16		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1025	1			T5	22		T9	1		T32	8
values[1]	672	1			T39	11		T82	17		T83	1
values[2]	820	1			T5	8		T9	1		T11	8
values[3]	3171	1			T2	49		T6	40		T7	28
values[4]	602	1			T16	9		T31	29		T82	12
values[5]	754	1			T83	1		T84	1		T63	26
values[6]	655	1			T3	7		T37	5		T42	1
values[7]	628	1			T3	7		T11	11		T12	8
values[8]	653	1			T11	1		T51	14		T37	4
values[9]	315	1			T9	1		T130	1		T49	19
minimum	16917	1			T1	100		T3	16		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

4357

1

T2

46

T3

6

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	1		T32	8		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T5	22		T63	9		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T39	6		T82	17		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T17	5		T131	1		T49	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	8		T9	1		T82	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	1		T44	10		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1724	1			T2	49		T6	40		T7	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T42	14		T194	18		T25	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T16	7		T31	14		T127	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T82	12		T128	13		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T83	1		T63	11		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T84	1		T63	1		T127	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T37	3		T42	1		T128	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	3		T48	1		T89	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	5		T12	8		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	1		T26	5		T49	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T11	1		T51	14		T37	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	8		T28	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T130	1		T49	7		T146	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T9	1		T244	20		T278	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T1	100		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T17	3		T291	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T168	7		T221	2		T207	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T63	13		T221	7		T19	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T39	5		T242	8		T227	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T17	3		T88	21		T128	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T88	2		T171	2		T247	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	7		T44	3		T127	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T52	26		T45	11		T248	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T42	13		T25	9		T29	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	2		T31	15		T127	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T128	11		T50	1		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T63	11		T197	10		T92	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T63	3		T148	16		T204	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T37	2		T128	5		T146	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	4		T89	12		T213	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	2		T34	1		T168	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	10		T26	4		T247	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T37	1		T42	2		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T15	3		T28	2		T203	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T49	12		T146	2		T222	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T244	13		T278	12		T160	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T17	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T207	13		T285	3		T292	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T290	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T168	1		T102	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T17	3		T291	1		T293	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T32	8		T84	1		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T63	9		T136	16		T19	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T9	1		T82	17		T63	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	22		T131	1		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	8		T39	6		T82	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T42	14		T44	10		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1757	1			T2	49		T6	40		T7	28
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	1		T194	18		T25	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T31	14		T127	3		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T29	21		T130	1		T128	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T16	7		T83	1		T63	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T63	1		T127	9		T148	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T42	1		T197	1		T128	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	3		T11	1		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T37	3		T39	3		T168	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T26	5		T49	6		T129	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T3	5		T11	1		T12	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T9	1		T15	8		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T1	100		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T207	16		T285	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T168	7		T102	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T17	2		T269	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T221	2		T207	13		T230	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T63	13		T19	2		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T227	2		T294	3		T295	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T88	21		T89	12		T221	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	5		T88	2		T171	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T42	13		T44	3		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T52	26		T45	11		T248	30
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	7		T25	9		T31	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T31	15		T127	11		T208	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T29	12		T128	11		T50	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T16	2		T63	11		T92	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T63	3		T148	16		T204	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T197	10		T128	5		T146	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	4		T11	10		T89	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T37	2		T39	1		T168	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T26	4		T133	11		T238	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	2		T37	1		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T15	3		T28	2		T203	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	1		T32	1		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T5	1		T63	14		T221	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	6		T82	1		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T17	6		T131	1		T49	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	1		T9	1		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	8		T44	4		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T2	3		T6	3		T7	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T42	14		T194	1		T25	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T16	7		T31	16		T127	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T82	1		T128	12		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T83	1		T63	12		T197	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T84	1		T63	4		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T37	3		T42	1		T128	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	5		T48	1		T89	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	3		T12	1		T34	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	11		T26	8		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	1		T51	1		T37	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	9		T28	3		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T130	1		T49	16		T146	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T9	1		T244	14		T278	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T17	3		T291	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T32	7		T196	15		T207	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	21		T63	8		T136	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T39	5		T82	16		T159	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	2		T88	10		T128	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	7		T82	8		T88	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T44	9		T127	13		T55	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T2	46		T6	37		T7	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T42	13		T194	17		T25	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T16	2		T31	13		T127	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T82	11		T128	12		T50	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T63	10		T92	2		T192	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T127	8		T148	9		T136	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T37	2		T128	2		T146	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	2		T89	14		T213	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	4		T12	7		T87	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T26	1		T49	5		T129	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T51	13		T37	1		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	2		T200	7		T252	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T49	3		T146	14		T222	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T244	19		T278	11		T241	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T17	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T207	17		T285	16		T292	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T290	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T168	8		T102	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T17	3		T291	1		T293	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	1		T84	1		T221	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T63	14		T136	1		T19	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T9	1		T82	1		T63	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	1		T131	1		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	1		T39	6		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T42	14		T44	4		T17	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T2	3		T6	3		T7	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	8		T194	1		T25	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T31	16		T127	12		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T29	14		T130	1		T128	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T16	7		T83	1		T63	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T63	4		T127	1		T148	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T42	1		T197	11		T128	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	5		T11	11		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T37	3		T39	3		T168	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T26	8		T49	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T3	3		T11	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T9	1		T15	9		T28	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T207	12		T285	2		T292	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T290	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T102	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T17	2		T269	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T32	7		T196	15		T207	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T63	8		T136	15		T19	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T82	16		T159	17		T199	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	21		T88	10		T89	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	7		T39	5		T82	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T42	13		T44	9		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T2	46		T6	37		T7	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T194	17		T25	10		T31	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T31	13		T127	2		T208	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T29	19		T128	12		T50	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T16	2		T63	10		T92	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T127	8		T148	9		T199	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T128	2		T146	8		T192	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	2		T89	14		T136	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T37	2		T39	1		T92	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T26	1		T49	5		T129	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T3	4		T12	7		T51	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T15	2		T247	16		T200	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28