Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T1

100

T2

49

T3

30

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22677

1

T1

100

T2

49

T3

30

auto[ADC_CTRL_FILTER_COND_OUT]

3535

1

T5

8

T9

1

T11

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19603

1

T1

97

T3

23

T4

20

auto[1]

6609

1

T1

3

T2

49

T3

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22209

1

T1

100

T2

49

T3

22

auto[1]

4003

1

T3

8

T11

17

T52

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	644	1			T1	3		T9	1		T10	1
values[0]	43	1			T19	9		T223	9		T226	25
values[1]	695	1			T9	1		T11	11		T39	11
values[2]	3035	1			T2	49		T6	40		T7	28
values[3]	740	1			T197	11		T127	24		T168	9
values[4]	687	1			T3	7		T9	1		T28	3
values[5]	803	1			T44	13		T26	2		T31	29
values[6]	708	1			T42	3		T92	24		T129	11
values[7]	770	1			T11	1		T42	1		T15	11
values[8]	600	1			T5	22		T39	4		T25	20
values[9]	990	1			T3	7		T5	8		T11	8
minimum	16497	1			T1	97		T3	16		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	756	1			T9	1		T37	5		T39	11
values[1]	3002	1			T2	49		T6	40		T7	28
values[2]	701	1			T3	7		T9	1		T32	8
values[3]	831	1			T28	3		T82	17		T84	1
values[4]	704	1			T44	13		T26	2		T31	29
values[5]	731	1			T11	1		T42	3		T16	9
values[6]	718	1			T42	1		T39	4		T15	11
values[7]	601	1			T3	7		T5	22		T25	20
values[8]	934	1			T5	8		T9	1		T11	8
values[9]	125	1			T82	9		T221	3		T256	10
minimum	17109	1			T1	100		T3	16		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

4357

1

T2

46

T3

6

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T39	6		T63	10		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	1		T37	3		T194	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1758	1			T2	49		T6	40		T7	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T82	12		T17	3		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	3		T9	1		T197	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T32	8		T168	1		T148	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T84	1		T167	12		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T28	1		T82	17		T49	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T44	10		T26	1		T31	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T84	1		T199	4		T247	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T42	1		T16	7		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	1		T92	17		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	8		T84	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T42	1		T39	3		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	5		T5	22		T25	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T32	3		T167	3		T168	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T9	1		T29	11		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T5	8		T11	1		T51	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T221	1		T256	10		T173	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T82	9		T141	1		T150	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16846	1			T1	100		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T11	1		T130	1		T48	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T39	5		T63	13		T213	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T37	2		T31	18		T63	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T52	26		T42	13		T45	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T17	2		T204	7		T174	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	4		T197	10		T17	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T168	8		T148	16		T92	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T167	10		T87	11		T88	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T28	2		T49	12		T87	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T44	3		T26	1		T31	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T247	14		T231	24		T207	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T42	2		T16	2		T247	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T92	7		T149	15		T230	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T15	3		T220	15		T205	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T39	1		T127	11		T221	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	2		T25	9		T128	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T167	10		T168	7		T148	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T29	2		T63	3		T88	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	7		T37	1		T26	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T221	2		T257	11		T212	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T141	13		T296	1		T297	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	2		T15	1		T17	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T11	10		T48	1		T203	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	531	1			T1	3		T9	1		T10	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T82	9		T49	2		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T223	9		T226	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T19	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T39	6		T63	9		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	1		T11	1		T31	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1739	1			T2	49		T6	40		T7	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T37	3		T194	18		T82	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T197	1		T127	14		T88	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T168	1		T148	10		T92	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	3		T9	1		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T28	1		T32	8		T82	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T44	10		T26	1		T31	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T84	1		T87	4		T159	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T42	1		T129	11		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T92	17		T199	8		T172	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	8		T16	7		T84	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	1		T42	1		T195	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	22		T25	11		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T39	3		T148	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	5		T83	1		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T5	8		T11	1		T51	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16361	1			T1	97		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T29	2		T63	3		T221	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T141	13		T296	1		T298	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T226	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T19	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T39	5		T63	13		T213	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	10		T31	18		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T52	26		T42	13		T45	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T37	2		T63	11		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T197	10		T127	10		T88	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T168	8		T148	16		T92	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	4		T17	3		T167	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T28	2		T49	12		T50	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T44	3		T26	1		T31	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T87	5		T247	14		T249	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T42	2		T149	6		T20	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T92	7		T230	5		T259	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	3		T16	2		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T127	11		T221	7		T213	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T25	9		T35	12		T216	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T39	1		T148	9		T247	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	2		T88	9		T128	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T11	7		T37	1		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T39	6		T63	15		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	1		T37	3		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T2	3		T6	3		T7	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T82	1		T17	3		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	5		T9	1		T197	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T32	1		T168	9		T148	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T84	1		T167	11		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T28	3		T82	1		T49	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T44	4		T26	2		T31	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T84	1		T199	1		T247	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T42	3		T16	7		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	1		T92	8		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	9		T84	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T42	1		T39	3		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	3		T5	1		T25	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T32	1		T167	11		T168	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	1		T29	3		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T5	1		T11	8		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T221	3		T256	1		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T82	1		T141	14		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16958	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T11	11		T130	1		T48	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T39	5		T63	8		T213	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T37	2		T194	17		T31	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T2	46		T6	37		T7	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T82	11		T17	2		T136	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	2		T17	2		T127	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T32	7		T148	9		T92	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T167	11		T87	9		T88	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T82	16		T49	3		T87	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T44	9		T31	13		T144	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T199	3		T247	16		T231	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T16	2		T129	25		T247	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T92	16		T199	7		T172	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	2		T129	4		T258	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T39	1		T127	2		T213	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	4		T5	21		T25	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T32	2		T167	2		T247	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T29	10		T88	12		T242	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	7		T51	13		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T256	9		T173	15		T257	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T82	8		T150	7		T296	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T243	7		T299	11		T152	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T48	2		T19	2		T243	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	499	1			T1	3		T9	1		T10	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T82	1		T49	2		T141	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T223	1		T226	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T19	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T39	6		T63	14		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	1		T11	11		T31	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T2	3		T6	3		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T37	3		T194	1		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T197	11		T127	11		T88	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T168	9		T148	17		T92	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	5		T9	1		T17	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T28	3		T32	1		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T44	4		T26	2		T31	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T84	1		T87	6		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T42	3		T129	1		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T92	8		T199	1		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	9		T16	7		T84	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	1		T42	1		T195	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	1		T25	10		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T39	3		T148	10		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	3		T83	1		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T5	1		T11	8		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16497	1			T1	97		T3	16		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T29	10		T172	11		T256	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T82	8		T296	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T223	8		T226	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T19	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T39	5		T63	8		T213	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T31	10		T48	2		T92	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T2	46		T6	37		T7	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	2		T194	17		T82	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T127	13		T88	10		T146	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T148	9		T92	16		T128	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	2		T17	2		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T32	7		T82	16		T49	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T44	9		T31	13		T88	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T87	3		T159	17		T145	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T129	10		T258	2		T149	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T92	16		T199	7		T172	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	2		T16	2		T129	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T127	2		T213	10		T149	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	21		T25	10		T49	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	1		T247	8		T35	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	4		T88	12		T128	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T5	7		T51	13		T37	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28