Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T1

100

T2

49

T3

30

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22584

1

T1

100

T2

49

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3628

1

T3

7

T5

30

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19880

1

T1

100

T3

30

T4

20

auto[1]

6332

1

T2

49

T5

30

T6

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22209

1

T1

100

T2

49

T3

22

auto[1]

4003

1

T3

8

T11

17

T52

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	311	1			T3	7		T63	22		T136	7
values[0]	71	1			T88	32		T162	21		T158	8
values[1]	728	1			T82	21		T84	1		T127	14
values[2]	581	1			T5	22		T9	1		T11	11
values[3]	754	1			T9	1		T63	23		T195	1
values[4]	572	1			T11	9		T37	4		T42	1
values[5]	3018	1			T2	49		T6	40		T7	28
values[6]	624	1			T3	7		T9	1		T51	14
values[7]	680	1			T39	15		T194	18		T15	11
values[8]	823	1			T5	8		T12	8		T42	3
values[9]	1139	1			T42	27		T44	13		T25	20
minimum	16911	1			T1	100		T3	16		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	740	1			T82	21		T127	38		T48	7
values[1]	623	1			T5	22		T9	1		T11	11
values[2]	777	1			T9	1		T31	29		T195	1
values[3]	2905	1			T2	49		T6	40		T7	28
values[4]	562	1			T29	13		T87	21		T215	2
values[5]	694	1			T3	7		T9	1		T51	14
values[6]	600	1			T39	4		T194	18		T15	11
values[7]	886	1			T5	8		T12	8		T42	3
values[8]	1075	1			T3	7		T42	27		T44	13
values[9]	201	1			T31	29		T63	22		T136	7
minimum	17149	1			T1	100		T3	16		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

4357

1

T2

46

T3

6

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T82	21		T48	6		T55	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T127	17		T49	7		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	1		T26	1		T63	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	22		T9	1		T63	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T9	1		T127	9		T55	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T31	11		T195	1		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1680	1			T2	49		T6	40		T7	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T37	3		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T29	11		T215	1		T145	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T87	10		T215	1		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	3		T9	1		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T51	14		T37	3		T39	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	3		T15	8		T26	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T194	18		T31	8		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T12	8		T130	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T5	8		T42	1		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T44	10		T28	1		T32	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T3	5		T42	14		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T63	11		T136	7		T213	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T31	14		T138	1		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16829	1			T1	100		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T84	1		T49	2		T88	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	1		T55	13		T148	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T127	21		T49	12		T220	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	10		T26	1		T63	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T167	10		T128	12		T141	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T146	7		T222	15		T203	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T31	18		T168	7		T88	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T11	7		T52	26		T45	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T37	1		T87	5		T205	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T29	2		T231	24		T246	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T87	11		T221	2		T50	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	4		T29	10		T63	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T37	2		T39	5		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T39	1		T15	3		T26	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T31	9		T148	9		T171	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T242	8		T18	3		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T42	2		T25	9		T197	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T44	3		T28	2		T17	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T3	2		T42	13		T17	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T63	11		T213	15		T174	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T31	15		T138	10		T300	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	2		T15	1		T17	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T88	21		T207	12		T262	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T63	11		T136	7		T213	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T3	5		T21	1		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T162	6		T158	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T88	11		T284	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T82	21		T48	6		T55	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T84	1		T127	3		T49	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	1		T26	1		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	22		T9	1		T127	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T9	1		T63	9		T127	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T63	1		T195	1		T167	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	1		T131	1		T234	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	1		T37	3		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1788	1			T2	49		T6	40		T7	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T87	10		T215	2		T50	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	3		T9	1		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T51	14		T37	3		T82	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	3		T15	8		T26	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T39	6		T194	18		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	8		T130	1		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	8		T42	1		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T44	10		T28	1		T32	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T42	14		T25	11		T31	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T1	100		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T63	11		T213	15		T174	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T3	2		T216	1		T278	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T162	15		T158	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T88	21		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T48	1		T55	13		T148	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T127	11		T49	12		T149	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	10		T26	1		T168	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T127	10		T220	15		T205	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T63	13		T146	7		T222	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T167	10		T168	7		T88	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	7		T203	3		T247	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T37	1		T31	18		T87	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T52	26		T45	11		T29	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T87	11		T50	1		T238	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	4		T29	10		T63	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T37	2		T128	11		T221	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	1		T15	3		T26	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T39	5		T16	2		T31	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T18	3		T133	11		T207	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T42	2		T197	10		T167	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T44	3		T28	2		T17	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T42	13		T25	9		T31	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T82	2		T48	5		T55	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T127	23		T49	16		T220	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	11		T26	2		T63	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	1		T9	1		T63	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	1		T127	1		T55	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T31	19		T195	1		T168	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T2	3		T6	3		T7	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T37	3		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T29	3		T215	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T87	12		T215	1		T221	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	5		T9	1		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T51	1		T37	3		T39	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	3		T15	9		T26	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T194	1		T31	10		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	1		T130	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T5	1		T42	3		T25	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T44	4		T28	3		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T3	3		T42	14		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T63	12		T136	1		T213	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T31	16		T138	11		T300	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16967	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T84	1		T49	2		T88	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T82	19		T48	2		T55	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T127	15		T49	3		T149	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T63	8		T196	15		T199	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	21		T167	2		T128	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T127	8		T146	8		T222	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T31	10		T88	12		T199	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T2	46		T6	37		T7	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T37	1		T87	3		T256	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T29	10		T145	14		T231	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T87	9		T50	2		T214	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	2		T29	9		T88	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T51	13		T37	2		T39	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T39	1		T15	2		T26	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T194	17		T31	7		T208	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	7		T242	2		T18	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	7		T25	10		T167	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T44	9		T32	2		T17	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T3	4		T42	13		T17	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T63	10		T136	6		T213	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T31	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T89	14		T92	16		T204	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T88	10		T129	4		T207	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T63	12		T136	1		T213	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T3	3		T21	1		T216	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T162	16		T158	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T88	22		T284	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T82	2		T48	5		T55	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T84	1		T127	12		T49	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	11		T26	2		T168	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T5	1		T9	1		T127	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	1		T63	14		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T63	1		T195	1		T167	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	8		T131	1		T234	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	1		T37	3		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T2	3		T6	3		T7	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T87	12		T215	2		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	5		T9	1		T29	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T51	1		T37	3		T82	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	3		T15	9		T26	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T39	6		T194	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	1		T130	1		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T5	1		T42	3		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T44	4		T28	3		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T42	14		T25	10		T31	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T63	10		T136	6		T213	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T3	4		T278	11		T156	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T162	5		T158	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T88	10		T284	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T82	19		T48	2		T55	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T127	2		T49	3		T129	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T159	17		T196	15		T249	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T5	21		T127	13		T129	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T63	8		T127	8		T146	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T167	2		T88	12		T128	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T247	8		T144	5		T268	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T37	1		T31	10		T87	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T2	46		T6	37		T7	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T87	9		T50	2		T214	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	2		T29	9		T88	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T51	13		T37	2		T82	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T39	1		T15	2		T26	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T39	5		T194	17		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	7		T18	4		T258	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	7		T167	11		T49	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T44	9		T32	2		T17	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T42	13		T25	10		T31	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28