Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T1

100

T2

49

T3

30

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22778

1

T1

100

T2

49

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3434

1

T3

14

T5

30

T9

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20377

1

T1

100

T3

30

T4

20

auto[1]

5835

1

T2

49

T6

40

T7

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22209

1

T1

100

T2

49

T3

22

auto[1]

4003

1

T3

8

T11

17

T52

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	276	1			T42	3		T148	10		T215	1
values[0]	41	1			T12	8		T301	23		T302	5
values[1]	695	1			T5	22		T9	1		T194	18
values[2]	641	1			T11	1		T44	13		T25	20
values[3]	657	1			T5	8		T28	1		T63	22
values[4]	472	1			T84	2		T63	22		T130	2
values[5]	636	1			T11	8		T37	5		T42	28
values[6]	841	1			T39	11		T29	20		T32	8
values[7]	937	1			T3	7		T9	1		T51	14
values[8]	810	1			T37	4		T16	9		T31	29
values[9]	3295	1			T2	49		T3	7		T6	40
minimum	16911	1			T1	100		T3	16		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	592	1			T5	22		T9	1		T11	1
values[1]	722	1			T5	8		T44	13		T25	20
values[2]	569	1			T28	1		T63	22		T130	1
values[3]	516	1			T84	2		T63	22		T130	1
values[4]	833	1			T11	8		T37	5		T42	28
values[5]	857	1			T39	11		T32	8		T82	12
values[6]	3155	1			T2	49		T3	7		T6	40
values[7]	752	1			T26	2		T28	3		T16	9
values[8]	959	1			T3	7		T9	1		T11	11
values[9]	104	1			T149	19		T201	1		T202	1
minimum	17153	1			T1	100		T3	16		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

4357

1

T2

46

T3

6

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T11	1		T195	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	22		T29	11		T88	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T44	10		T26	4		T89	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	8		T25	11		T32	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T28	1		T92	3		T50	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T63	11		T130	1		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T130	1		T171	1		T145	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T84	2		T63	9		T195	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	1		T42	15		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T37	3		T29	10		T89	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T32	8		T82	12		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T39	6		T83	1		T127	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1761	1			T2	49		T6	40		T7	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	3		T9	1		T51	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T26	1		T28	1		T31	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T16	7		T83	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T15	8		T148	10		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	5		T9	1		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T202	1		T209	1		T303	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T149	10		T201	1		T225	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16848	1			T1	100		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T63	1		T203	1		T160	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T127	11		T168	7		T87	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T29	2		T88	2		T246	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T44	3		T26	3		T89	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T25	9		T49	12		T128	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T92	6		T50	1		T204	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T63	11		T168	8		T92	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T133	11		T149	6		T205	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T63	13		T87	5		T207	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	7		T42	13		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T37	2		T29	10		T89	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T197	10		T55	13		T128	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T39	5		T127	10		T213	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T52	26		T37	1		T45	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	4		T39	1		T31	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T26	1		T28	2		T31	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T16	2		T34	1		T88	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T15	3		T148	16		T204	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	2		T11	10		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T209	4		T210	3		T211	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T149	9		T153	13		T226	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	2		T15	1		T31	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T63	3		T203	3		T160	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T198	1		T204	16		T256	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T42	1		T148	1		T215	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T12	8		T302	1		T304	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T301	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T9	1		T194	18		T31	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	22		T63	1		T88	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	1		T44	10		T26	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T25	11		T29	11		T32	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T28	1		T50	4		T213	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	8		T63	11		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T130	1		T92	3		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T84	2		T63	9		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	1		T42	15		T17	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T37	3		T195	1		T89	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T32	8		T131	1		T55	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T39	6		T29	10		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T82	12		T63	1		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T3	3		T9	1		T51	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T37	3		T31	11		T167	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T16	7		T82	9		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1889	1			T2	49		T6	40		T7	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	5		T9	1		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T1	100		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T204	4		T174	11		T147	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T42	2		T148	9		T192	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T302	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T301	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T31	9		T127	11		T48	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T63	3		T88	2		T203	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T44	3		T26	3		T89	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T25	9		T29	2		T128	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T50	1		T213	2		T204	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T63	11		T168	8		T49	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T92	6		T219	14		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T63	13		T87	5		T207	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	7		T42	13		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T37	2		T89	12		T146	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T55	13		T221	2		T203	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	5		T29	10		T127	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T197	10		T167	10		T171	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T3	4		T39	1		T31	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T37	1		T31	18		T167	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T16	2		T34	1		T88	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T52	26		T45	11		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	2		T11	10		T17	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	1		T11	1		T195	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T5	1		T29	3		T88	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T44	4		T26	6		T89	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	1		T25	10		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T28	1		T92	7		T50	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T63	12		T130	1		T168	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T130	1		T171	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T84	2		T63	14		T195	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	8		T42	15		T17	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T37	3		T29	11		T89	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T32	1		T82	1		T197	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T39	6		T83	1		T127	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T2	3		T6	3		T7	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	5		T9	1		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T26	2		T28	3		T31	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T16	7		T83	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T15	9		T148	17		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	3		T9	1		T11	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T202	1		T209	5		T303	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T149	10		T201	1		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16962	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T63	4		T203	4		T160	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T127	2		T87	9		T88	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	21		T29	10		T88	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T44	9		T26	1		T89	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T5	7		T25	10		T32	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T92	2		T50	2		T204	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T63	10		T92	16		T204	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T145	14		T256	2		T149	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T63	8		T87	3		T199	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T42	13		T17	2		T127	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T37	2		T29	9		T89	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T32	7		T82	11		T55	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T39	5		T127	13		T159	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T2	46		T6	37		T7	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	2		T51	13		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T31	10		T167	11		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T16	2		T88	10		T129	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T15	2		T148	9		T199	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	4		T17	2		T199	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T305	16		T211	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T149	9		T225	6		T226	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T12	7		T194	17		T31	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T142	11		T162	15		T301	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T198	1		T204	5		T256	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T42	3		T148	10		T215	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T12	1		T302	5		T304	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T301	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	1		T194	1		T31	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T63	4		T88	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	1		T44	4		T26	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T25	10		T29	3		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T28	1		T50	3		T213	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	1		T63	12		T168	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T130	1		T92	7		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T84	2		T63	14		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	8		T42	15		T17	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T37	3		T195	1		T89	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T32	1		T131	1		T55	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T39	6		T29	11		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T82	1		T63	1		T197	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T3	5		T9	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T37	3		T31	19		T167	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T16	7		T82	1		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T2	3		T6	3		T7	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	3		T9	1		T11	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T204	15		T256	16		T200	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T192	9		T193	14		T225	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T12	7		T304	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T301	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T194	17		T31	7		T82	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	21		T88	2		T256	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T44	9		T26	1		T89	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T25	10		T29	10		T32	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T50	2		T213	2		T204	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	7		T63	10		T49	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T92	2		T145	14		T155	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T63	8		T87	3		T199	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T42	13		T17	2		T127	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T37	2		T89	8		T146	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T32	7		T55	12		T18	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T39	5		T29	9		T127	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T82	11		T167	2		T128	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	2		T51	13		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T37	1		T31	10		T167	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	2		T82	8		T88	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T2	46		T6	37		T7	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	4		T17	2		T199	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28