Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T1

100

T2

49

T3

30

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22619

1

T1

100

T2

49

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3593

1

T3

7

T5

8

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19717

1

T1

100

T3

23

T4

20

auto[1]

6495

1

T2

49

T3

7

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22209

1

T1

100

T2

49

T3

22

auto[1]

4003

1

T3

8

T11

17

T52

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	309	1			T11	11		T28	3		T195	1
values[0]	39	1			T48	1		T245	1		T160	11
values[1]	685	1			T42	3		T25	20		T29	13
values[2]	801	1			T12	8		T194	18		T15	11
values[3]	637	1			T51	14		T37	5		T130	1
values[4]	675	1			T26	7		T28	1		T29	20
values[5]	3218	1			T2	49		T3	7		T5	8
values[6]	779	1			T3	7		T9	1		T39	11
values[7]	515	1			T9	1		T11	1		T42	27
values[8]	510	1			T26	2		T130	1		T48	2
values[9]	1133	1			T5	22		T32	3		T82	12
minimum	16911	1			T1	100		T3	16		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	697	1			T42	3		T25	20		T31	29
values[1]	810	1			T12	8		T194	18		T15	11
values[2]	573	1			T51	14		T37	5		T31	29
values[3]	3107	1			T2	49		T6	40		T7	28
values[4]	911	1			T3	14		T5	8		T9	1
values[5]	660	1			T9	2		T11	1		T42	27
values[6]	508	1			T39	4		T82	17		T130	1
values[7]	588	1			T26	2		T32	3		T48	2
values[8]	979	1			T5	22		T11	11		T28	3
values[9]	217	1			T63	22		T17	8		T217	6
minimum	17162	1			T1	100		T3	16		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

4357

1

T2

46

T3

6

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T42	1		T25	11		T31	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T83	1		T63	9		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	8		T31	8		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T194	18		T15	8		T127	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T195	1		T171	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T51	14		T37	3		T31	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1783	1			T2	49		T6	40		T7	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T42	1		T26	4		T63	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	5		T9	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T3	3		T5	8		T44	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	1		T11	1		T42	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	1		T39	6		T129	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T82	17		T135	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T39	3		T130	1		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T26	1		T32	3		T48	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T55	13		T129	5		T204	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T5	22		T11	1		T82	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T28	1		T168	1		T92	34
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T63	11		T276	1		T142	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T17	5		T217	1		T237	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T1	100		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T32	8		T247	9		T258	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T42	2		T25	9		T31	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T63	13		T87	11		T244	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T31	9		T127	11		T49	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	3		T203	9		T18	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T171	2		T144	4		T244	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T37	2		T31	15		T89	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T52	26		T45	11		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	3		T34	1		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	2		T11	7		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	4		T44	3		T88	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T42	13		T88	9		T221	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	5		T203	3		T133	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T227	2		T278	12		T174	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T39	1		T168	8		T128	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T26	1		T221	7		T146	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T55	13		T204	13		T230	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	10		T17	2		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T28	2		T168	7		T92	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T63	11		T142	12		T147	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T17	3		T217	5		T237	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	2		T15	1		T29	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T247	14		T268	12		T277	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T11	1		T195	1		T48	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T28	1		T17	5		T92	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T48	1		T160	1		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T245	1		T190	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T42	1		T25	11		T29	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T32	8		T83	1		T63	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	8		T31	19		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T194	18		T15	8		T127	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T171	1		T135	1		T247	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T51	14		T37	3		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T28	1		T29	10		T195	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T26	4		T31	14		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1724	1			T2	49		T6	40		T7	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	3		T5	8		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T3	5		T16	7		T82	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T9	1		T39	6		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	1		T11	1		T42	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T39	3		T168	1		T49	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T26	1		T48	2		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T130	1		T230	3		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T5	22		T32	3		T82	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T168	1		T55	13		T92	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T1	100		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T11	10		T48	1		T87	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T28	2		T17	3		T92	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T160	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T190	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T42	2		T25	9		T29	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T63	13		T247	14		T268	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T31	27		T127	11		T49	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	3		T87	11		T203	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T171	2		T144	4		T244	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T37	2		T89	12		T249	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T29	10		T167	10		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T26	3		T31	15		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T11	7		T52	26		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	4		T44	3		T88	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	2		T16	2		T88	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T39	5		T133	11		T231	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T42	13		T149	6		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T39	1		T168	8		T128	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T26	1		T221	7		T213	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T230	7		T306	10		T193	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T63	11		T17	2		T89	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T168	7		T55	13		T92	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T42	3		T25	10		T31	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T83	1		T63	14		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	1		T31	10		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T194	1		T15	9		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T195	1		T171	3		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T51	1		T37	3		T31	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T2	3		T6	3		T7	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T42	1		T26	6		T63	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T3	3		T9	1		T11	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	5		T5	1		T44	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	1		T11	1		T42	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	1		T39	6		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T82	1		T135	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T39	3		T130	1		T168	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T26	2		T32	1		T48	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T55	14		T129	1		T204	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	1		T11	11		T82	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T28	3		T168	8		T92	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T63	12		T276	1		T142	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T17	6		T217	6		T237	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16953	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T32	1		T247	15		T258	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T25	10		T31	10		T148	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T63	8		T87	9		T196	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	7		T31	7		T127	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T194	17		T15	2		T127	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T144	1		T172	14		T244	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T51	13		T37	2		T31	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T2	46		T6	37		T7	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T26	1		T253	1		T174	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	4		T37	1		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	2		T5	7		T44	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T42	13		T82	8		T88	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T39	5		T129	10		T145	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T82	16		T261	7		T256	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T39	1		T128	2		T173	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T32	2		T146	14		T213	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T55	12		T129	4		T204	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	21		T82	11		T17	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T92	32		T128	2		T159	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T63	10		T142	11		T147	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T17	2		T147	11		T241	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T29	10		T49	5		T136	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T32	7		T247	8		T258	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T11	11		T195	1		T48	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T28	3		T17	6		T92	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T48	1		T160	11		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T245	1		T190	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T42	3		T25	10		T29	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T32	1		T83	1		T63	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	1		T31	29		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T194	1		T15	9		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T171	3		T135	1		T247	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T51	1		T37	3		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T28	1		T29	11		T195	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T26	6		T31	16		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T2	3		T6	3		T7	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T3	5		T5	1		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	3		T16	7		T82	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	1		T39	6		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	1		T11	1		T42	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T39	3		T168	9		T49	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T26	2		T48	2		T221	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T130	1		T230	8		T306	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	1		T32	1		T82	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T168	8		T55	14		T92	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T48	2		T87	3		T142	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T17	2		T92	16		T252	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T307	18		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T190	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T25	10		T29	10		T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T32	7		T63	8		T196	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	7		T31	17		T127	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T194	17		T15	2		T127	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T144	1		T200	11		T244	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T51	13		T37	2		T89	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T29	9		T167	11		T199	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T26	1		T31	13		T128	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T2	46		T6	37		T7	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	2		T5	7		T44	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	4		T16	2		T82	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T39	5		T129	10		T145	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T42	13		T82	16		T256	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T39	1		T128	2		T174	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T261	7		T213	10		T247	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T230	2		T193	12		T273	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	21		T32	2		T82	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T55	12		T92	16		T128	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28