Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T1

100

T2

49

T3

30

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22340

1

T1

100

T2

49

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3872

1

T3

7

T5

22

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20141

1

T1

100

T3

30

T4

20

auto[1]

6071

1

T2

49

T5

30

T6

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22209

1

T1

100

T2

49

T3

22

auto[1]

4003

1

T3

8

T11

17

T52

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	315	1			T51	14		T195	1		T49	19
values[0]	53	1			T17	5		T291	1		T293	1
values[1]	763	1			T32	8		T84	1		T63	22
values[2]	632	1			T5	22		T9	1		T39	11
values[3]	827	1			T5	8		T9	1		T42	27
values[4]	3219	1			T2	49		T6	40		T7	28
values[5]	676	1			T29	33		T31	29		T130	1
values[6]	611	1			T16	9		T83	1		T63	26
values[7]	778	1			T3	7		T42	1		T84	1
values[8]	596	1			T11	11		T37	5		T39	4
values[9]	831	1			T3	7		T9	1		T11	1
minimum	16911	1			T1	100		T3	16		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	639	1			T9	1		T32	8		T84	1
values[1]	761	1			T5	22		T39	11		T82	17
values[2]	790	1			T5	8		T9	1		T11	8
values[3]	3139	1			T2	49		T6	40		T7	28
values[4]	701	1			T16	9		T29	20		T31	29
values[5]	675	1			T83	1		T84	1		T63	26
values[6]	678	1			T3	7		T11	11		T37	5
values[7]	563	1			T12	8		T39	4		T26	9
values[8]	843	1			T3	7		T9	1		T11	1
values[9]	202	1			T49	19		T146	17		T222	29
minimum	17221	1			T1	100		T3	16		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

4357

1

T2

46

T3

6

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	1		T32	8		T84	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T63	9		T136	16		T19	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T39	6		T82	17		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T5	22		T17	5		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	8		T9	1		T82	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	1		T42	14		T44	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1732	1			T2	49		T6	40		T7	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T194	18		T25	11		T29	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T16	7		T31	14		T127	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T29	10		T82	12		T148	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T83	1		T63	11		T92	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T84	1		T63	1		T127	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	3		T42	1		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	3		T11	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	8		T39	3		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T26	5		T49	6		T145	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	5		T11	1		T51	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T9	1		T15	8		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T49	7		T146	15		T222	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T244	20		T278	12		T286	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16872	1			T1	100		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T17	3		T204	5		T137	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T168	7		T207	13		T263	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T63	13		T19	2		T213	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T39	5		T242	8		T227	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T17	3		T88	21		T89	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T88	2		T171	2		T247	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	7		T42	13		T44	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T52	26		T45	11		T248	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T25	9		T29	2		T31	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T16	2		T31	15		T127	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T29	10		T148	16		T128	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T63	11		T92	6		T246	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T63	3		T204	13		T247	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	2		T197	10		T128	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	4		T11	10		T89	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T39	1		T34	1		T168	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T26	4		T133	11		T238	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	2		T37	1		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T15	3		T28	2		T48	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T49	12		T146	2		T222	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T244	13		T278	12		T308	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	2		T15	1		T17	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T17	2		T204	7		T137	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T51	14		T195	1		T49	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T283	1		T21	1		T244	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T102	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T17	3		T291	1		T293	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T32	8		T84	1		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T63	9		T19	7		T213	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	1		T39	6		T82	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	22		T131	1		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	8		T9	1		T82	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T42	14		T44	10		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1746	1			T2	49		T6	40		T7	28
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	1		T194	18		T25	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T31	14		T127	3		T48	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T29	21		T130	1		T50	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T16	7		T83	1		T63	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T63	1		T127	9		T148	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T42	1		T197	1		T146	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	3		T84	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	3		T39	3		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	1		T26	5		T49	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	5		T11	1		T12	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T9	1		T15	8		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T1	100		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T49	12		T146	2		T207	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T244	13		T278	12		T160	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T102	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T17	2		T269	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T168	7		T221	2		T230	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T63	13		T19	2		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T39	5		T227	2		T207	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T88	21		T89	12		T128	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T88	2		T171	2		T242	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T42	13		T44	3		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T52	26		T45	11		T248	30
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	7		T25	9		T31	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T31	15		T127	11		T92	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T29	12		T50	1		T20	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T16	2		T63	11		T92	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T63	3		T148	16		T128	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T197	10		T146	7		T246	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	4		T89	12		T213	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	2		T39	1		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	10		T26	4		T133	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	2		T37	1		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	3		T28	2		T48	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T9	1		T32	1		T84	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T63	14		T136	1		T19	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	6		T82	1		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T5	1		T17	6		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	1		T9	1		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T11	8		T42	14		T44	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T2	3		T6	3		T7	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T194	1		T25	10		T29	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T16	7		T31	16		T127	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T29	11		T82	1		T148	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T83	1		T63	12		T92	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T84	1		T63	4		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T37	3		T42	1		T197	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	5		T11	11		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	1		T39	3		T34	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T26	8		T49	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	3		T11	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T9	1		T15	9		T28	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T49	16		T146	3		T222	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T244	14		T278	13		T286	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16985	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T17	3		T204	8		T137	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T32	7		T207	14		T278	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T63	8		T136	15		T19	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T39	5		T82	16		T159	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	21		T17	2		T88	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	7		T82	8		T88	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T42	13		T44	9		T127	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T2	46		T6	37		T7	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T194	17		T25	10		T29	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T16	2		T31	13		T127	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T29	9		T82	11		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T63	10		T92	2		T192	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T127	8		T136	6		T204	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T37	2		T128	2		T146	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	2		T89	14		T213	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T12	7		T39	1		T87	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T26	1		T49	5		T145	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	4		T51	13		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T15	2		T48	2		T129	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T49	3		T146	14		T222	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T244	19		T278	11		T308	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T196	15		T230	11		T173	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T17	2		T204	4		T249	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T51	1		T195	1		T49	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T283	1		T21	1		T244	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T102	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T17	3		T291	1		T293	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T32	1		T84	1		T168	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T63	14		T19	7		T213	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T9	1		T39	6		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	1		T131	1		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T9	1		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T42	14		T44	4		T17	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T2	3		T6	3		T7	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	8		T194	1		T25	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T31	16		T127	12		T48	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T29	14		T130	1		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	7		T83	1		T63	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T63	4		T127	1		T148	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T42	1		T197	11		T146	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	5		T84	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T37	3		T39	3		T34	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	11		T26	8		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	3		T11	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	1		T15	9		T28	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T51	13		T49	3		T146	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T244	19		T278	11		T309	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T102	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T17	2		T269	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T32	7		T196	15		T230	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T63	8		T19	2		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T39	5		T82	16		T159	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	21		T88	10		T89	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	7		T82	8		T88	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T42	13		T44	9		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T2	46		T6	37		T7	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T194	17		T25	10		T31	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T31	13		T127	2		T92	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T29	19		T50	2		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T16	2		T63	10		T92	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T127	8		T148	9		T128	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T146	8		T243	8		T192	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	2		T89	14		T136	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T37	2		T39	1		T92	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T26	1		T49	5		T145	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	4		T12	7		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	2		T48	2		T129	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28