Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T1

100

T2

49

T3

30

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20301

1

T1

100

T3

23

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

5911

1

T2

49

T3

7

T5

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20191

1

T1

100

T3

23

T4

20

auto[1]

6021

1

T2

49

T3

7

T6

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22209

1

T1

100

T2

49

T3

22

auto[1]

4003

1

T3

8

T11

17

T52

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	165	1			T50	5		T222	29		T203	10
values[0]	24	1			T163	7		T209	5		T251	11
values[1]	601	1			T42	1		T44	13		T16	9
values[2]	594	1			T167	13		T168	9		T55	1
values[3]	850	1			T3	7		T37	5		T42	3
values[4]	669	1			T39	11		T29	20		T82	9
values[5]	742	1			T5	8		T9	1		T12	8
values[6]	745	1			T11	8		T25	20		T28	1
values[7]	665	1			T9	1		T28	3		T32	8
values[8]	708	1			T9	1		T11	1		T51	14
values[9]	3538	1			T2	49		T3	7		T5	22
minimum	16911	1			T1	100		T3	16		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	681	1			T42	1		T44	13		T16	9
values[1]	3141	1			T2	49		T6	40		T7	28
values[2]	711	1			T3	7		T37	5		T15	11
values[3]	595	1			T9	1		T37	4		T39	11
values[4]	944	1			T5	8		T12	8		T31	17
values[5]	592	1			T11	8		T25	20		T28	1
values[6]	603	1			T9	2		T11	1		T28	3
values[7]	727	1			T51	14		T42	27		T194	18
values[8]	1081	1			T3	7		T5	22		T11	11
values[9]	103	1			T26	7		T222	29		T230	6
minimum	17034	1			T1	100		T3	16		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

4357

1

T2

46

T3

6

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T44	10		T32	3		T195	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T42	1		T16	7		T82	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T42	1		T167	3		T55	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1744	1			T2	49		T6	40		T7	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T37	3		T26	1		T92	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	5		T15	8		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T195	1		T168	1		T87	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	1		T37	3		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T5	8		T12	8		T31	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T84	1		T63	21		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T25	11		T171	1		T249	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	1		T28	1		T31	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	2		T28	1		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	1		T130	1		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T42	14		T194	18		T127	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T51	14		T84	1		T63	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T3	3		T11	1		T31	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T5	22		T39	3		T29	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T222	14		T230	5		T310	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T26	4		T147	12		T311	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	100		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T133	1		T144	2		T21	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T44	3		T128	11		T213	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T16	2		T220	15		T246	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T42	2		T167	10		T247	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	974	1			T52	26		T45	11		T248	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T37	2		T26	1		T92	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	2		T15	3		T197	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T168	7		T87	5		T88	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T37	1		T39	5		T29	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T31	9		T127	10		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T63	24		T89	12		T92	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T25	9		T249	5		T270	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	7		T31	15		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T28	2		T87	11		T221	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T137	11		T20	3		T250	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T42	13		T127	11		T55	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T63	3		T92	7		T221	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T3	4		T11	10		T31	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T39	1		T29	2		T148	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T222	15		T230	1		T312	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T26	3		T147	11		T272	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	2		T15	1		T17	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T133	11		T144	4		T140	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T50	4		T222	14		T205	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T203	1		T306	1		T313	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T251	4		T314	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T163	7		T209	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T44	10		T32	3		T195	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T42	1		T16	7		T82	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T167	3		T55	1		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T168	1		T49	7		T129	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T37	3		T42	1		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	5		T15	8		T84	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T195	1		T168	1		T88	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T39	6		T29	10		T82	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	8		T12	8		T31	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	1		T37	3		T84	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T25	11		T127	14		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	1		T28	1		T31	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	1		T28	1		T87	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T32	8		T130	1		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	1		T42	14		T194	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	1		T51	14		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T3	3		T11	1		T31	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1827	1			T2	49		T5	22		T6	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T1	100		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T50	1		T222	15		T205	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T203	9		T306	10		T313	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T251	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T209	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T44	3		T213	15		T208	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T16	2		T133	11		T144	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T167	10		T128	11		T207	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T168	8		T49	12		T144	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T37	2		T42	2		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	2		T15	3		T197	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T168	7		T88	9		T207	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T39	5		T29	10		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T31	9		T148	9		T87	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T37	1		T247	14		T253	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T25	9		T127	10		T204	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	7		T31	15		T63	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T28	2		T87	11		T221	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T146	2		T137	11		T315	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T42	13		T127	11		T88	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T63	3		T92	7		T208	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T3	4		T11	10		T31	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1066	1			T52	26		T39	1		T45	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T44	4		T32	1		T195	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T42	1		T16	7		T82	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T42	3		T167	11		T55	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1318	1			T2	3		T6	3		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T37	3		T26	2		T92	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	3		T15	9		T197	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T195	1		T168	8		T87	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	1		T37	3		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	1		T12	1		T31	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T84	1		T63	27		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T25	10		T171	1		T249	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	8		T28	1		T31	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	2		T28	3		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	1		T130	1		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T42	14		T194	1		T127	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T51	1		T84	1		T63	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T3	5		T11	11		T31	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T5	1		T39	3		T29	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T222	16		T230	2		T310	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T26	6		T147	12		T311	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16960	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T133	12		T144	5		T21	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T44	9		T32	2		T128	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T16	2		T82	16		T159	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T167	2		T49	5		T196	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1400	1			T2	46		T6	37		T7	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T37	2		T92	16		T128	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	4		T15	2		T127	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T87	3		T88	12		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T37	1		T39	5		T29	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	7		T12	7		T31	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T63	18		T89	14		T92	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T25	10		T249	9		T243	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T31	13		T32	7		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T87	9		T242	2		T230	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T20	3		T262	19		T316	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T42	13		T194	17		T127	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T51	13		T92	16		T136	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T3	2		T31	10		T82	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	21		T39	1		T29	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T222	13		T230	4		T312	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T26	1		T147	11		T272	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T147	2		T317	2		T251	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T144	1		T243	7		T140	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T50	3		T222	16		T205	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T203	10		T306	11		T313	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T251	8		T314	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T163	1		T209	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T44	4		T32	1		T195	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T42	1		T16	7		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T167	11		T55	1		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T168	9		T49	16		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T37	3		T42	3		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	3		T15	9		T84	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T195	1		T168	8		T88	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T39	6		T29	11		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T12	1		T31	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	1		T37	3		T84	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T25	10		T127	11		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T11	8		T28	1		T31	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	1		T28	3		T87	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T32	1		T130	1		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	1		T42	14		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	1		T51	1		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T3	5		T11	11		T31	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1434	1			T2	3		T5	1		T6	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T50	2		T222	13		T209	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T313	16		T152	11		T309	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T251	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T163	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T44	9		T32	2		T213	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	2		T82	16		T159	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T167	2		T49	5		T128	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T49	3		T129	15		T199	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T37	2		T92	16		T128	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	4		T15	2		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T88	12		T129	10		T207	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T39	5		T29	9		T82	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	7		T12	7		T31	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	1		T247	16		T172	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T25	10		T127	13		T204	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T31	13		T63	18		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T87	9		T242	2		T249	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T32	7		T146	14		T315	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T42	13		T194	17		T127	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T51	13		T92	16		T136	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T3	2		T31	10		T82	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1459	1			T2	46		T5	21		T6	37

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28