Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	1		T26	6		T31	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T29	3		T17	6		T167	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T2	3		T6	3		T7	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T9	1		T12	1		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	1		T42	1		T171	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T148	17		T221	8		T227	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T42	14		T28	3		T63	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T37	3		T39	6		T29	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T83	1		T63	1		T197	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T39	3		T82	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	1		T44	4		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T48	2		T49	2		T92	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T3	5		T5	1		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	9		T16	7		T128	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T51	1		T31	10		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	3		T11	8		T25	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T9	1		T32	1		T17	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T194	1		T84	1		T215	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	11		T129	1		T203	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T190	4		T228	1		T229	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16926	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T132	1		T141	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T26	1		T31	13		T204	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T29	10		T17	2		T167	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T2	46		T6	37		T7	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	7		T82	11		T127	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	21		T50	2		T172	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T148	9		T236	11		T190	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T42	13		T48	2		T88	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T37	1		T39	5		T29	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T55	12		T214	2		T149	29
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T39	1		T82	16		T167	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T44	9		T32	7		T63	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T92	2		T146	14		T18	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	2		T5	7		T49	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T15	2		T16	2		T128	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T51	13		T31	7		T63	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	4		T25	10		T127	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T32	2		T17	2		T92	32
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T194	17		T19	2		T199	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T129	15		T231	13		T243	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T190	2		T229	11		T96	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T162	5		T232	1		T233	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T88	22		T173	1		T211	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	1		T26	6		T31	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T29	3		T17	6		T167	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T2	3		T6	3		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	1		T127	1		T168	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	1		T37	3		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	1		T82	1		T221	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T42	14		T28	3		T63	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T37	3		T39	6		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T44	4		T63	1		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T39	3		T31	19		T82	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T26	2		T32	1		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T82	1		T49	2		T92	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	1		T11	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T15	9		T16	7		T48	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T3	5		T51	1		T31	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	3		T11	8		T25	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T9	1		T11	11		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T194	1		T89	13		T215	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T232	6		T233	11		T235	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T88	10		T173	12		T211	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T26	1		T31	13		T204	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T29	10		T17	2		T167	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T2	46		T6	37		T7	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	7		T127	8		T196	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T5	21		T37	2		T48	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T82	11		T236	11		T190	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T42	13		T88	2		T149	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T37	1		T39	5		T29	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T44	9		T149	9		T244	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T39	1		T31	10		T82	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	7		T63	10		T127	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T82	16		T92	2		T18	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	7		T145	14		T136	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	2		T16	2		T128	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	2		T51	13		T31	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	4		T25	10		T127	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T32	2		T17	2		T92	32
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T194	17		T89	14		T242	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28