Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T1

100

T2

49

T3

30

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20315

1

T1

100

T3

23

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

5897

1

T2

49

T3

7

T5

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

100

T3

23

T4

20

auto[1]

5998

1

T2

49

T3

7

T6

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22209

1

T1

100

T2

49

T3

22

auto[1]

4003

1

T3

8

T11

17

T52

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T245	3		-	-		-	-
values[0]	113	1			T16	9		T243	8		T193	15
values[1]	496	1			T42	1		T44	13		T32	3
values[2]	629	1			T15	11		T82	17		T167	13
values[3]	818	1			T3	7		T37	5		T42	3
values[4]	704	1			T39	11		T29	20		T82	9
values[5]	744	1			T5	8		T9	1		T12	8
values[6]	767	1			T11	8		T25	20		T28	1
values[7]	671	1			T9	1		T28	3		T32	8
values[8]	631	1			T9	1		T11	1		T51	14
values[9]	3725	1			T2	49		T3	7		T5	22
minimum	16911	1			T1	100		T3	16		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	791	1			T42	1		T44	13		T16	9
values[1]	3197	1			T2	49		T6	40		T7	28
values[2]	678	1			T3	7		T37	5		T15	11
values[3]	635	1			T9	1		T37	4		T39	11
values[4]	861	1			T5	8		T12	8		T31	17
values[5]	627	1			T11	8		T25	20		T28	1
values[6]	633	1			T9	2		T11	1		T194	18
values[7]	684	1			T3	7		T11	11		T51	14
values[8]	973	1			T5	22		T39	4		T31	29
values[9]	216	1			T26	7		T222	29		T230	23
minimum	16917	1			T1	100		T3	16		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

4357

1

T2

46

T3

6

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T32	3		T195	1		T128	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T42	1		T44	10		T16	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T42	1		T167	3		T55	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1777	1			T2	49		T6	40		T7	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T37	3		T26	1		T92	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	5		T15	8		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T195	1		T168	1		T87	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	1		T37	3		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T5	8		T12	8		T31	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T63	12		T131	1		T89	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T25	11		T171	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	1		T28	1		T31	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	2		T194	18		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	1		T215	1		T172	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	3		T11	1		T42	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T51	14		T29	11		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T31	11		T82	12		T89	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T5	22		T39	3		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T222	14		T230	17		T205	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T26	4		T245	2		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T1	100		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T246	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T128	11		T213	15		T208	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T44	3		T16	2		T133	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T42	2		T167	10		T247	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	979	1			T52	26		T45	11		T248	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T37	2		T26	1		T92	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	2		T15	3		T197	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T168	7		T87	5		T88	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T37	1		T39	5		T29	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T31	9		T127	10		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T63	11		T89	12		T92	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T25	9		T137	11		T249	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	7		T31	15		T63	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T28	2		T87	11		T88	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T20	3		T244	2		T250	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	4		T11	10		T42	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T29	2		T63	3		T208	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T31	18		T89	12		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T39	1		T148	16		T92	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T222	15		T230	6		T205	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T26	3		T245	1		T217	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T246	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T245	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T147	3		T218	1		T251	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T16	7		T243	8		T193	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T32	3		T195	1		T213	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T42	1		T44	10		T159	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T167	3		T55	1		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	8		T82	17		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T37	3		T42	1		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	5		T84	1		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T195	1		T168	1		T88	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T39	6		T29	10		T82	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	8		T12	8		T31	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	1		T37	3		T84	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T25	11		T127	14		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	1		T28	1		T31	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	1		T28	1		T87	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T32	8		T130	2		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T42	14		T194	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	1		T51	14		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	398	1			T3	3		T11	1		T31	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1879	1			T2	49		T5	22		T6	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T1	100		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T147	9		T218	4		T251	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T16	2		T193	2		T229	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T213	15		T208	2		T252	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T44	3		T133	11		T144	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T167	10		T128	11		T207	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T15	3		T168	8		T49	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T37	2		T42	2		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	2		T197	10		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T168	7		T88	9		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T39	5		T29	10		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T31	9		T148	9		T87	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T37	1		T247	14		T253	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T25	9		T127	10		T221	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	7		T31	15		T63	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T28	2		T87	11		T88	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T146	2		T137	11		T244	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T42	13		T127	11		T88	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T63	3		T92	7		T208	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T3	4		T11	10		T31	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1115	1			T52	26		T39	1		T45	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T32	1		T195	1		T128	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T42	1		T44	4		T16	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T42	3		T167	11		T55	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1331	1			T2	3		T6	3		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	3		T26	2		T92	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	3		T15	9		T197	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T195	1		T168	8		T87	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	1		T37	3		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	1		T12	1		T31	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T63	13		T131	1		T89	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T25	10		T171	1		T137	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	8		T28	1		T31	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T9	2		T194	1		T28	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	1		T215	1		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	5		T11	11		T42	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T51	1		T29	3		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T31	19		T82	1		T89	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T5	1		T39	3		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T222	16		T230	8		T205	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T26	6		T245	2		T217	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T246	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T32	2		T128	12		T213	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T44	9		T16	2		T82	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T167	2		T49	5		T196	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1425	1			T2	46		T6	37		T7	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T37	2		T92	16		T128	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	4		T15	2		T127	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T87	3		T88	12		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T37	1		T39	5		T29	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	7		T12	7		T31	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T63	10		T89	14		T92	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T25	10		T249	9		T243	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T31	13		T32	7		T63	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T194	17		T87	9		T88	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T172	14		T20	3		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	2		T42	13		T127	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T51	13		T29	10		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T31	10		T82	11		T89	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	21		T39	1		T148	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T222	13		T230	15		T209	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T26	1		T245	1		T147	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T245	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T147	10		T218	5		T251	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T16	7		T243	1		T193	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T32	1		T195	1		T213	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T42	1		T44	4		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T167	11		T55	1		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	9		T82	1		T168	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T37	3		T42	3		T26	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	3		T84	1		T197	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T195	1		T168	8		T88	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T39	6		T29	11		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	1		T12	1		T31	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	1		T37	3		T84	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T25	10		T127	11		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	8		T28	1		T31	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T28	3		T87	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T32	1		T130	2		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	1		T42	14		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T51	1		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	397	1			T3	5		T11	11		T31	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1489	1			T2	3		T5	1		T6	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T147	2		T251	3		T254	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T16	2		T243	7		T193	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T32	2		T213	16		T208	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T44	9		T159	17		T145	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T167	2		T49	5		T128	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T15	2		T82	16		T49	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T37	2		T92	16		T128	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	4		T17	2		T127	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T88	12		T129	10		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T39	5		T29	9		T82	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	7		T12	7		T31	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T37	1		T247	16		T172	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T25	10		T127	13		T204	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T31	13		T63	18		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T87	9		T88	10		T242	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T32	7		T146	14		T244	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T42	13		T194	17		T127	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T51	13		T92	16		T136	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T3	2		T31	10		T82	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1505	1			T2	46		T5	21		T6	37

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28