Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T1

100

T2

49

T3

30

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22877

1

T1

100

T2

49

T3

30

auto[ADC_CTRL_FILTER_COND_OUT]

3335

1

T9

2

T11

20

T37

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19685

1

T1

97

T3

23

T4

20

auto[1]

6527

1

T1

3

T2

49

T3

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22209

1

T1

100

T2

49

T3

22

auto[1]

4003

1

T3

8

T11

17

T52

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	417	1			T1	3		T10	1		T53	4
values[0]	29	1			T48	2		T19	9		T255	18
values[1]	690	1			T9	1		T11	11		T39	11
values[2]	3054	1			T2	49		T6	40		T7	28
values[3]	709	1			T197	11		T127	24		T168	9
values[4]	760	1			T3	7		T9	1		T28	3
values[5]	768	1			T44	13		T26	2		T31	29
values[6]	691	1			T42	3		T92	24		T129	11
values[7]	734	1			T11	1		T42	1		T15	11
values[8]	575	1			T5	22		T39	4		T131	1
values[9]	1288	1			T3	7		T5	8		T9	1
minimum	16497	1			T1	97		T3	16		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	893	1			T11	11		T37	5		T39	11
values[1]	3087	1			T2	49		T6	40		T7	28
values[2]	686	1			T3	7		T9	1		T32	8
values[3]	769	1			T28	3		T31	29		T82	17
values[4]	708	1			T44	13		T26	2		T84	1
values[5]	739	1			T11	1		T16	9		T83	1
values[6]	701	1			T42	4		T39	4		T15	11
values[7]	653	1			T3	7		T5	22		T25	20
values[8]	841	1			T5	8		T9	1		T11	8
values[9]	206	1			T82	9		T55	26		T49	2
minimum	16929	1			T1	100		T3	16		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

4357

1

T2

46

T3

6

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T194	18		T63	9		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	1		T37	3		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1797	1			T2	49		T6	40		T7	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	1		T28	1		T82	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	3		T9	1		T197	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T32	8		T148	10		T87	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T28	1		T31	14		T84	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T82	17		T55	1		T50	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T44	10		T84	1		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T26	1		T87	4		T199	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T171	1		T129	11		T247	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	1		T16	7		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T42	1		T15	8		T84	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T42	1		T39	3		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	5		T5	22		T25	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T32	3		T167	3		T168	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T5	8		T51	14		T29	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T9	1		T11	1		T37	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T55	13		T128	3		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T82	9		T49	2		T256	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16780	1			T1	100		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T223	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T63	13		T203	9		T204	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	10		T37	2		T39	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T52	26		T42	13		T45	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T128	11		T146	2		T204	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	4		T197	10		T17	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T148	16		T87	11		T222	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T28	2		T31	15		T167	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T50	1		T208	5		T253	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T44	3		T171	2		T247	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T26	1		T87	5		T231	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T247	11		T149	6		T230	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T16	2		T92	7		T149	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T42	2		T15	3		T221	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	1		T127	11		T213	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T3	2		T25	9		T148	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T167	10		T168	7		T128	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T29	2		T88	9		T242	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	7		T37	1		T26	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T55	13		T128	7		T221	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T257	5		T141	13		T33	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	2		T15	1		T17	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	415	1			T1	3		T10	1		T53	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T49	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T48	2		T255	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T19	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T130	2		T17	3		T203	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	1		T11	1		T39	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1787	1			T2	49		T6	40		T7	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T37	3		T28	1		T82	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T197	1		T127	14		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T148	10		T128	13		T222	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	3		T9	1		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T32	8		T82	17		T87	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T44	10		T31	14		T84	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T26	1		T83	1		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T42	1		T129	11		T258	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T92	17		T247	1		T259	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	8		T84	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	1		T42	1		T16	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	22		T131	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T39	3		T49	6		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	416	1			T3	5		T5	8		T51	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T9	1		T11	1		T37	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16361	1			T1	97		T3	14		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T255	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T19	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T17	2		T203	9		T219	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	10		T39	5		T31	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T52	26		T42	13		T45	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T37	2		T34	1		T146	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T197	10		T127	10		T168	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T148	16		T128	11		T222	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	4		T28	2		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T87	16		T50	1		T207	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T44	3		T31	15		T88	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T26	1		T231	24		T253	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	2		T149	6		T230	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T92	7		T259	11		T260	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	3		T247	11		T220	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T16	2		T127	11		T213	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T148	9		T221	7		T252	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T39	1		T247	14		T35	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T3	2		T25	9		T29	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T11	7		T37	1		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T194	1		T63	14		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T11	11		T37	3		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T2	3		T6	3		T7	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	1		T28	1		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	5		T9	1		T197	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T32	1		T148	17		T87	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T28	3		T31	16		T84	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T82	1		T55	1		T50	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T44	4		T84	1		T171	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T26	2		T87	6		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T171	1		T129	1		T247	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	1		T16	7		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T42	3		T15	9		T84	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T42	1		T39	3		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	3		T5	1		T25	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T32	1		T167	11		T168	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	1		T51	1		T29	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	1		T11	8		T37	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T55	14		T128	8		T221	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T82	1		T49	2		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16916	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T223	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T194	17		T63	8		T261	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T37	2		T39	5		T31	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T2	46		T6	37		T7	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T82	11		T128	12		T146	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	2		T17	2		T127	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T32	7		T148	9		T87	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T31	13		T167	11		T49	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T82	16		T50	2		T145	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T44	9		T247	16		T144	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T87	3		T199	3		T231	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T129	10		T247	11		T258	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	2		T92	16		T129	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T15	2		T129	4		T193	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T39	1		T127	2		T213	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	4		T5	21		T25	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T32	2		T167	2		T49	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	7		T51	13		T29	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T37	1		T26	1		T29	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T55	12		T128	2		T144	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T82	8		T256	9		T150	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T262	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T223	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	415	1			T1	3		T10	1		T53	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T49	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T48	2		T255	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T19	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T130	2		T17	3		T203	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	1		T11	11		T39	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T2	3		T6	3		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T37	3		T28	1		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T197	11		T127	11		T168	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T148	17		T128	12		T222	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	5		T9	1		T28	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T32	1		T82	1		T87	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T44	4		T31	16		T84	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T26	2		T83	1		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T42	3		T129	1		T258	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T92	8		T247	1		T259	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	9		T84	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	1		T42	1		T16	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	1		T131	1		T148	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T39	3		T49	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T3	3		T5	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T9	1		T11	8		T37	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16497	1			T1	97		T3	16		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T255	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T19	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T17	2		T261	7		T207	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T39	5		T31	10		T63	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T2	46		T6	37		T7	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T37	2		T82	11		T146	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T127	13		T88	10		T92	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T148	9		T128	12		T222	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	2		T17	2		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T32	7		T82	16		T87	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T44	9		T31	13		T88	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T145	14		T172	14		T231	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T129	10		T258	2		T149	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T92	16		T259	10		T263	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	2		T129	4		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T16	2		T127	2		T129	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T5	21		T193	12		T264	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T39	1		T49	5		T247	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T3	4		T5	7		T51	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T37	1		T26	1		T29	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28