Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T1

100

T2

49

T3

30

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22667

1

T1

100

T2

49

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3545

1

T3

7

T5

8

T9

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20002

1

T1

100

T3

23

T4

20

auto[1]

6210

1

T2

49

T3

7

T5

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22209

1

T1

100

T2

49

T3

22

auto[1]

4003

1

T3

8

T11

17

T52

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	213	1			T11	8		T195	1		T168	8
values[0]	36	1			T265	36		-	-		-	-
values[1]	713	1			T11	11		T42	27		T26	2
values[2]	801	1			T9	1		T31	29		T84	2
values[3]	809	1			T9	1		T25	20		T28	1
values[4]	523	1			T5	22		T39	4		T63	22
values[5]	931	1			T42	3		T194	18		T15	11
values[6]	624	1			T9	1		T51	14		T42	1
values[7]	844	1			T3	7		T37	9		T32	8
values[8]	2790	1			T2	49		T5	8		T6	40
values[9]	1017	1			T3	7		T11	1		T12	8
minimum	16911	1			T1	100		T3	16		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	761	1			T42	27		T26	2		T28	3
values[1]	841	1			T9	1		T29	13		T31	29
values[2]	633	1			T9	1		T25	20		T28	1
values[3]	626	1			T5	22		T39	4		T194	18
values[4]	844	1			T42	4		T16	9		T31	17
values[5]	722	1			T9	1		T51	14		T32	8
values[6]	3106	1			T2	49		T3	7		T6	40
values[7]	457	1			T5	8		T12	8		T39	11
values[8]	880	1			T3	7		T11	1		T44	13
values[9]	163	1			T11	8		T17	8		T167	22
minimum	17179	1			T1	100		T3	16		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

4357

1

T2

46

T3

6

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T42	14		T26	1		T195	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T28	1		T135	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	1		T29	11		T31	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T84	1		T55	13		T50	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T130	1		T131	1		T127	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	1		T25	11		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	22		T26	4		T82	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	3		T194	18		T15	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T42	2		T31	8		T159	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T16	7		T148	10		T88	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T32	8		T88	3		T89	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	1		T51	14		T49	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1736	1			T2	49		T3	5		T6	40
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T37	6		T82	9		T127	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T39	6		T83	1		T63	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	8		T12	8		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	1		T44	10		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T3	3		T31	14		T82	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T11	1		T17	5		T167	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T168	1		T266	1		T267	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16847	1			T1	100		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T34	1		T171	1		T203	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T42	13		T26	1		T87	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T28	2		T247	14		T35	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T29	2		T31	18		T63	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T55	13		T50	1		T204	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T48	1		T204	4		T268	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T25	9		T89	12		T207	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T26	3		T127	11		T221	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T39	1		T15	3		T63	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T42	2		T31	9		T222	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T16	2		T148	16		T88	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T88	2		T89	12		T92	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T49	12		T92	14		T149	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	944	1			T3	2		T52	26		T45	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T37	3		T127	10		T167	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T39	5		T63	13		T197	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T128	7		T203	3		T149	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T44	3		T29	10		T92	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	4		T31	15		T17	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T11	7		T17	3		T167	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T168	7		T267	2		T269	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	2		T11	10		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T34	1		T203	9		T253	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T11	1		T195	1		T174	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T168	1		T49	6		T208	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T265	16		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	1		T42	14		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T28	1		T34	1		T171	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	1		T31	11		T84	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T84	1		T50	4		T145	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T29	11		T131	1		T127	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	1		T25	11		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	22		T130	1		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T39	3		T63	11		T258	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T42	1		T26	4		T31	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T194	18		T15	8		T16	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T42	1		T89	15		T92	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	1		T51	14		T49	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	5		T32	8		T88	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T37	6		T127	14		T167	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T2	49		T6	40		T7	28
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	8		T82	9		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	1		T44	10		T29	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T3	3		T12	8		T31	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T1	100		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T11	7		T174	12		T236	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T168	7		T208	5		T270	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T265	20		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	10		T42	13		T26	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T28	2		T34	1		T203	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T31	18		T63	3		T137	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T50	1		T204	20		T247	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T29	2		T48	1		T204	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T25	9		T55	13		T89	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T221	7		T146	2		T220	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T39	1		T63	11		T252	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T42	2		T26	3		T31	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	3		T16	2		T148	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T89	12		T92	6		T19	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T49	12		T92	14		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	2		T88	2		T213	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T37	3		T127	10		T167	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T52	26		T39	5		T45	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T128	7		T149	9		T271	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T44	3		T29	10		T17	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	4		T31	15		T17	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T42	14		T26	2		T195	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T28	3		T135	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	1		T29	3		T31	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T84	1		T55	14		T50	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T130	1		T131	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	1		T25	10		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	1		T26	6		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T39	3		T194	1		T15	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T42	4		T31	10		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T16	7		T148	17		T88	32
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T32	1		T88	3		T89	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	1		T51	1		T49	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T2	3		T3	3		T6	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T37	6		T82	1		T127	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	6		T83	1		T63	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	1		T12	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	1		T44	4		T29	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	5		T31	16		T82	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T11	8		T17	6		T167	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T168	8		T266	1		T267	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16983	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T34	2		T171	1		T203	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T42	13		T87	9		T199	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T247	16		T258	2		T35	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T29	10		T31	10		T230	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T55	12		T50	2		T145	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T127	8		T48	2		T129	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T25	10		T89	8		T172	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	21		T26	1		T82	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	1		T194	17		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T31	7		T159	17		T196	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T16	2		T148	9		T88	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T32	7		T88	2		T89	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T51	13		T49	3		T92	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T2	46		T3	4		T6	37
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T37	3		T82	8		T127	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T39	5		T63	8		T87	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T5	7		T12	7		T128	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T44	9		T29	9		T92	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	2		T31	13		T82	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T17	2		T167	11		T174	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T267	1		T269	15		T272	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T173	12		T273	11		T265	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T136	15		T256	9		T253	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T11	8		T195	1		T174	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T168	8		T49	1		T208	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T265	21		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	11		T42	14		T26	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T28	3		T34	2		T171	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	1		T31	19		T84	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T84	1		T50	3		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T29	3		T131	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T9	1		T25	10		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T130	1		T221	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T39	3		T63	12		T258	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T42	3		T26	6		T31	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T194	1		T15	9		T16	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T42	1		T89	13		T92	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	1		T51	1		T49	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	3		T32	1		T88	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T37	6		T127	11		T167	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T2	3		T6	3		T7	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	1		T82	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T11	1		T44	4		T29	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T3	5		T12	1		T31	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T174	9		T236	16		T274	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T49	5		T208	7		T236	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T265	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T42	13		T87	9		T214	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T136	15		T258	2		T256	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T31	10		T199	15		T149	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T50	2		T145	14		T204	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T29	10		T127	8		T48	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T25	10		T55	12		T89	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	21		T146	14		T200	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T39	1		T63	10		T258	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T26	1		T31	7		T82	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T194	17		T15	2		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T89	14		T92	2		T159	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T51	13		T49	3		T92	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	4		T32	7		T88	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T37	3		T127	13		T167	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T2	46		T6	37		T7	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	7		T82	8		T128	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T44	9		T29	9		T17	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	2		T12	7		T31	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28