Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T1

100

T2

49

T3

30

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22745

1

T1

100

T2

49

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3467

1

T3

7

T9

1

T11

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20095

1

T1

100

T3

23

T4

20

auto[1]

6117

1

T2

49

T3

7

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22209

1

T1

100

T2

49

T3

22

auto[1]

4003

1

T3

8

T11

17

T52

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	350	1			T199	8		T213	5		T204	20
values[0]	41	1			T173	13		T141	14		T211	7
values[1]	840	1			T9	1		T26	7		T29	13
values[2]	2960	1			T2	49		T6	40		T7	28
values[3]	769	1			T5	22		T9	1		T37	5
values[4]	570	1			T37	4		T42	27		T39	11
values[5]	663	1			T39	4		T44	13		T28	3
values[6]	764	1			T26	2		T32	8		T82	17
values[7]	657	1			T5	8		T11	1		T15	11
values[8]	800	1			T3	14		T11	8		T51	14
values[9]	887	1			T9	1		T11	11		T194	18
minimum	16911	1			T1	100		T3	16		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	645	1			T9	1		T26	7		T29	13
values[1]	3054	1			T2	49		T6	40		T7	28
values[2]	653	1			T5	22		T42	1		T148	26
values[3]	591	1			T37	4		T42	27		T39	11
values[4]	743	1			T39	4		T44	13		T29	20
values[5]	701	1			T11	1		T26	2		T32	8
values[6]	747	1			T3	7		T5	8		T15	11
values[7]	673	1			T3	7		T11	8		T51	14
values[8]	926	1			T9	1		T11	11		T194	18
values[9]	231	1			T129	16		T203	4		T231	41
minimum	17248	1			T1	100		T3	16		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

4357

1

T2

46

T3

6

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	1		T26	4		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T29	11		T17	5		T167	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1767	1			T2	49		T6	40		T7	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	1		T12	8		T82	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	22		T42	1		T89	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T148	10		T221	1		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T42	14		T28	1		T63	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T37	3		T39	6		T31	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T44	10		T83	1		T63	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T39	3		T29	10		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	1		T26	1		T32	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T82	17		T48	2		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	3		T5	8		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T15	8		T16	7		T128	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T51	14		T31	8		T84	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	5		T11	1		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T9	1		T11	1		T32	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T194	18		T215	1		T19	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T129	16		T203	1		T231	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T190	3		T228	1		T229	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16823	1			T1	100		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T88	11		T215	1		T132	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T26	3		T204	13		T144	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T29	2		T17	3		T167	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T52	26		T37	2		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T168	7		T87	5		T221	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T89	12		T171	2		T50	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T148	16		T221	7		T227	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T42	13		T28	2		T63	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T37	1		T39	5		T31	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T44	3		T197	10		T55	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T39	1		T29	10		T167	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T26	1		T63	11		T127	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T92	6		T146	2		T203	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	4		T49	12		T213	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	3		T16	2		T128	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T31	9		T63	13		T168	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	2		T11	7		T25	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	10		T17	2		T148	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T19	2		T204	4		T137	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T203	3		T231	24		T263	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T190	3		T229	7		T96	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	2		T15	1		T31	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T88	21		T207	16		T138	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T213	3		T133	1		T231	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T199	8		T204	16		T245	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T173	13		T141	1		T211	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	1		T26	4		T31	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T29	11		T17	5		T88	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1712	1			T2	49		T6	40		T7	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	8		T82	12		T167	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T5	22		T37	3		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	1		T127	9		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	14		T63	1		T88	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T37	3		T39	6		T34	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T44	10		T28	1		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	3		T29	10		T31	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T26	1		T32	8		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T82	17		T49	2		T92	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	8		T11	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	8		T16	7		T48	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	3		T51	14		T31	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	5		T11	1		T25	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T9	1		T11	1		T32	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T194	18		T89	15		T215	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T1	100		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T213	2		T133	11		T231	24
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T204	4		T245	1		T192	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T141	13		T211	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T26	3		T31	15		T204	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T29	2		T17	3		T88	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T52	26		T42	2		T45	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T167	10		T168	7		T87	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T37	2		T48	1		T87	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T221	7		T236	4		T190	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T42	13		T63	3		T88	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T37	1		T39	5		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T44	3		T28	2		T149	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T39	1		T29	10		T31	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T26	1		T63	11		T197	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T92	6		T146	2		T203	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T268	12		T270	11		T273	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	3		T16	2		T128	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	4		T31	9		T63	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	2		T11	7		T25	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	10		T17	2		T148	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T89	12		T242	8		T19	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	1		T26	6		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T29	3		T17	6		T167	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T2	3		T6	3		T7	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	1		T12	1		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	1		T42	1		T89	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T148	17		T221	8		T227	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T42	14		T28	3		T63	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T37	3		T39	6		T31	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T44	4		T83	1		T63	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T39	3		T29	11		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	1		T26	2		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T82	1		T48	2		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	5		T5	1		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T15	9		T16	7		T128	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T51	1		T31	10		T84	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	3		T11	8		T25	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T9	1		T11	11		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T194	1		T215	1		T19	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T129	1		T203	4		T231	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T190	4		T228	1		T229	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16976	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T88	22		T215	1		T132	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T26	1		T204	15		T144	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	10		T17	2		T167	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T2	46		T6	37		T7	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	7		T82	11		T127	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	21		T89	8		T50	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T148	9		T236	11		T190	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T42	13		T48	2		T88	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T37	1		T39	5		T31	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T44	9		T55	12		T214	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	1		T29	9		T167	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T32	7		T63	10		T127	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T82	16		T92	2		T146	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	2		T5	7		T49	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T15	2		T16	2		T128	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T51	13		T31	7		T63	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	4		T25	10		T127	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T32	2		T17	2		T92	32
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T194	17		T19	2		T199	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T129	15		T231	13		T243	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T190	2		T229	11		T96	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T31	13		T257	6		T265	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T88	10		T207	12		T173	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T213	3		T133	12		T231	28
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T199	1		T204	5		T245	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T173	1		T141	14		T211	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	1		T26	6		T31	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T29	3		T17	6		T88	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T2	3		T6	3		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	1		T82	1		T167	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T37	3		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	1		T127	1		T221	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T42	14		T63	4		T88	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T37	3		T39	6		T34	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T44	4		T28	3		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T39	3		T29	11		T31	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T26	2		T32	1		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T82	1		T49	2		T92	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	1		T11	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	9		T16	7		T48	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T3	5		T51	1		T31	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	3		T11	8		T25	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T9	1		T11	11		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T194	1		T89	13		T215	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T213	2		T231	13		T256	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T199	7		T204	15		T245	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T173	12		T211	3		T99	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	1		T31	13		T204	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T29	10		T17	2		T88	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T2	46		T6	37		T7	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	7		T82	11		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T5	21		T37	2		T48	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T127	8		T236	11		T190	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T42	13		T88	2		T149	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T37	1		T39	5		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T44	9		T149	9		T244	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T39	1		T29	9		T31	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T32	7		T63	10		T127	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T82	16		T92	2		T146	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	7		T145	14		T136	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T15	2		T16	2		T128	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	2		T51	13		T31	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	4		T25	10		T127	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T32	2		T17	2		T92	32
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T194	17		T89	14		T242	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28