Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26212

1

T1

100

T2

49

T3

30

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22531

1

T1

100

T2

49

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3681

1

T3

7

T5

30

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19992

1

T1

100

T3

30

T4

20

auto[1]

6220

1

T2

49

T5

30

T6

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22209

1

T1

100

T2

49

T3

22

auto[1]

4003

1

T3

8

T11

17

T52

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T19	9		T280	1		T281	12
values[0]	84	1			T162	21		T241	23		T282	30
values[1]	696	1			T82	21		T84	1		T127	14
values[2]	597	1			T5	22		T9	1		T11	11
values[3]	738	1			T63	23		T195	1		T127	9
values[4]	578	1			T9	1		T11	9		T37	4
values[5]	3018	1			T2	49		T6	40		T7	28
values[6]	647	1			T3	7		T51	14		T37	5
values[7]	645	1			T9	1		T39	15		T194	18
values[8]	840	1			T5	8		T12	8		T42	3
values[9]	1436	1			T3	7		T42	27		T44	13
minimum	16911	1			T1	100		T3	16		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	881	1			T26	2		T82	21		T84	1
values[1]	706	1			T5	22		T9	1		T11	11
values[2]	730	1			T9	1		T31	29		T195	1
values[3]	2973	1			T2	49		T6	40		T7	28
values[4]	539	1			T29	13		T87	9		T215	2
values[5]	718	1			T3	7		T9	1		T51	14
values[6]	621	1			T194	18		T15	11		T26	7
values[7]	834	1			T5	8		T12	8		T42	3
values[8]	1092	1			T3	7		T42	27		T44	13
values[9]	177	1			T31	29		T136	7		T213	32
minimum	16941	1			T1	100		T3	16		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

4357

1

T2

46

T3

6

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T26	1		T82	21		T84	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T127	3		T49	9		T88	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	1		T11	1		T63	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	22		T63	1		T127	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	1		T55	1		T146	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T31	11		T195	1		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1663	1			T2	49		T6	40		T7	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	1		T37	3		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T29	11		T215	1		T145	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T87	4		T215	1		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	3		T82	17		T84	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T9	1		T51	14		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T15	8		T26	4		T92	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T194	18		T31	8		T32	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	8		T39	3		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	8		T42	1		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T44	10		T28	1		T32	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T3	5		T42	14		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T213	17		T256	17		T230	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T31	14		T136	7		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16791	1			T1	100		T3	14		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T26	1		T48	1		T55	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T127	11		T49	12		T88	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	10		T63	13		T168	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T127	10		T167	10		T128	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T146	7		T203	3		T204	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T31	18		T168	7		T88	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T11	7		T52	26		T45	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T37	1		T87	11		T144	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T29	2		T231	24		T246	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T87	5		T221	2		T50	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	4		T63	3		T88	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T37	2		T39	5		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	3		T26	3		T92	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T31	9		T148	9		T171	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T39	1		T197	10		T242	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T42	2		T25	9		T167	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T44	3		T28	2		T63	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	2		T42	13		T221	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T213	15		T230	1		T262	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T31	15		T138	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	2		T15	1		T17	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T19	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T280	1		T281	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T162	6		T284	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T241	9		T282	17		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T82	21		T84	1		T48	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T127	3		T49	9		T88	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	1		T11	1		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	22		T127	14		T48	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T63	9		T127	9		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T63	1		T195	1		T167	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	1		T11	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	1		T37	3		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1729	1			T2	49		T6	40		T7	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T87	10		T215	2		T50	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	3		T82	17		T63	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T51	14		T37	3		T31	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T39	3		T15	8		T26	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T9	1		T39	6		T194	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	8		T130	1		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	8		T42	1		T167	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T44	10		T28	1		T32	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T3	5		T42	14		T25	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T1	100		T3	14		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T19	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T281	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T162	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T241	14		T282	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T48	1		T55	13		T148	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T127	11		T49	12		T88	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	10		T26	1		T168	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T127	10		T220	15		T252	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T63	13		T146	7		T204	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T167	10		T168	7		T88	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	7		T203	3		T247	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T37	1		T31	18		T87	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T52	26		T45	11		T29	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T87	11		T50	1		T238	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	4		T63	3		T88	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T37	2		T31	9		T128	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T39	1		T15	3		T26	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T39	5		T16	2		T29	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T197	10		T18	3		T214	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T42	2		T167	10		T146	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T44	3		T28	2		T63	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T3	2		T42	13		T25	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T15	1		T17	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T26	2		T82	2		T84	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T127	12		T49	18		T88	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	1		T11	11		T63	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	1		T63	1		T127	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	1		T55	1		T146	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T31	19		T195	1		T168	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T2	3		T6	3		T7	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	1		T37	3		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T29	3		T215	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T87	6		T215	1		T221	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	5		T82	1		T84	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	1		T51	1		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	9		T26	6		T92	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T194	1		T31	10		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	1		T39	3		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T5	1		T42	3		T25	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T44	4		T28	3		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T3	3		T42	14		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T213	16		T256	1		T230	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T31	16		T136	1		T138	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16925	1			T1	100		T3	16		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T82	19		T48	2		T55	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T127	2		T49	3		T88	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T63	8		T159	17		T196	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	21		T127	13		T167	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T146	8		T204	15		T258	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T31	10		T88	12		T222	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T2	46		T6	37		T7	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T37	1		T87	9		T199	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T29	10		T145	14		T231	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T87	3		T50	2		T214	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	2		T82	16		T88	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T51	13		T37	2		T39	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T15	2		T26	1		T92	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T194	17		T31	7		T32	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	7		T39	1		T242	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	7		T25	10		T167	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T44	9		T32	2		T63	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T3	4		T42	13		T129	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T213	16		T256	16		T230	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T31	13		T136	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T204	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T19	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T280	1		T281	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T162	16		T284	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T241	15		T282	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T82	2		T84	1		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T127	12		T49	18		T88	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	1		T11	11		T26	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	1		T127	11		T48	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T63	14		T127	1		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T63	1		T195	1		T167	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	1		T11	8		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	1		T37	3		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T2	3		T6	3		T7	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T87	12		T215	2		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	5		T82	1		T63	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T51	1		T37	3		T31	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T39	3		T15	9		T26	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	1		T39	6		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	1		T130	1		T197	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T5	1		T42	3		T167	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	405	1			T44	4		T28	3		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T3	3		T42	14		T25	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	100		T3	16		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T19	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T162	5		T284	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T241	8		T282	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T82	19		T48	2		T55	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T127	2		T49	3		T88	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T159	17		T196	15		T249	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	21		T127	13		T129	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T63	8		T127	8		T146	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T167	2		T88	12		T128	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T247	8		T268	12		T285	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T37	1		T31	10		T87	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T2	46		T6	37		T7	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T87	9		T50	2		T214	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	2		T82	16		T88	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T51	13		T37	2		T31	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T39	1		T15	2		T26	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T39	5		T194	17		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	7		T18	4		T214	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	7		T167	11		T49	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T44	9		T32	2		T63	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T3	4		T42	13		T25	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21855

1

T1

100

T2

3

T3

24

auto[1]

auto[0]

4357

1

T2

46

T3

6

T5

28