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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 99.07 96.67 100.00 100.00 98.83 98.33 91.61


Total test records in report: 917
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T793 /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3731612467 Aug 09 05:34:53 PM PDT 24 Aug 09 05:49:55 PM PDT 24 396290580682 ps
T177 /workspace/coverage/default/24.adc_ctrl_stress_all.3683414196 Aug 09 05:35:49 PM PDT 24 Aug 09 05:49:23 PM PDT 24 286504126032 ps
T67 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2659402055 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:15 PM PDT 24 511895309 ps
T106 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3880581591 Aug 09 05:53:09 PM PDT 24 Aug 09 05:53:10 PM PDT 24 538757637 ps
T794 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1404020619 Aug 09 05:53:18 PM PDT 24 Aug 09 05:53:19 PM PDT 24 518546927 ps
T68 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2883205501 Aug 09 05:53:11 PM PDT 24 Aug 09 05:53:15 PM PDT 24 541604692 ps
T64 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1082830812 Aug 09 05:53:14 PM PDT 24 Aug 09 05:53:23 PM PDT 24 4038654291 ps
T107 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4211943712 Aug 09 05:53:11 PM PDT 24 Aug 09 05:53:12 PM PDT 24 588913870 ps
T124 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.896921388 Aug 09 05:53:03 PM PDT 24 Aug 09 05:53:06 PM PDT 24 1199660154 ps
T795 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.986774071 Aug 09 05:53:17 PM PDT 24 Aug 09 05:53:19 PM PDT 24 495317954 ps
T60 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.407747477 Aug 09 05:53:10 PM PDT 24 Aug 09 05:53:19 PM PDT 24 3965183896 ps
T86 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2213774087 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:14 PM PDT 24 447094542 ps
T72 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2526412205 Aug 09 05:53:17 PM PDT 24 Aug 09 05:53:18 PM PDT 24 373948651 ps
T796 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2742851030 Aug 09 05:53:26 PM PDT 24 Aug 09 05:53:27 PM PDT 24 532935343 ps
T61 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.474979401 Aug 09 05:53:10 PM PDT 24 Aug 09 05:53:15 PM PDT 24 2706034673 ps
T797 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2375748324 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:14 PM PDT 24 326701593 ps
T120 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1868162001 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:14 PM PDT 24 544486277 ps
T65 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2678465778 Aug 09 05:53:07 PM PDT 24 Aug 09 05:53:14 PM PDT 24 4240437555 ps
T73 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1967893794 Aug 09 05:53:14 PM PDT 24 Aug 09 05:53:17 PM PDT 24 766164930 ps
T121 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1518005321 Aug 09 05:53:09 PM PDT 24 Aug 09 05:53:10 PM PDT 24 575421477 ps
T66 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.230834937 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:34 PM PDT 24 8444465214 ps
T798 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.262660757 Aug 09 05:53:24 PM PDT 24 Aug 09 05:53:26 PM PDT 24 312227747 ps
T69 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2288988170 Aug 09 05:53:11 PM PDT 24 Aug 09 05:53:22 PM PDT 24 3982552817 ps
T79 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3179971510 Aug 09 05:52:59 PM PDT 24 Aug 09 05:53:12 PM PDT 24 4658523220 ps
T62 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2948712857 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:18 PM PDT 24 4606487904 ps
T125 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1283328920 Aug 09 05:53:00 PM PDT 24 Aug 09 05:53:26 PM PDT 24 26812154978 ps
T122 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2934280550 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:13 PM PDT 24 533621317 ps
T78 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2209416106 Aug 09 05:53:10 PM PDT 24 Aug 09 05:53:11 PM PDT 24 567129614 ps
T799 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.74625716 Aug 09 05:53:28 PM PDT 24 Aug 09 05:53:30 PM PDT 24 469479668 ps
T108 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1735991721 Aug 09 05:53:04 PM PDT 24 Aug 09 05:54:34 PM PDT 24 20851628912 ps
T800 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3012725210 Aug 09 05:53:04 PM PDT 24 Aug 09 05:53:07 PM PDT 24 922634892 ps
T77 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.456718557 Aug 09 05:53:24 PM PDT 24 Aug 09 05:53:26 PM PDT 24 588928805 ps
T123 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2066192291 Aug 09 05:53:23 PM PDT 24 Aug 09 05:53:28 PM PDT 24 4325859135 ps
T109 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3905564540 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:13 PM PDT 24 483322165 ps
T110 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3639303623 Aug 09 05:53:11 PM PDT 24 Aug 09 05:53:54 PM PDT 24 16570330151 ps
T801 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3978198708 Aug 09 05:53:23 PM PDT 24 Aug 09 05:53:30 PM PDT 24 1603414953 ps
T74 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3503652867 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:15 PM PDT 24 990550538 ps
T802 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.394827580 Aug 09 05:53:17 PM PDT 24 Aug 09 05:53:20 PM PDT 24 453525611 ps
T803 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1873493352 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:15 PM PDT 24 473208259 ps
T320 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1848622406 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:32 PM PDT 24 8275495260 ps
T321 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3603232119 Aug 09 05:53:10 PM PDT 24 Aug 09 05:53:13 PM PDT 24 4077746352 ps
T804 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.257450771 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:20 PM PDT 24 8354095738 ps
T805 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4023890004 Aug 09 05:53:15 PM PDT 24 Aug 09 05:53:17 PM PDT 24 475972768 ps
T806 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.115821489 Aug 09 05:53:18 PM PDT 24 Aug 09 05:53:28 PM PDT 24 4034675520 ps
T807 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2332151325 Aug 09 05:53:20 PM PDT 24 Aug 09 05:53:22 PM PDT 24 618028464 ps
T808 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.150434067 Aug 09 05:53:15 PM PDT 24 Aug 09 05:53:16 PM PDT 24 431622310 ps
T809 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2567030362 Aug 09 05:53:17 PM PDT 24 Aug 09 05:53:19 PM PDT 24 519543015 ps
T810 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.595301458 Aug 09 05:53:19 PM PDT 24 Aug 09 05:53:26 PM PDT 24 5624401176 ps
T811 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2686032747 Aug 09 05:53:17 PM PDT 24 Aug 09 05:53:19 PM PDT 24 5002793404 ps
T812 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2778212297 Aug 09 05:53:18 PM PDT 24 Aug 09 05:53:21 PM PDT 24 4492841814 ps
T813 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.385182855 Aug 09 05:53:22 PM PDT 24 Aug 09 05:53:24 PM PDT 24 543473661 ps
T814 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3355226498 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:17 PM PDT 24 602764534 ps
T815 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1232929718 Aug 09 05:53:11 PM PDT 24 Aug 09 05:53:12 PM PDT 24 373357673 ps
T322 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1112294284 Aug 09 05:53:14 PM PDT 24 Aug 09 05:53:29 PM PDT 24 7737705167 ps
T816 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3145266336 Aug 09 05:53:15 PM PDT 24 Aug 09 05:53:19 PM PDT 24 4512422974 ps
T817 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3285561698 Aug 09 05:53:24 PM PDT 24 Aug 09 05:53:25 PM PDT 24 346290716 ps
T818 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2809175988 Aug 09 05:53:15 PM PDT 24 Aug 09 05:53:19 PM PDT 24 4303620704 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.178994096 Aug 09 05:53:01 PM PDT 24 Aug 09 05:53:02 PM PDT 24 910073537 ps
T819 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.525194124 Aug 09 05:53:23 PM PDT 24 Aug 09 05:53:25 PM PDT 24 484954138 ps
T318 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3632774722 Aug 09 05:53:07 PM PDT 24 Aug 09 05:53:14 PM PDT 24 8342254311 ps
T820 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3922544908 Aug 09 05:53:06 PM PDT 24 Aug 09 05:53:18 PM PDT 24 4136625501 ps
T821 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2920180078 Aug 09 05:53:02 PM PDT 24 Aug 09 05:53:03 PM PDT 24 441928568 ps
T822 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.527157835 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:14 PM PDT 24 488115911 ps
T823 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.33141532 Aug 09 05:53:01 PM PDT 24 Aug 09 05:53:03 PM PDT 24 492860005 ps
T824 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2251980921 Aug 09 05:53:06 PM PDT 24 Aug 09 05:53:07 PM PDT 24 347130954 ps
T825 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2646772326 Aug 09 05:53:24 PM PDT 24 Aug 09 05:53:25 PM PDT 24 541207740 ps
T826 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2601510402 Aug 09 05:53:24 PM PDT 24 Aug 09 05:53:25 PM PDT 24 511456008 ps
T827 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1252239296 Aug 09 05:53:14 PM PDT 24 Aug 09 05:53:15 PM PDT 24 502821474 ps
T828 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2229239044 Aug 09 05:53:05 PM PDT 24 Aug 09 05:53:07 PM PDT 24 871857707 ps
T112 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2367407224 Aug 09 05:53:07 PM PDT 24 Aug 09 05:53:08 PM PDT 24 421609116 ps
T829 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.513375880 Aug 09 05:53:23 PM PDT 24 Aug 09 05:53:24 PM PDT 24 509811938 ps
T830 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1170756531 Aug 09 05:53:23 PM PDT 24 Aug 09 05:53:26 PM PDT 24 310798264 ps
T113 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2808760699 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:15 PM PDT 24 361378720 ps
T831 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1365744669 Aug 09 05:53:11 PM PDT 24 Aug 09 05:53:12 PM PDT 24 363969976 ps
T114 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4062739882 Aug 09 05:53:09 PM PDT 24 Aug 09 05:53:11 PM PDT 24 1425325334 ps
T832 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.815897784 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:27 PM PDT 24 4569580274 ps
T833 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3704699808 Aug 09 05:53:17 PM PDT 24 Aug 09 05:53:19 PM PDT 24 435179483 ps
T115 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1735816070 Aug 09 05:53:16 PM PDT 24 Aug 09 05:53:17 PM PDT 24 909898261 ps
T834 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1930421116 Aug 09 05:53:10 PM PDT 24 Aug 09 05:53:13 PM PDT 24 2558870308 ps
T835 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3800866784 Aug 09 05:53:22 PM PDT 24 Aug 09 05:53:23 PM PDT 24 292709498 ps
T836 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2323207047 Aug 09 05:53:23 PM PDT 24 Aug 09 05:53:24 PM PDT 24 501456819 ps
T837 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3137047919 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:18 PM PDT 24 2492379908 ps
T838 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2512010903 Aug 09 05:53:03 PM PDT 24 Aug 09 05:53:04 PM PDT 24 392520304 ps
T839 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1618482352 Aug 09 05:53:16 PM PDT 24 Aug 09 05:53:17 PM PDT 24 527092030 ps
T840 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.389466084 Aug 09 05:53:24 PM PDT 24 Aug 09 05:53:25 PM PDT 24 319893872 ps
T116 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.188338174 Aug 09 05:53:05 PM PDT 24 Aug 09 05:53:06 PM PDT 24 344866572 ps
T841 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3922983595 Aug 09 05:53:18 PM PDT 24 Aug 09 05:53:28 PM PDT 24 4377323090 ps
T842 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3571295557 Aug 09 05:53:25 PM PDT 24 Aug 09 05:53:27 PM PDT 24 355649842 ps
T843 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.300837430 Aug 09 05:53:11 PM PDT 24 Aug 09 05:53:15 PM PDT 24 535930623 ps
T844 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3329400926 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:14 PM PDT 24 537734848 ps
T845 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1833846965 Aug 09 05:53:19 PM PDT 24 Aug 09 05:53:21 PM PDT 24 496869317 ps
T846 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2137164698 Aug 09 05:53:14 PM PDT 24 Aug 09 05:53:15 PM PDT 24 607358323 ps
T847 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2315822688 Aug 09 05:53:03 PM PDT 24 Aug 09 05:53:05 PM PDT 24 419594304 ps
T117 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2683116779 Aug 09 05:53:11 PM PDT 24 Aug 09 05:54:01 PM PDT 24 24637199046 ps
T848 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3795037308 Aug 09 05:53:07 PM PDT 24 Aug 09 05:53:18 PM PDT 24 4625757691 ps
T849 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2310197795 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:13 PM PDT 24 466773230 ps
T850 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.305073367 Aug 09 05:53:18 PM PDT 24 Aug 09 05:53:20 PM PDT 24 400661988 ps
T851 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2921343132 Aug 09 05:53:07 PM PDT 24 Aug 09 05:53:08 PM PDT 24 507509800 ps
T852 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3075924130 Aug 09 05:53:14 PM PDT 24 Aug 09 05:53:16 PM PDT 24 445993891 ps
T853 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1941547483 Aug 09 05:53:18 PM PDT 24 Aug 09 05:53:20 PM PDT 24 478217867 ps
T854 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3585069516 Aug 09 05:53:07 PM PDT 24 Aug 09 05:53:08 PM PDT 24 420681338 ps
T855 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.826940836 Aug 09 05:53:14 PM PDT 24 Aug 09 05:53:19 PM PDT 24 4694594871 ps
T856 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2550392015 Aug 09 05:53:04 PM PDT 24 Aug 09 05:53:06 PM PDT 24 1140442025 ps
T857 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2987968278 Aug 09 05:53:22 PM PDT 24 Aug 09 05:53:29 PM PDT 24 4206701345 ps
T858 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2899416462 Aug 09 05:53:10 PM PDT 24 Aug 09 05:53:14 PM PDT 24 4334937357 ps
T319 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.937699689 Aug 09 05:53:22 PM PDT 24 Aug 09 05:53:26 PM PDT 24 4576721787 ps
T859 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2678844573 Aug 09 05:53:11 PM PDT 24 Aug 09 05:53:13 PM PDT 24 495537770 ps
T860 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3280889883 Aug 09 05:53:14 PM PDT 24 Aug 09 05:53:15 PM PDT 24 385784644 ps
T861 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.459208949 Aug 09 05:53:09 PM PDT 24 Aug 09 05:53:16 PM PDT 24 2508968059 ps
T862 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.572772452 Aug 09 05:53:18 PM PDT 24 Aug 09 05:53:19 PM PDT 24 510595411 ps
T863 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1368029680 Aug 09 05:53:08 PM PDT 24 Aug 09 05:53:40 PM PDT 24 26593685550 ps
T864 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4164671196 Aug 09 05:53:01 PM PDT 24 Aug 09 05:53:05 PM PDT 24 2616223840 ps
T865 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3945946178 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:14 PM PDT 24 465333441 ps
T866 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.356977822 Aug 09 05:53:18 PM PDT 24 Aug 09 05:53:19 PM PDT 24 414401258 ps
T867 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.357303509 Aug 09 05:53:05 PM PDT 24 Aug 09 05:53:07 PM PDT 24 558543525 ps
T868 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2216623929 Aug 09 05:53:05 PM PDT 24 Aug 09 05:53:08 PM PDT 24 529253491 ps
T869 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2265064523 Aug 09 05:53:23 PM PDT 24 Aug 09 05:53:25 PM PDT 24 496694614 ps
T870 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3906951990 Aug 09 05:53:23 PM PDT 24 Aug 09 05:53:25 PM PDT 24 362739216 ps
T871 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2909341314 Aug 09 05:53:23 PM PDT 24 Aug 09 05:53:25 PM PDT 24 418030109 ps
T872 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2199010098 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:14 PM PDT 24 595040046 ps
T118 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2949823333 Aug 09 05:53:03 PM PDT 24 Aug 09 05:53:05 PM PDT 24 335945017 ps
T873 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.276027471 Aug 09 05:53:02 PM PDT 24 Aug 09 05:53:04 PM PDT 24 409316793 ps
T874 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1335805564 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:16 PM PDT 24 4770857355 ps
T875 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3924969874 Aug 09 05:53:14 PM PDT 24 Aug 09 05:53:15 PM PDT 24 364769834 ps
T876 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2254881188 Aug 09 05:53:17 PM PDT 24 Aug 09 05:53:18 PM PDT 24 558071481 ps
T877 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.198329779 Aug 09 05:53:21 PM PDT 24 Aug 09 05:53:22 PM PDT 24 293643826 ps
T878 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2495957756 Aug 09 05:53:17 PM PDT 24 Aug 09 05:53:32 PM PDT 24 4175007250 ps
T879 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.456537971 Aug 09 05:53:09 PM PDT 24 Aug 09 05:53:11 PM PDT 24 419719269 ps
T880 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2422740485 Aug 09 05:53:22 PM PDT 24 Aug 09 05:53:24 PM PDT 24 404143057 ps
T881 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.79763696 Aug 09 05:53:22 PM PDT 24 Aug 09 05:53:23 PM PDT 24 622970136 ps
T882 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.775014962 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:14 PM PDT 24 404393213 ps
T883 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.127008047 Aug 09 05:53:23 PM PDT 24 Aug 09 05:53:25 PM PDT 24 516522238 ps
T884 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4028190116 Aug 09 05:53:08 PM PDT 24 Aug 09 05:53:11 PM PDT 24 770308190 ps
T885 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.302314979 Aug 09 05:53:24 PM PDT 24 Aug 09 05:53:26 PM PDT 24 391299876 ps
T886 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.883500119 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:13 PM PDT 24 348636668 ps
T887 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1957253368 Aug 09 05:53:13 PM PDT 24 Aug 09 05:53:19 PM PDT 24 4397246345 ps
T888 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3515426219 Aug 09 05:53:16 PM PDT 24 Aug 09 05:53:18 PM PDT 24 523099316 ps
T889 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.449626783 Aug 09 05:53:16 PM PDT 24 Aug 09 05:53:18 PM PDT 24 698760283 ps
T890 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3513085057 Aug 09 05:53:22 PM PDT 24 Aug 09 05:53:23 PM PDT 24 415277326 ps
T891 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1205730918 Aug 09 05:53:11 PM PDT 24 Aug 09 05:53:15 PM PDT 24 559604638 ps
T892 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3085099500 Aug 09 05:53:04 PM PDT 24 Aug 09 05:53:05 PM PDT 24 580167075 ps
T893 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2717040290 Aug 09 05:53:17 PM PDT 24 Aug 09 05:53:18 PM PDT 24 442475733 ps
T894 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3682755449 Aug 09 05:53:02 PM PDT 24 Aug 09 05:53:07 PM PDT 24 965000859 ps
T895 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3380389782 Aug 09 05:53:10 PM PDT 24 Aug 09 05:53:12 PM PDT 24 372847282 ps
T896 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2230903457 Aug 09 05:53:23 PM PDT 24 Aug 09 05:53:25 PM PDT 24 424512453 ps
T897 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.172141369 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:15 PM PDT 24 2052233574 ps
T898 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.476168925 Aug 09 05:53:09 PM PDT 24 Aug 09 05:53:11 PM PDT 24 1061982906 ps
T899 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2006752705 Aug 09 05:53:16 PM PDT 24 Aug 09 05:53:17 PM PDT 24 337300787 ps
T900 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1649265053 Aug 09 05:53:23 PM PDT 24 Aug 09 05:53:24 PM PDT 24 281176529 ps
T901 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.798355310 Aug 09 05:53:14 PM PDT 24 Aug 09 05:53:16 PM PDT 24 400139509 ps
T902 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.327175060 Aug 09 05:53:25 PM PDT 24 Aug 09 05:53:26 PM PDT 24 472525659 ps
T903 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3126287757 Aug 09 05:53:11 PM PDT 24 Aug 09 05:53:13 PM PDT 24 406701809 ps
T904 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.883305711 Aug 09 05:53:22 PM PDT 24 Aug 09 05:53:23 PM PDT 24 504376635 ps
T905 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.907539837 Aug 09 05:53:21 PM PDT 24 Aug 09 05:53:23 PM PDT 24 516873889 ps
T906 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.341571989 Aug 09 05:53:22 PM PDT 24 Aug 09 05:53:24 PM PDT 24 381178253 ps
T907 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2625158534 Aug 09 05:53:14 PM PDT 24 Aug 09 05:53:24 PM PDT 24 3975448427 ps
T908 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3108096674 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:14 PM PDT 24 420328762 ps
T119 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2334066829 Aug 09 05:53:14 PM PDT 24 Aug 09 05:53:16 PM PDT 24 327675588 ps
T909 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1548127174 Aug 09 05:53:24 PM PDT 24 Aug 09 05:53:26 PM PDT 24 381215052 ps
T910 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.880316504 Aug 09 05:53:15 PM PDT 24 Aug 09 05:53:16 PM PDT 24 493423469 ps
T911 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2083619106 Aug 09 05:53:15 PM PDT 24 Aug 09 05:53:17 PM PDT 24 634631372 ps
T912 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.472981639 Aug 09 05:53:11 PM PDT 24 Aug 09 05:53:13 PM PDT 24 429129987 ps
T913 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2441449417 Aug 09 05:53:17 PM PDT 24 Aug 09 05:53:19 PM PDT 24 443993394 ps
T914 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3494738021 Aug 09 05:53:22 PM PDT 24 Aug 09 05:53:23 PM PDT 24 405538751 ps
T915 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.577261282 Aug 09 05:53:22 PM PDT 24 Aug 09 05:53:27 PM PDT 24 2134423512 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2119958181 Aug 09 05:53:11 PM PDT 24 Aug 09 05:53:12 PM PDT 24 1048605427 ps
T917 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.907978972 Aug 09 05:53:12 PM PDT 24 Aug 09 05:53:20 PM PDT 24 3892411623 ps

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.4049850858
Short name T3
Test name
Test status
Simulation time 327703617012 ps
CPU time 166.98 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:38:12 PM PDT 24
Peak memory 201404 kb
Host smart-dbeac4a3-c3d3-4798-aa55-2a338b2645a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049850858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.4049850858
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3940882574
Short name T53
Test name
Test status
Simulation time 118239669381 ps
CPU time 559.77 seconds
Started Aug 09 05:35:26 PM PDT 24
Finished Aug 09 05:44:46 PM PDT 24
Peak memory 201804 kb
Host smart-b200a329-8658-472a-9580-936dd7623ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940882574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3940882574
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2849766571
Short name T49
Test name
Test status
Simulation time 936589931865 ps
CPU time 655.68 seconds
Started Aug 09 05:36:06 PM PDT 24
Finished Aug 09 05:47:02 PM PDT 24
Peak memory 210128 kb
Host smart-a531afbe-3954-4f40-b5c7-4b2b48825883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849766571 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2849766571
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2848787679
Short name T5
Test name
Test status
Simulation time 360768704578 ps
CPU time 211.69 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:38:36 PM PDT 24
Peak memory 201416 kb
Host smart-9f3d6487-28f0-41dd-a1e9-f9f2a4396f2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848787679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2848787679
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1370331825
Short name T63
Test name
Test status
Simulation time 656383587744 ps
CPU time 1385.33 seconds
Started Aug 09 05:38:10 PM PDT 24
Finished Aug 09 06:01:16 PM PDT 24
Peak memory 201408 kb
Host smart-1f9040f6-5ef1-40c5-bec4-afff6d69dac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370331825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1370331825
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.811453486
Short name T18
Test name
Test status
Simulation time 291642375226 ps
CPU time 295.42 seconds
Started Aug 09 05:37:09 PM PDT 24
Finished Aug 09 05:42:05 PM PDT 24
Peak memory 210072 kb
Host smart-3e810185-4e5c-41b2-8afb-04f8010595d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811453486 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.811453486
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1398953431
Short name T31
Test name
Test status
Simulation time 508203389567 ps
CPU time 541.88 seconds
Started Aug 09 05:34:56 PM PDT 24
Finished Aug 09 05:43:58 PM PDT 24
Peak memory 201408 kb
Host smart-edec6fd5-e414-43d4-8951-efafe10d1afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398953431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1398953431
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.879643631
Short name T92
Test name
Test status
Simulation time 527012445484 ps
CPU time 1026.89 seconds
Started Aug 09 05:35:53 PM PDT 24
Finished Aug 09 05:53:00 PM PDT 24
Peak memory 201384 kb
Host smart-b8a9fec0-655f-4df9-bdb2-1b1174b71408
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879643631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.879643631
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3405014579
Short name T247
Test name
Test status
Simulation time 665342332728 ps
CPU time 367.19 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:41:33 PM PDT 24
Peak memory 201504 kb
Host smart-727cc29a-ee1d-4362-b640-09b50839c6eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405014579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3405014579
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2916517296
Short name T42
Test name
Test status
Simulation time 569771882301 ps
CPU time 363.6 seconds
Started Aug 09 05:36:03 PM PDT 24
Finished Aug 09 05:42:07 PM PDT 24
Peak memory 201440 kb
Host smart-42cba61e-4a9e-47ed-b4c2-b34a31ed7416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916517296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2916517296
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2192850873
Short name T244
Test name
Test status
Simulation time 575627049318 ps
CPU time 661.38 seconds
Started Aug 09 05:35:50 PM PDT 24
Finished Aug 09 05:46:52 PM PDT 24
Peak memory 201328 kb
Host smart-d20186ac-9ac7-4bdb-ad47-24791646f987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192850873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2192850873
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.114717938
Short name T207
Test name
Test status
Simulation time 507953619860 ps
CPU time 289.59 seconds
Started Aug 09 05:37:03 PM PDT 24
Finished Aug 09 05:41:52 PM PDT 24
Peak memory 201404 kb
Host smart-468b7e69-94ae-42cf-b973-ab6b3cd13e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114717938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.114717938
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1356793332
Short name T27
Test name
Test status
Simulation time 8360491090 ps
CPU time 10.65 seconds
Started Aug 09 05:34:58 PM PDT 24
Finished Aug 09 05:35:09 PM PDT 24
Peak memory 218260 kb
Host smart-8c2b398e-510b-4c1e-bd39-105a02bb4569
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356793332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1356793332
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.229506103
Short name T174
Test name
Test status
Simulation time 510631937181 ps
CPU time 279.54 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 05:40:14 PM PDT 24
Peak memory 201440 kb
Host smart-10686f99-f078-4adc-ac44-ec7553a82fa2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229506103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.229506103
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.136664684
Short name T9
Test name
Test status
Simulation time 486557993378 ps
CPU time 63.78 seconds
Started Aug 09 05:37:08 PM PDT 24
Finished Aug 09 05:38:12 PM PDT 24
Peak memory 201388 kb
Host smart-d0e20162-9ed7-4f62-8389-08695a3c49c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136664684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.136664684
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.443419045
Short name T128
Test name
Test status
Simulation time 537687652009 ps
CPU time 193.84 seconds
Started Aug 09 05:35:59 PM PDT 24
Finished Aug 09 05:39:13 PM PDT 24
Peak memory 201400 kb
Host smart-d5529dc1-40df-4c38-a089-3afc6d38ef0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443419045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.443419045
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2883205501
Short name T68
Test name
Test status
Simulation time 541604692 ps
CPU time 4.03 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 209680 kb
Host smart-2aeb001f-9c31-4c8b-a1dc-d321b4a55902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883205501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2883205501
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2316288344
Short name T205
Test name
Test status
Simulation time 489187786524 ps
CPU time 1153.3 seconds
Started Aug 09 05:36:03 PM PDT 24
Finished Aug 09 05:55:16 PM PDT 24
Peak memory 201452 kb
Host smart-6ae6fb1c-ea8b-4e3f-ab8b-2e9f1aece35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316288344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2316288344
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3639303623
Short name T110
Test name
Test status
Simulation time 16570330151 ps
CPU time 42.92 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:53:54 PM PDT 24
Peak memory 201552 kb
Host smart-dee6c701-0f74-4e78-97a7-ccccf58c4682
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639303623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3639303623
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.277131597
Short name T7
Test name
Test status
Simulation time 397338136169 ps
CPU time 244.73 seconds
Started Aug 09 05:35:41 PM PDT 24
Finished Aug 09 05:39:46 PM PDT 24
Peak memory 201396 kb
Host smart-b266f099-293a-4f73-a2a6-96e8ec43b21c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277131597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.277131597
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3742464714
Short name T230
Test name
Test status
Simulation time 566396792511 ps
CPU time 900.8 seconds
Started Aug 09 05:35:26 PM PDT 24
Finished Aug 09 05:50:28 PM PDT 24
Peak memory 201400 kb
Host smart-b46b5133-8c7a-465e-82d7-01db0600ab3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742464714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3742464714
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3067475964
Short name T129
Test name
Test status
Simulation time 542611903957 ps
CPU time 308.11 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:40:21 PM PDT 24
Peak memory 201304 kb
Host smart-ea9d4572-e258-4298-ad9f-4fca7372a46c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067475964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3067475964
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1230692175
Short name T147
Test name
Test status
Simulation time 336961290381 ps
CPU time 223.08 seconds
Started Aug 09 05:38:05 PM PDT 24
Finished Aug 09 05:41:48 PM PDT 24
Peak memory 201436 kb
Host smart-5e72169e-1279-4811-a040-866fc08838d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230692175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1230692175
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3993210676
Short name T149
Test name
Test status
Simulation time 506899357739 ps
CPU time 322.9 seconds
Started Aug 09 05:35:16 PM PDT 24
Finished Aug 09 05:40:39 PM PDT 24
Peak memory 201496 kb
Host smart-f6d723b4-c467-4a6d-b121-642463ddbcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993210676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3993210676
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2209207516
Short name T190
Test name
Test status
Simulation time 4025406163507 ps
CPU time 2463.15 seconds
Started Aug 09 05:36:16 PM PDT 24
Finished Aug 09 06:17:20 PM PDT 24
Peak memory 201776 kb
Host smart-66ae3967-250e-41bc-8b0e-11c9886f4101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209207516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2209207516
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3731195490
Short name T29
Test name
Test status
Simulation time 346984236966 ps
CPU time 206.45 seconds
Started Aug 09 05:36:21 PM PDT 24
Finished Aug 09 05:39:47 PM PDT 24
Peak memory 201428 kb
Host smart-ed59c5c2-87c6-48a2-a47d-621156362b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731195490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3731195490
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3759665703
Short name T19
Test name
Test status
Simulation time 59089997359 ps
CPU time 158.17 seconds
Started Aug 09 05:35:53 PM PDT 24
Finished Aug 09 05:38:32 PM PDT 24
Peak memory 217796 kb
Host smart-aceda8c2-1d21-46f2-8f51-3bef72dce24c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759665703 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3759665703
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.632729164
Short name T82
Test name
Test status
Simulation time 514986899289 ps
CPU time 436.19 seconds
Started Aug 09 05:36:33 PM PDT 24
Finished Aug 09 05:43:50 PM PDT 24
Peak memory 201504 kb
Host smart-784ba30e-8665-41a7-a010-187237b92bd4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632729164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.632729164
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1648722144
Short name T17
Test name
Test status
Simulation time 120238299206 ps
CPU time 144.58 seconds
Started Aug 09 05:36:56 PM PDT 24
Finished Aug 09 05:39:21 PM PDT 24
Peak memory 210176 kb
Host smart-54f9c01f-29fe-434d-8695-698dbf043624
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648722144 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1648722144
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3870052981
Short name T209
Test name
Test status
Simulation time 314943180407 ps
CPU time 168.5 seconds
Started Aug 09 05:36:46 PM PDT 24
Finished Aug 09 05:39:34 PM PDT 24
Peak memory 210148 kb
Host smart-1af36079-b5ad-47d5-a58f-dc8f432855ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870052981 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3870052981
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.233499688
Short name T342
Test name
Test status
Simulation time 327664054 ps
CPU time 0.79 seconds
Started Aug 09 05:35:11 PM PDT 24
Finished Aug 09 05:35:12 PM PDT 24
Peak memory 201240 kb
Host smart-534dd541-fc21-4d89-a85b-eca8289a5f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233499688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.233499688
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2015628666
Short name T88
Test name
Test status
Simulation time 484277063788 ps
CPU time 1172.3 seconds
Started Aug 09 05:35:35 PM PDT 24
Finished Aug 09 05:55:08 PM PDT 24
Peak memory 201416 kb
Host smart-ac4cd53b-a0c0-4df4-84fd-d94aef44dfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015628666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2015628666
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1082830812
Short name T64
Test name
Test status
Simulation time 4038654291 ps
CPU time 8.84 seconds
Started Aug 09 05:53:14 PM PDT 24
Finished Aug 09 05:53:23 PM PDT 24
Peak memory 201616 kb
Host smart-479d7d65-7c74-469d-9511-9ab38802a734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082830812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1082830812
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1530318989
Short name T141
Test name
Test status
Simulation time 492699478877 ps
CPU time 1144 seconds
Started Aug 09 05:35:05 PM PDT 24
Finished Aug 09 05:54:10 PM PDT 24
Peak memory 201372 kb
Host smart-7b3de1bd-35ff-4593-be9a-49761c7f4937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530318989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1530318989
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3136720403
Short name T162
Test name
Test status
Simulation time 499582418382 ps
CPU time 311.78 seconds
Started Aug 09 05:35:41 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 201472 kb
Host smart-300a0371-2703-4e5f-b6a3-05bd000f0c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136720403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3136720403
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.407747477
Short name T60
Test name
Test status
Simulation time 3965183896 ps
CPU time 8.79 seconds
Started Aug 09 05:53:10 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201640 kb
Host smart-a5f29396-4b75-4015-8164-3de6158965ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407747477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.407747477
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1964261209
Short name T265
Test name
Test status
Simulation time 676875775367 ps
CPU time 807.91 seconds
Started Aug 09 05:35:52 PM PDT 24
Finished Aug 09 05:49:20 PM PDT 24
Peak memory 201408 kb
Host smart-973c5525-0a16-4c28-9f80-a9cad88e01cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964261209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1964261209
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3480088747
Short name T203
Test name
Test status
Simulation time 492984829184 ps
CPU time 1209.1 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:55:26 PM PDT 24
Peak memory 201428 kb
Host smart-17f2d70c-6716-4eda-bc74-d5f45c28fdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480088747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3480088747
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.4112310825
Short name T192
Test name
Test status
Simulation time 166812399993 ps
CPU time 187.73 seconds
Started Aug 09 05:36:50 PM PDT 24
Finished Aug 09 05:39:57 PM PDT 24
Peak memory 201368 kb
Host smart-566789bb-ab93-4673-85fd-a4975dddc30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112310825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.4112310825
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1930970984
Short name T168
Test name
Test status
Simulation time 325607568916 ps
CPU time 369.85 seconds
Started Aug 09 05:35:47 PM PDT 24
Finished Aug 09 05:41:57 PM PDT 24
Peak memory 201404 kb
Host smart-662b5c38-d43e-435b-9bb7-94ae0d2f6d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930970984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1930970984
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2332057906
Short name T137
Test name
Test status
Simulation time 490648762999 ps
CPU time 246.82 seconds
Started Aug 09 05:36:33 PM PDT 24
Finished Aug 09 05:40:40 PM PDT 24
Peak memory 201456 kb
Host smart-bd00fcde-cb89-4237-b22d-9cb5a4956736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332057906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2332057906
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3921685770
Short name T243
Test name
Test status
Simulation time 546800614479 ps
CPU time 295.53 seconds
Started Aug 09 05:37:33 PM PDT 24
Finished Aug 09 05:42:28 PM PDT 24
Peak memory 201300 kb
Host smart-24087386-381f-4386-bdd4-7e8bc6c1c354
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921685770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3921685770
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.447189026
Short name T223
Test name
Test status
Simulation time 546979816479 ps
CPU time 1361.67 seconds
Started Aug 09 05:35:33 PM PDT 24
Finished Aug 09 05:58:16 PM PDT 24
Peak memory 201376 kb
Host smart-4ebb835c-debb-4b4f-828d-a310e3c8c5c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447189026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.447189026
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2565388493
Short name T304
Test name
Test status
Simulation time 325312465526 ps
CPU time 733.43 seconds
Started Aug 09 05:35:21 PM PDT 24
Finished Aug 09 05:47:35 PM PDT 24
Peak memory 201460 kb
Host smart-1ad87a73-8173-46ee-8bdc-dc5f9149c88e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565388493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2565388493
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1807378405
Short name T169
Test name
Test status
Simulation time 333297055738 ps
CPU time 713.37 seconds
Started Aug 09 05:35:35 PM PDT 24
Finished Aug 09 05:47:29 PM PDT 24
Peak memory 201404 kb
Host smart-1992f699-27d4-42b4-bd1d-d7f7d4a22f42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807378405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1807378405
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3159873905
Short name T48
Test name
Test status
Simulation time 192823762340 ps
CPU time 232.54 seconds
Started Aug 09 05:38:13 PM PDT 24
Finished Aug 09 05:42:06 PM PDT 24
Peak memory 218168 kb
Host smart-c289bfa5-9b32-4965-b5d6-656f9b51278e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159873905 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3159873905
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3224930363
Short name T282
Test name
Test status
Simulation time 511951486812 ps
CPU time 249.1 seconds
Started Aug 09 05:37:02 PM PDT 24
Finished Aug 09 05:41:12 PM PDT 24
Peak memory 201456 kb
Host smart-0b7f810b-0c4f-4d9b-8288-4a9efdb13e74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224930363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3224930363
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2097256390
Short name T102
Test name
Test status
Simulation time 344125449725 ps
CPU time 368.45 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:41:33 PM PDT 24
Peak memory 201428 kb
Host smart-da635c4a-4abe-4bd8-85ec-3c6c681eeb76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097256390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2097256390
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1091018150
Short name T245
Test name
Test status
Simulation time 232792392708 ps
CPU time 151.97 seconds
Started Aug 09 05:35:43 PM PDT 24
Finished Aug 09 05:38:15 PM PDT 24
Peak memory 211308 kb
Host smart-c80a4486-2d6f-4b2d-b974-b9ce01df0452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091018150 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1091018150
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1999147008
Short name T252
Test name
Test status
Simulation time 493791777612 ps
CPU time 608.57 seconds
Started Aug 09 05:36:00 PM PDT 24
Finished Aug 09 05:46:08 PM PDT 24
Peak memory 201388 kb
Host smart-7753f0d6-e28e-42fa-a344-1db77b2eb747
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999147008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1999147008
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.829961540
Short name T545
Test name
Test status
Simulation time 128552720757 ps
CPU time 358.72 seconds
Started Aug 09 05:36:23 PM PDT 24
Finished Aug 09 05:42:22 PM PDT 24
Peak memory 201724 kb
Host smart-aac3c572-9ddb-4a93-a496-d5520d4cf41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829961540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.829961540
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2339570119
Short name T195
Test name
Test status
Simulation time 325480328350 ps
CPU time 438.85 seconds
Started Aug 09 05:37:23 PM PDT 24
Finished Aug 09 05:44:42 PM PDT 24
Peak memory 201408 kb
Host smart-9661cc0c-73e5-4740-a30b-0d07174d3d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339570119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2339570119
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.700742745
Short name T259
Test name
Test status
Simulation time 497610710998 ps
CPU time 254.78 seconds
Started Aug 09 05:35:09 PM PDT 24
Finished Aug 09 05:39:24 PM PDT 24
Peak memory 201344 kb
Host smart-ffe19dff-e729-4690-9621-eb3e96a37fcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700742745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.700742745
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.394827580
Short name T802
Test name
Test status
Simulation time 453525611 ps
CPU time 2.81 seconds
Started Aug 09 05:53:17 PM PDT 24
Finished Aug 09 05:53:20 PM PDT 24
Peak memory 217972 kb
Host smart-242ea248-aaf4-4424-9d71-555a4e1c6cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394827580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.394827580
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2604301386
Short name T277
Test name
Test status
Simulation time 238229910129 ps
CPU time 144.94 seconds
Started Aug 09 05:35:29 PM PDT 24
Finished Aug 09 05:37:54 PM PDT 24
Peak memory 209848 kb
Host smart-1ea43a13-7679-4965-acd8-cb06858af580
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604301386 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2604301386
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1034664456
Short name T301
Test name
Test status
Simulation time 575637361309 ps
CPU time 1392.71 seconds
Started Aug 09 05:35:56 PM PDT 24
Finished Aug 09 05:59:09 PM PDT 24
Peak memory 201448 kb
Host smart-68662a34-5336-4d8a-a33c-64860797c780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034664456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1034664456
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.557116556
Short name T251
Test name
Test status
Simulation time 363569077476 ps
CPU time 826.85 seconds
Started Aug 09 05:36:25 PM PDT 24
Finished Aug 09 05:50:12 PM PDT 24
Peak memory 201336 kb
Host smart-4f0170f1-2c19-462f-897b-d7d94dbce3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557116556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.557116556
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1987636499
Short name T273
Test name
Test status
Simulation time 407705600243 ps
CPU time 498.87 seconds
Started Aug 09 05:38:23 PM PDT 24
Finished Aug 09 05:46:42 PM PDT 24
Peak memory 201460 kb
Host smart-2935eea7-17af-447b-8e62-f9630724c98f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987636499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1987636499
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3151309966
Short name T622
Test name
Test status
Simulation time 104478955226 ps
CPU time 331.08 seconds
Started Aug 09 05:35:10 PM PDT 24
Finished Aug 09 05:40:41 PM PDT 24
Peak memory 201860 kb
Host smart-e41ad050-c6b2-4ede-b757-6fa35b03ed29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151309966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3151309966
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1506653686
Short name T236
Test name
Test status
Simulation time 517285822995 ps
CPU time 1216.97 seconds
Started Aug 09 05:35:23 PM PDT 24
Finished Aug 09 05:55:40 PM PDT 24
Peak memory 201436 kb
Host smart-cec3a0f9-da2f-4519-945d-52dbd4fecd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506653686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1506653686
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3165146133
Short name T246
Test name
Test status
Simulation time 492173232601 ps
CPU time 1194.04 seconds
Started Aug 09 05:35:21 PM PDT 24
Finished Aug 09 05:55:16 PM PDT 24
Peak memory 201416 kb
Host smart-78305fd5-9bce-4410-be06-4d199ce57932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165146133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3165146133
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.310572592
Short name T290
Test name
Test status
Simulation time 353050245372 ps
CPU time 794.05 seconds
Started Aug 09 05:35:42 PM PDT 24
Finished Aug 09 05:48:56 PM PDT 24
Peak memory 201308 kb
Host smart-003dad56-c893-4f7e-9f51-7946c78e476b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310572592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.310572592
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1992515726
Short name T281
Test name
Test status
Simulation time 168295869086 ps
CPU time 64.34 seconds
Started Aug 09 05:36:18 PM PDT 24
Finished Aug 09 05:37:22 PM PDT 24
Peak memory 201424 kb
Host smart-108ee8ae-b518-4480-ad96-8c8cd6f121e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992515726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1992515726
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2515734001
Short name T656
Test name
Test status
Simulation time 350080939187 ps
CPU time 254.38 seconds
Started Aug 09 05:36:23 PM PDT 24
Finished Aug 09 05:40:37 PM PDT 24
Peak memory 210156 kb
Host smart-d109d517-fcf4-4018-8784-bca5301ef2d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515734001 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2515734001
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3501496509
Short name T269
Test name
Test status
Simulation time 506793152753 ps
CPU time 325.71 seconds
Started Aug 09 05:38:18 PM PDT 24
Finished Aug 09 05:43:44 PM PDT 24
Peak memory 201448 kb
Host smart-ef06e608-265f-427c-9d00-c40e656ee2fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501496509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3501496509
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.151938906
Short name T188
Test name
Test status
Simulation time 100961113487 ps
CPU time 363.53 seconds
Started Aug 09 05:34:55 PM PDT 24
Finished Aug 09 05:40:59 PM PDT 24
Peak memory 201820 kb
Host smart-5512c193-604d-4b81-966b-29c24d29c51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151938906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.151938906
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.937699689
Short name T319
Test name
Test status
Simulation time 4576721787 ps
CPU time 4.1 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:26 PM PDT 24
Peak memory 201608 kb
Host smart-f244260e-d9ac-48b5-a763-ef73b8c01762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937699689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.937699689
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.450409930
Short name T99
Test name
Test status
Simulation time 363038795637 ps
CPU time 405.92 seconds
Started Aug 09 05:35:28 PM PDT 24
Finished Aug 09 05:42:14 PM PDT 24
Peak memory 201380 kb
Host smart-2f8dd8b0-5e18-45d1-897e-969a256b58d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450409930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.450409930
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2324003580
Short name T755
Test name
Test status
Simulation time 521329256439 ps
CPU time 76.36 seconds
Started Aug 09 05:35:37 PM PDT 24
Finished Aug 09 05:36:53 PM PDT 24
Peak memory 201408 kb
Host smart-82cbc7f5-6ffd-4889-8777-cc27570a455b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324003580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2324003580
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2597249925
Short name T35
Test name
Test status
Simulation time 492847482780 ps
CPU time 298.67 seconds
Started Aug 09 05:37:11 PM PDT 24
Finished Aug 09 05:42:09 PM PDT 24
Peak memory 201408 kb
Host smart-53d6bf14-906e-43a2-a4a6-2d356b46a900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597249925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2597249925
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2842330363
Short name T255
Test name
Test status
Simulation time 366745318812 ps
CPU time 773.69 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:48:11 PM PDT 24
Peak memory 201332 kb
Host smart-e927299a-e82d-4b38-aee7-18071e9403c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842330363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2842330363
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2684555890
Short name T283
Test name
Test status
Simulation time 482255487623 ps
CPU time 586.93 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:45:04 PM PDT 24
Peak memory 201464 kb
Host smart-c3caac3a-24c1-4ca8-b552-c9e06a175395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684555890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2684555890
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1874059580
Short name T208
Test name
Test status
Simulation time 329213211031 ps
CPU time 194.46 seconds
Started Aug 09 05:34:48 PM PDT 24
Finished Aug 09 05:38:03 PM PDT 24
Peak memory 201472 kb
Host smart-e10aa092-5659-4165-b766-e92c5915ac73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874059580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1874059580
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3322662953
Short name T309
Test name
Test status
Simulation time 346522650981 ps
CPU time 744.97 seconds
Started Aug 09 05:35:01 PM PDT 24
Finished Aug 09 05:47:26 PM PDT 24
Peak memory 201440 kb
Host smart-77ec525c-c90a-41fc-8e8a-b983011577ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322662953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3322662953
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.549350105
Short name T307
Test name
Test status
Simulation time 354610319339 ps
CPU time 209.32 seconds
Started Aug 09 05:35:21 PM PDT 24
Finished Aug 09 05:38:50 PM PDT 24
Peak memory 201432 kb
Host smart-dba53797-eb27-4ab8-94d8-a9924ba38c1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549350105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.549350105
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.239578809
Short name T464
Test name
Test status
Simulation time 166705078316 ps
CPU time 370.2 seconds
Started Aug 09 05:35:05 PM PDT 24
Finished Aug 09 05:41:15 PM PDT 24
Peak memory 201448 kb
Host smart-d1fcd689-694e-4777-acad-40b18bb61c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239578809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.239578809
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2625579055
Short name T160
Test name
Test status
Simulation time 483097079650 ps
CPU time 272.22 seconds
Started Aug 09 05:35:22 PM PDT 24
Finished Aug 09 05:39:55 PM PDT 24
Peak memory 201456 kb
Host smart-65c6e35c-6cfc-4fd4-803d-c5069abc9620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625579055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2625579055
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3486864744
Short name T185
Test name
Test status
Simulation time 111652405530 ps
CPU time 464.67 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:43:09 PM PDT 24
Peak memory 201828 kb
Host smart-2b9e3c81-666a-4adc-a840-b2f0bff2a402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486864744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3486864744
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.422606897
Short name T327
Test name
Test status
Simulation time 228716950451 ps
CPU time 679.33 seconds
Started Aug 09 05:35:16 PM PDT 24
Finished Aug 09 05:46:35 PM PDT 24
Peak memory 217984 kb
Host smart-68f50db9-aaa9-47b6-9192-97014c21abff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422606897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
422606897
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1896690924
Short name T58
Test name
Test status
Simulation time 340867328011 ps
CPU time 245.77 seconds
Started Aug 09 05:35:22 PM PDT 24
Finished Aug 09 05:39:28 PM PDT 24
Peak memory 217216 kb
Host smart-333ebff6-f22d-4de7-b076-927cf1f7280f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896690924 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1896690924
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3683414196
Short name T177
Test name
Test status
Simulation time 286504126032 ps
CPU time 814.26 seconds
Started Aug 09 05:35:49 PM PDT 24
Finished Aug 09 05:49:23 PM PDT 24
Peak memory 210004 kb
Host smart-32c1e8f7-9a01-48c5-9a4b-7162e2a9ddc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683414196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3683414196
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3532155158
Short name T275
Test name
Test status
Simulation time 439756352590 ps
CPU time 166.2 seconds
Started Aug 09 05:35:52 PM PDT 24
Finished Aug 09 05:38:39 PM PDT 24
Peak memory 201344 kb
Host smart-c6e282c1-e8e4-4180-b5bc-8bf2935b6696
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532155158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3532155158
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2716912469
Short name T305
Test name
Test status
Simulation time 426735966506 ps
CPU time 503.72 seconds
Started Aug 09 05:35:55 PM PDT 24
Finished Aug 09 05:44:19 PM PDT 24
Peak memory 201360 kb
Host smart-c876021a-1aa4-4da7-aa91-57da9819a91f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716912469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2716912469
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.156526513
Short name T186
Test name
Test status
Simulation time 120198699469 ps
CPU time 590.36 seconds
Started Aug 09 05:35:57 PM PDT 24
Finished Aug 09 05:45:48 PM PDT 24
Peak memory 201780 kb
Host smart-933a7339-a033-4d57-870b-8b8147c1967c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156526513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.156526513
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2021443763
Short name T163
Test name
Test status
Simulation time 511591937307 ps
CPU time 139.26 seconds
Started Aug 09 05:36:04 PM PDT 24
Finished Aug 09 05:38:23 PM PDT 24
Peak memory 201452 kb
Host smart-aa236178-a361-4857-9098-7944bf969640
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021443763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2021443763
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3757316549
Short name T226
Test name
Test status
Simulation time 578740616163 ps
CPU time 1189.07 seconds
Started Aug 09 05:36:31 PM PDT 24
Finished Aug 09 05:56:21 PM PDT 24
Peak memory 201376 kb
Host smart-d345243d-cb51-461c-92b3-6401272b728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757316549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3757316549
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2477669528
Short name T262
Test name
Test status
Simulation time 335772806944 ps
CPU time 806.8 seconds
Started Aug 09 05:35:06 PM PDT 24
Finished Aug 09 05:48:33 PM PDT 24
Peak memory 201360 kb
Host smart-5137bbb3-7b40-4659-b24d-fa9573e77d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477669528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2477669528
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3570901837
Short name T302
Test name
Test status
Simulation time 331420540881 ps
CPU time 141.4 seconds
Started Aug 09 05:37:04 PM PDT 24
Finished Aug 09 05:39:25 PM PDT 24
Peak memory 201364 kb
Host smart-ccbdede2-7857-4a25-b40a-370ce4eba816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570901837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3570901837
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.411558953
Short name T204
Test name
Test status
Simulation time 515778176272 ps
CPU time 297.44 seconds
Started Aug 09 05:34:54 PM PDT 24
Finished Aug 09 05:39:51 PM PDT 24
Peak memory 201476 kb
Host smart-e77017a2-de16-4a77-80a4-eead327787ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411558953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.411558953
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3682755449
Short name T894
Test name
Test status
Simulation time 965000859 ps
CPU time 4.21 seconds
Started Aug 09 05:53:02 PM PDT 24
Finished Aug 09 05:53:07 PM PDT 24
Peak memory 201536 kb
Host smart-1cfdd852-0673-4d32-9953-0605f74b8a80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682755449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3682755449
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1283328920
Short name T125
Test name
Test status
Simulation time 26812154978 ps
CPU time 25.31 seconds
Started Aug 09 05:53:00 PM PDT 24
Finished Aug 09 05:53:26 PM PDT 24
Peak memory 201620 kb
Host smart-0b81d152-fc5f-4480-8d5c-3e1384984d95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283328920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1283328920
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.178994096
Short name T111
Test name
Test status
Simulation time 910073537 ps
CPU time 1.23 seconds
Started Aug 09 05:53:01 PM PDT 24
Finished Aug 09 05:53:02 PM PDT 24
Peak memory 201272 kb
Host smart-1285e2ab-3b82-47d4-a911-dc348da3c66d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178994096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.178994096
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2199010098
Short name T872
Test name
Test status
Simulation time 595040046 ps
CPU time 1.17 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:14 PM PDT 24
Peak memory 201520 kb
Host smart-084f04d8-6aa1-4211-8dc4-94e6da0ac09e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199010098 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2199010098
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.33141532
Short name T823
Test name
Test status
Simulation time 492860005 ps
CPU time 1.36 seconds
Started Aug 09 05:53:01 PM PDT 24
Finished Aug 09 05:53:03 PM PDT 24
Peak memory 201280 kb
Host smart-131a8266-5aa4-4b85-8475-48c87099f63c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33141532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.33141532
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2920180078
Short name T821
Test name
Test status
Simulation time 441928568 ps
CPU time 1.16 seconds
Started Aug 09 05:53:02 PM PDT 24
Finished Aug 09 05:53:03 PM PDT 24
Peak memory 201300 kb
Host smart-e6f83bd5-b9de-47a6-be65-a5a2b06f9a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920180078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2920180078
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2512010903
Short name T838
Test name
Test status
Simulation time 392520304 ps
CPU time 1.27 seconds
Started Aug 09 05:53:03 PM PDT 24
Finished Aug 09 05:53:04 PM PDT 24
Peak memory 201552 kb
Host smart-b2484510-b206-4e7d-a066-a355ff0d3922
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512010903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2512010903
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3179971510
Short name T79
Test name
Test status
Simulation time 4658523220 ps
CPU time 12.1 seconds
Started Aug 09 05:52:59 PM PDT 24
Finished Aug 09 05:53:12 PM PDT 24
Peak memory 201684 kb
Host smart-fc6083a5-33c8-479b-baa8-f8757dfa4e34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179971510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3179971510
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.896921388
Short name T124
Test name
Test status
Simulation time 1199660154 ps
CPU time 2.89 seconds
Started Aug 09 05:53:03 PM PDT 24
Finished Aug 09 05:53:06 PM PDT 24
Peak memory 201492 kb
Host smart-70faa907-690d-4b9f-b47b-d0aac26a5f3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896921388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.896921388
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1368029680
Short name T863
Test name
Test status
Simulation time 26593685550 ps
CPU time 32.11 seconds
Started Aug 09 05:53:08 PM PDT 24
Finished Aug 09 05:53:40 PM PDT 24
Peak memory 201504 kb
Host smart-0d291a9a-2ed0-4127-959f-6f1bf2385205
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368029680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1368029680
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4062739882
Short name T114
Test name
Test status
Simulation time 1425325334 ps
CPU time 1.5 seconds
Started Aug 09 05:53:09 PM PDT 24
Finished Aug 09 05:53:11 PM PDT 24
Peak memory 201332 kb
Host smart-df363731-8e24-495b-bb29-bf90ebcbaca7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062739882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.4062739882
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2315822688
Short name T847
Test name
Test status
Simulation time 419594304 ps
CPU time 1.78 seconds
Started Aug 09 05:53:03 PM PDT 24
Finished Aug 09 05:53:05 PM PDT 24
Peak memory 201500 kb
Host smart-20d8efda-e296-4bf5-ae2f-054f1f07b024
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315822688 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2315822688
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.276027471
Short name T873
Test name
Test status
Simulation time 409316793 ps
CPU time 1.71 seconds
Started Aug 09 05:53:02 PM PDT 24
Finished Aug 09 05:53:04 PM PDT 24
Peak memory 201300 kb
Host smart-131e919c-f7b2-46f6-98f0-c632ce1717b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276027471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.276027471
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2251980921
Short name T824
Test name
Test status
Simulation time 347130954 ps
CPU time 0.94 seconds
Started Aug 09 05:53:06 PM PDT 24
Finished Aug 09 05:53:07 PM PDT 24
Peak memory 201356 kb
Host smart-1f206731-d4a4-47ab-9da2-49a3a7690907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251980921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2251980921
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4164671196
Short name T864
Test name
Test status
Simulation time 2616223840 ps
CPU time 3.88 seconds
Started Aug 09 05:53:01 PM PDT 24
Finished Aug 09 05:53:05 PM PDT 24
Peak memory 201436 kb
Host smart-b898e226-150c-48cc-ac42-eb6c99c00069
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164671196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.4164671196
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.357303509
Short name T867
Test name
Test status
Simulation time 558543525 ps
CPU time 2.62 seconds
Started Aug 09 05:53:05 PM PDT 24
Finished Aug 09 05:53:07 PM PDT 24
Peak memory 209700 kb
Host smart-ebd86492-97e3-49be-a240-b65a8c1dd79e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357303509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.357303509
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3795037308
Short name T848
Test name
Test status
Simulation time 4625757691 ps
CPU time 11.65 seconds
Started Aug 09 05:53:07 PM PDT 24
Finished Aug 09 05:53:18 PM PDT 24
Peak memory 201640 kb
Host smart-5393091a-ada5-4836-8f6c-52f066a6ea01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795037308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3795037308
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1232929718
Short name T815
Test name
Test status
Simulation time 373357673 ps
CPU time 1.21 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:53:12 PM PDT 24
Peak memory 201488 kb
Host smart-38377c10-736e-4a99-b546-42df55b2099e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232929718 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1232929718
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2334066829
Short name T119
Test name
Test status
Simulation time 327675588 ps
CPU time 1.58 seconds
Started Aug 09 05:53:14 PM PDT 24
Finished Aug 09 05:53:16 PM PDT 24
Peak memory 201364 kb
Host smart-8560e96a-3b45-4fe9-8919-9ebd7ad18134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334066829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2334066829
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.572772452
Short name T862
Test name
Test status
Simulation time 510595411 ps
CPU time 1.87 seconds
Started Aug 09 05:53:18 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201352 kb
Host smart-4e59e618-cc3e-4450-9729-22833ebf7e61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572772452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.572772452
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.826940836
Short name T855
Test name
Test status
Simulation time 4694594871 ps
CPU time 4.86 seconds
Started Aug 09 05:53:14 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201544 kb
Host smart-47fd81ef-90ba-4127-8814-bcfb6fadca9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826940836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.826940836
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3503652867
Short name T74
Test name
Test status
Simulation time 990550538 ps
CPU time 2.88 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 201608 kb
Host smart-0655488d-3122-4aa5-8912-23f1b7bcf312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503652867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3503652867
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.150434067
Short name T808
Test name
Test status
Simulation time 431622310 ps
CPU time 1.41 seconds
Started Aug 09 05:53:15 PM PDT 24
Finished Aug 09 05:53:16 PM PDT 24
Peak memory 201504 kb
Host smart-2d582668-e425-477c-b45a-6a203c238df9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150434067 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.150434067
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1518005321
Short name T121
Test name
Test status
Simulation time 575421477 ps
CPU time 1.17 seconds
Started Aug 09 05:53:09 PM PDT 24
Finished Aug 09 05:53:10 PM PDT 24
Peak memory 201336 kb
Host smart-5101193d-7fe4-4b1e-94af-53270813c65d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518005321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1518005321
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.527157835
Short name T822
Test name
Test status
Simulation time 488115911 ps
CPU time 1.68 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:14 PM PDT 24
Peak memory 201360 kb
Host smart-d8c410a9-9bc1-4b15-a156-b4ff19ee6d21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527157835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.527157835
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2495957756
Short name T878
Test name
Test status
Simulation time 4175007250 ps
CPU time 15.43 seconds
Started Aug 09 05:53:17 PM PDT 24
Finished Aug 09 05:53:32 PM PDT 24
Peak memory 201468 kb
Host smart-033f2466-dbcb-4e38-8524-9bdefa771dfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495957756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2495957756
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1335805564
Short name T874
Test name
Test status
Simulation time 4770857355 ps
CPU time 4.26 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:16 PM PDT 24
Peak memory 201604 kb
Host smart-8a22661d-6497-4d82-b2ff-6326fe9e095a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335805564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1335805564
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2137164698
Short name T846
Test name
Test status
Simulation time 607358323 ps
CPU time 0.98 seconds
Started Aug 09 05:53:14 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 201488 kb
Host smart-14a3b95f-d1ef-4593-9439-9c38bd51e2cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137164698 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2137164698
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.356977822
Short name T866
Test name
Test status
Simulation time 414401258 ps
CPU time 0.96 seconds
Started Aug 09 05:53:18 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201348 kb
Host smart-b4703288-7a6e-44a9-bbc7-322f5cd66e2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356977822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.356977822
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.883500119
Short name T886
Test name
Test status
Simulation time 348636668 ps
CPU time 0.82 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:13 PM PDT 24
Peak memory 201368 kb
Host smart-dd30d97c-2bb9-4da3-bd09-b67650eeaf5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883500119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.883500119
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.474979401
Short name T61
Test name
Test status
Simulation time 2706034673 ps
CPU time 5.42 seconds
Started Aug 09 05:53:10 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 201444 kb
Host smart-858a842e-dfd2-473f-876e-441fc8921438
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474979401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.474979401
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.449626783
Short name T889
Test name
Test status
Simulation time 698760283 ps
CPU time 1.89 seconds
Started Aug 09 05:53:16 PM PDT 24
Finished Aug 09 05:53:18 PM PDT 24
Peak memory 201656 kb
Host smart-d8822899-96f0-4010-8704-0735a5d60181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449626783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.449626783
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3145266336
Short name T816
Test name
Test status
Simulation time 4512422974 ps
CPU time 4.06 seconds
Started Aug 09 05:53:15 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201644 kb
Host smart-f9ad62e1-e794-4956-a50b-e69af3a7b3d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145266336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3145266336
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1941547483
Short name T853
Test name
Test status
Simulation time 478217867 ps
CPU time 1.27 seconds
Started Aug 09 05:53:18 PM PDT 24
Finished Aug 09 05:53:20 PM PDT 24
Peak memory 201472 kb
Host smart-04ba347a-bcc8-42b4-bcbd-9b81b869c851
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941547483 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1941547483
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2934280550
Short name T122
Test name
Test status
Simulation time 533621317 ps
CPU time 1.03 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:13 PM PDT 24
Peak memory 201352 kb
Host smart-8e097c10-475e-4d49-97a4-731feaab3617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934280550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2934280550
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.880316504
Short name T910
Test name
Test status
Simulation time 493423469 ps
CPU time 1.19 seconds
Started Aug 09 05:53:15 PM PDT 24
Finished Aug 09 05:53:16 PM PDT 24
Peak memory 201284 kb
Host smart-5e209abd-d7be-4999-9ae0-d962ecfdf08b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880316504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.880316504
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.815897784
Short name T832
Test name
Test status
Simulation time 4569580274 ps
CPU time 14.03 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:27 PM PDT 24
Peak memory 201568 kb
Host smart-8f16dae2-a523-4f45-9f9e-2ddc7c53158e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815897784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.815897784
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1873493352
Short name T803
Test name
Test status
Simulation time 473208259 ps
CPU time 2.37 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 201632 kb
Host smart-85320d3a-5d60-4015-8c60-19cd089d2380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873493352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1873493352
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3922983595
Short name T841
Test name
Test status
Simulation time 4377323090 ps
CPU time 9.88 seconds
Started Aug 09 05:53:18 PM PDT 24
Finished Aug 09 05:53:28 PM PDT 24
Peak memory 201612 kb
Host smart-9ab5bc42-eef7-4a10-a5eb-9b9b58b72113
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922983595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3922983595
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2659402055
Short name T67
Test name
Test status
Simulation time 511895309 ps
CPU time 2 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 201520 kb
Host smart-65f030cc-33f2-4c18-995e-47b53bd7c956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659402055 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2659402055
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1868162001
Short name T120
Test name
Test status
Simulation time 544486277 ps
CPU time 1.08 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:14 PM PDT 24
Peak memory 201324 kb
Host smart-b35002fc-8a09-4c1a-bcdd-26ab1521c465
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868162001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1868162001
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2375748324
Short name T797
Test name
Test status
Simulation time 326701593 ps
CPU time 0.86 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:14 PM PDT 24
Peak memory 201388 kb
Host smart-f64239fe-b4ea-436d-8725-8a62d1b2b328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375748324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2375748324
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.577261282
Short name T915
Test name
Test status
Simulation time 2134423512 ps
CPU time 4.71 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:27 PM PDT 24
Peak memory 201376 kb
Host smart-5f7e7f96-bcdd-4060-90c3-c8b715141a88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577261282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.577261282
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2526412205
Short name T72
Test name
Test status
Simulation time 373948651 ps
CPU time 1.65 seconds
Started Aug 09 05:53:17 PM PDT 24
Finished Aug 09 05:53:18 PM PDT 24
Peak memory 201624 kb
Host smart-71faf543-608d-4dfa-867a-a77a6ee470e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526412205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2526412205
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2987968278
Short name T857
Test name
Test status
Simulation time 4206701345 ps
CPU time 6.57 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:29 PM PDT 24
Peak memory 201496 kb
Host smart-e6d9c258-8488-428e-b534-213473bcd1ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987968278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2987968278
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3329400926
Short name T844
Test name
Test status
Simulation time 537734848 ps
CPU time 2.02 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:14 PM PDT 24
Peak memory 201396 kb
Host smart-142d0334-149c-4561-8ee8-8f62f1078845
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329400926 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3329400926
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2441449417
Short name T913
Test name
Test status
Simulation time 443993394 ps
CPU time 1.85 seconds
Started Aug 09 05:53:17 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201364 kb
Host smart-62fe8e07-b44a-4860-91dc-9b4254504860
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441449417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2441449417
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.775014962
Short name T882
Test name
Test status
Simulation time 404393213 ps
CPU time 1.62 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:14 PM PDT 24
Peak memory 201400 kb
Host smart-b2942040-e91b-44ca-aa8c-ee27c484f71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775014962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.775014962
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2778212297
Short name T812
Test name
Test status
Simulation time 4492841814 ps
CPU time 3.44 seconds
Started Aug 09 05:53:18 PM PDT 24
Finished Aug 09 05:53:21 PM PDT 24
Peak memory 201576 kb
Host smart-de3ca395-b213-4c6e-8e19-774dae9ec91b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778212297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2778212297
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3704699808
Short name T833
Test name
Test status
Simulation time 435179483 ps
CPU time 2.35 seconds
Started Aug 09 05:53:17 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201540 kb
Host smart-e2332893-1281-4cef-a641-7421f2006919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704699808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3704699808
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.230834937
Short name T66
Test name
Test status
Simulation time 8444465214 ps
CPU time 21.24 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:34 PM PDT 24
Peak memory 201684 kb
Host smart-187b2a2d-f0fe-47e0-97f8-6e9a4be189c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230834937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.230834937
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2567030362
Short name T809
Test name
Test status
Simulation time 519543015 ps
CPU time 1.97 seconds
Started Aug 09 05:53:17 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201424 kb
Host smart-6416ec54-e56b-40b8-bcfb-2a576cc1b01c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567030362 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2567030362
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3380389782
Short name T895
Test name
Test status
Simulation time 372847282 ps
CPU time 1.17 seconds
Started Aug 09 05:53:10 PM PDT 24
Finished Aug 09 05:53:12 PM PDT 24
Peak memory 201316 kb
Host smart-c73e4046-df39-417d-be04-c9b76a816e63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380389782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3380389782
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3075924130
Short name T852
Test name
Test status
Simulation time 445993891 ps
CPU time 1.65 seconds
Started Aug 09 05:53:14 PM PDT 24
Finished Aug 09 05:53:16 PM PDT 24
Peak memory 201340 kb
Host smart-ae58702c-d7af-48d7-b508-aa31ec12457b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075924130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3075924130
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2809175988
Short name T818
Test name
Test status
Simulation time 4303620704 ps
CPU time 3.5 seconds
Started Aug 09 05:53:15 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201788 kb
Host smart-61860758-5fb7-401b-b4c2-63b6e079863e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809175988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2809175988
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1205730918
Short name T891
Test name
Test status
Simulation time 559604638 ps
CPU time 3.83 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 209876 kb
Host smart-64485a73-b22f-433f-864d-1eddf00db785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205730918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1205730918
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.257450771
Short name T804
Test name
Test status
Simulation time 8354095738 ps
CPU time 7.61 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:20 PM PDT 24
Peak memory 201644 kb
Host smart-194cfb10-4afc-431f-ade3-f9b182c33c74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257450771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.257450771
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.456718557
Short name T77
Test name
Test status
Simulation time 588928805 ps
CPU time 1.61 seconds
Started Aug 09 05:53:24 PM PDT 24
Finished Aug 09 05:53:26 PM PDT 24
Peak memory 201700 kb
Host smart-d2380294-f173-447b-8b41-c9ea932eae7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456718557 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.456718557
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.798355310
Short name T901
Test name
Test status
Simulation time 400139509 ps
CPU time 1 seconds
Started Aug 09 05:53:14 PM PDT 24
Finished Aug 09 05:53:16 PM PDT 24
Peak memory 201284 kb
Host smart-147d634d-a058-45d5-8ae5-0668290983f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798355310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.798355310
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1252239296
Short name T827
Test name
Test status
Simulation time 502821474 ps
CPU time 0.94 seconds
Started Aug 09 05:53:14 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 201352 kb
Host smart-0a10ac41-b581-4375-b2ce-afc23f194e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252239296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1252239296
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.115821489
Short name T806
Test name
Test status
Simulation time 4034675520 ps
CPU time 9.75 seconds
Started Aug 09 05:53:18 PM PDT 24
Finished Aug 09 05:53:28 PM PDT 24
Peak memory 201508 kb
Host smart-e23890db-c58c-49d4-8e68-68f83efea5e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115821489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.115821489
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2332151325
Short name T807
Test name
Test status
Simulation time 618028464 ps
CPU time 1.96 seconds
Started Aug 09 05:53:20 PM PDT 24
Finished Aug 09 05:53:22 PM PDT 24
Peak memory 201608 kb
Host smart-b1004599-9a2c-4141-a1f6-6da78e399d75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332151325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2332151325
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1833846965
Short name T845
Test name
Test status
Simulation time 496869317 ps
CPU time 1.97 seconds
Started Aug 09 05:53:19 PM PDT 24
Finished Aug 09 05:53:21 PM PDT 24
Peak memory 201492 kb
Host smart-62c14f70-e03a-4ddb-a413-6fca2fec36fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833846965 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1833846965
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2601510402
Short name T826
Test name
Test status
Simulation time 511456008 ps
CPU time 1.21 seconds
Started Aug 09 05:53:24 PM PDT 24
Finished Aug 09 05:53:25 PM PDT 24
Peak memory 201272 kb
Host smart-a6e3fb30-0b7e-45d1-ba66-2506ed539265
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601510402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2601510402
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.986774071
Short name T795
Test name
Test status
Simulation time 495317954 ps
CPU time 0.92 seconds
Started Aug 09 05:53:17 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201256 kb
Host smart-aa657c16-af5c-4f24-bf9e-7cece554e11b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986774071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.986774071
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3978198708
Short name T801
Test name
Test status
Simulation time 1603414953 ps
CPU time 6.58 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:30 PM PDT 24
Peak memory 201248 kb
Host smart-3b4670b4-99e1-406e-bc04-4de9daa67dfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978198708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3978198708
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3906951990
Short name T870
Test name
Test status
Simulation time 362739216 ps
CPU time 1.98 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:25 PM PDT 24
Peak memory 201888 kb
Host smart-9fba3c28-2973-416f-bce6-b33c89fa4899
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906951990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3906951990
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2686032747
Short name T811
Test name
Test status
Simulation time 5002793404 ps
CPU time 2.12 seconds
Started Aug 09 05:53:17 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201612 kb
Host smart-828c5f61-75e6-4791-b0bc-919529ceefd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686032747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2686032747
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2422740485
Short name T880
Test name
Test status
Simulation time 404143057 ps
CPU time 1.25 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:24 PM PDT 24
Peak memory 201520 kb
Host smart-8a724085-887d-4521-ba35-f94f1e119a51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422740485 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2422740485
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3515426219
Short name T888
Test name
Test status
Simulation time 523099316 ps
CPU time 1.9 seconds
Started Aug 09 05:53:16 PM PDT 24
Finished Aug 09 05:53:18 PM PDT 24
Peak memory 201368 kb
Host smart-87dc24dc-2017-4c13-833d-9abaa6711d0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515426219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3515426219
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2742851030
Short name T796
Test name
Test status
Simulation time 532935343 ps
CPU time 1.22 seconds
Started Aug 09 05:53:26 PM PDT 24
Finished Aug 09 05:53:27 PM PDT 24
Peak memory 201340 kb
Host smart-b29837cb-d841-4354-8f9c-14b7c8c19680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742851030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2742851030
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2066192291
Short name T123
Test name
Test status
Simulation time 4325859135 ps
CPU time 5.15 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:28 PM PDT 24
Peak memory 201460 kb
Host smart-3c46d73a-821f-4c6b-8789-78b1393d07e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066192291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2066192291
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1170756531
Short name T830
Test name
Test status
Simulation time 310798264 ps
CPU time 2.58 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:26 PM PDT 24
Peak memory 210060 kb
Host smart-2e538bcc-c9b5-434b-9e01-9eb58c70b480
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170756531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1170756531
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2625158534
Short name T907
Test name
Test status
Simulation time 3975448427 ps
CPU time 9.51 seconds
Started Aug 09 05:53:14 PM PDT 24
Finished Aug 09 05:53:24 PM PDT 24
Peak memory 201480 kb
Host smart-718c992f-24b8-4526-a352-ce5ecdd4c20c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625158534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2625158534
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2229239044
Short name T828
Test name
Test status
Simulation time 871857707 ps
CPU time 1.99 seconds
Started Aug 09 05:53:05 PM PDT 24
Finished Aug 09 05:53:07 PM PDT 24
Peak memory 201568 kb
Host smart-c9a1ebe4-3f32-4279-97be-2eac3a129e36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229239044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2229239044
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.476168925
Short name T898
Test name
Test status
Simulation time 1061982906 ps
CPU time 1.44 seconds
Started Aug 09 05:53:09 PM PDT 24
Finished Aug 09 05:53:11 PM PDT 24
Peak memory 201324 kb
Host smart-c7c9587b-3295-4dae-9758-12e9de698003
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476168925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.476168925
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3085099500
Short name T892
Test name
Test status
Simulation time 580167075 ps
CPU time 1.26 seconds
Started Aug 09 05:53:04 PM PDT 24
Finished Aug 09 05:53:05 PM PDT 24
Peak memory 201476 kb
Host smart-8fdba51f-e456-4e03-ab57-c013a4960ba7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085099500 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3085099500
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2367407224
Short name T112
Test name
Test status
Simulation time 421609116 ps
CPU time 0.82 seconds
Started Aug 09 05:53:07 PM PDT 24
Finished Aug 09 05:53:08 PM PDT 24
Peak memory 201352 kb
Host smart-52375c3b-b516-48a5-b154-b1b7be5ebfca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367407224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2367407224
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1365744669
Short name T831
Test name
Test status
Simulation time 363969976 ps
CPU time 0.81 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:53:12 PM PDT 24
Peak memory 201340 kb
Host smart-3c0f7de4-ec1a-4518-87f4-0e6d50cae66a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365744669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1365744669
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2948712857
Short name T62
Test name
Test status
Simulation time 4606487904 ps
CPU time 5.01 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:18 PM PDT 24
Peak memory 201564 kb
Host smart-4b72d75e-5fc1-4ab4-ae6c-8e51f3a178e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948712857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2948712857
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2550392015
Short name T856
Test name
Test status
Simulation time 1140442025 ps
CPU time 1.83 seconds
Started Aug 09 05:53:04 PM PDT 24
Finished Aug 09 05:53:06 PM PDT 24
Peak memory 201648 kb
Host smart-c8a926f2-c3ff-4c96-88c5-b6c25f6dc13c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550392015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2550392015
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3922544908
Short name T820
Test name
Test status
Simulation time 4136625501 ps
CPU time 11.64 seconds
Started Aug 09 05:53:06 PM PDT 24
Finished Aug 09 05:53:18 PM PDT 24
Peak memory 201580 kb
Host smart-f9970f84-3ba5-411b-b32f-d3cfa0d5e375
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922544908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3922544908
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.302314979
Short name T885
Test name
Test status
Simulation time 391299876 ps
CPU time 1.56 seconds
Started Aug 09 05:53:24 PM PDT 24
Finished Aug 09 05:53:26 PM PDT 24
Peak memory 201288 kb
Host smart-003b6509-d37d-4824-9834-61e1bbfefd86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302314979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.302314979
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1649265053
Short name T900
Test name
Test status
Simulation time 281176529 ps
CPU time 1.22 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:24 PM PDT 24
Peak memory 201164 kb
Host smart-d01bdab0-fb14-4238-be73-e116ff92035d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649265053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1649265053
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1404020619
Short name T794
Test name
Test status
Simulation time 518546927 ps
CPU time 1.29 seconds
Started Aug 09 05:53:18 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201356 kb
Host smart-834a97d8-98d0-4f94-9d2e-c5ac9831fd61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404020619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1404020619
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2006752705
Short name T899
Test name
Test status
Simulation time 337300787 ps
CPU time 0.81 seconds
Started Aug 09 05:53:16 PM PDT 24
Finished Aug 09 05:53:17 PM PDT 24
Peak memory 201316 kb
Host smart-772e9756-6e9b-4c2f-ae6e-7e5026110c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006752705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2006752705
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.883305711
Short name T904
Test name
Test status
Simulation time 504376635 ps
CPU time 0.91 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:23 PM PDT 24
Peak memory 201372 kb
Host smart-b45a4dd8-600b-43c4-91c6-17c8ce55cc1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883305711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.883305711
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.127008047
Short name T883
Test name
Test status
Simulation time 516522238 ps
CPU time 1.17 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:25 PM PDT 24
Peak memory 201288 kb
Host smart-80df916e-c8fe-484c-9730-ccdf46440457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127008047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.127008047
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1618482352
Short name T839
Test name
Test status
Simulation time 527092030 ps
CPU time 0.95 seconds
Started Aug 09 05:53:16 PM PDT 24
Finished Aug 09 05:53:17 PM PDT 24
Peak memory 201380 kb
Host smart-26c957c4-dcbe-4988-8df5-80e5ba0f47e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618482352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1618482352
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.305073367
Short name T850
Test name
Test status
Simulation time 400661988 ps
CPU time 1.18 seconds
Started Aug 09 05:53:18 PM PDT 24
Finished Aug 09 05:53:20 PM PDT 24
Peak memory 201360 kb
Host smart-e2f2cd03-bd48-4634-a296-bbd63b995090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305073367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.305073367
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3285561698
Short name T817
Test name
Test status
Simulation time 346290716 ps
CPU time 0.87 seconds
Started Aug 09 05:53:24 PM PDT 24
Finished Aug 09 05:53:25 PM PDT 24
Peak memory 201272 kb
Host smart-5874c4d4-d7c5-4480-88f0-a1820eca4289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285561698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3285561698
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2323207047
Short name T836
Test name
Test status
Simulation time 501456819 ps
CPU time 0.91 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:24 PM PDT 24
Peak memory 201272 kb
Host smart-73682243-2dc2-48f8-a177-0061caa84184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323207047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2323207047
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2949823333
Short name T118
Test name
Test status
Simulation time 335945017 ps
CPU time 2.18 seconds
Started Aug 09 05:53:03 PM PDT 24
Finished Aug 09 05:53:05 PM PDT 24
Peak memory 201572 kb
Host smart-5217db2f-fa39-4199-8b63-b9acd79ec638
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949823333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2949823333
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1735991721
Short name T108
Test name
Test status
Simulation time 20851628912 ps
CPU time 89.48 seconds
Started Aug 09 05:53:04 PM PDT 24
Finished Aug 09 05:54:34 PM PDT 24
Peak memory 201560 kb
Host smart-ede739ee-e40e-460c-95e4-839ff0e2101e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735991721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1735991721
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2119958181
Short name T916
Test name
Test status
Simulation time 1048605427 ps
CPU time 1.14 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:53:12 PM PDT 24
Peak memory 201340 kb
Host smart-e3bf1687-7412-4dd0-8eea-4dc9165b5012
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119958181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2119958181
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2216623929
Short name T868
Test name
Test status
Simulation time 529253491 ps
CPU time 2.16 seconds
Started Aug 09 05:53:05 PM PDT 24
Finished Aug 09 05:53:08 PM PDT 24
Peak memory 201476 kb
Host smart-a0030af6-e2f9-4b91-970a-d807a28e564a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216623929 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2216623929
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.341571989
Short name T906
Test name
Test status
Simulation time 381178253 ps
CPU time 1.7 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:24 PM PDT 24
Peak memory 201272 kb
Host smart-c77fe5f5-61d0-448e-83da-cbc3d70bffb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341571989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.341571989
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2678844573
Short name T859
Test name
Test status
Simulation time 495537770 ps
CPU time 1.79 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:53:13 PM PDT 24
Peak memory 201332 kb
Host smart-90f224bf-60cc-4832-9b3c-933b8579c720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678844573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2678844573
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.459208949
Short name T861
Test name
Test status
Simulation time 2508968059 ps
CPU time 6.49 seconds
Started Aug 09 05:53:09 PM PDT 24
Finished Aug 09 05:53:16 PM PDT 24
Peak memory 201368 kb
Host smart-6b7313d1-2293-4747-8bed-040338db0729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459208949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.459208949
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4028190116
Short name T884
Test name
Test status
Simulation time 770308190 ps
CPU time 2.93 seconds
Started Aug 09 05:53:08 PM PDT 24
Finished Aug 09 05:53:11 PM PDT 24
Peak memory 201484 kb
Host smart-efa27f85-2747-4b16-b811-335031835afe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028190116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.4028190116
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3632774722
Short name T318
Test name
Test status
Simulation time 8342254311 ps
CPU time 7.26 seconds
Started Aug 09 05:53:07 PM PDT 24
Finished Aug 09 05:53:14 PM PDT 24
Peak memory 201684 kb
Host smart-5e06f7ce-84fc-4964-b864-203d6f4413fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632774722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3632774722
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1548127174
Short name T909
Test name
Test status
Simulation time 381215052 ps
CPU time 1.5 seconds
Started Aug 09 05:53:24 PM PDT 24
Finished Aug 09 05:53:26 PM PDT 24
Peak memory 201572 kb
Host smart-327dc63e-9227-4e83-ab9a-fba7afd13aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548127174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1548127174
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3280889883
Short name T860
Test name
Test status
Simulation time 385784644 ps
CPU time 0.82 seconds
Started Aug 09 05:53:14 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 201296 kb
Host smart-49fca0a4-ecf2-4006-a836-3a8c6b88f7e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280889883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3280889883
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2265064523
Short name T869
Test name
Test status
Simulation time 496694614 ps
CPU time 1.28 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:25 PM PDT 24
Peak memory 201568 kb
Host smart-eb1bdd70-5de4-47f9-8299-be67e335b5bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265064523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2265064523
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2646772326
Short name T825
Test name
Test status
Simulation time 541207740 ps
CPU time 0.94 seconds
Started Aug 09 05:53:24 PM PDT 24
Finished Aug 09 05:53:25 PM PDT 24
Peak memory 201572 kb
Host smart-f5ee28c4-5379-4337-9d9d-04ba5be0ad3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646772326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2646772326
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.513375880
Short name T829
Test name
Test status
Simulation time 509811938 ps
CPU time 0.89 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:24 PM PDT 24
Peak memory 201288 kb
Host smart-89bbf4ad-d053-4338-a426-176aa30941ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513375880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.513375880
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.385182855
Short name T813
Test name
Test status
Simulation time 543473661 ps
CPU time 1.04 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:24 PM PDT 24
Peak memory 201312 kb
Host smart-204e7546-6f8d-440f-9921-91bf93208de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385182855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.385182855
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3494738021
Short name T914
Test name
Test status
Simulation time 405538751 ps
CPU time 1.06 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:23 PM PDT 24
Peak memory 201284 kb
Host smart-d5bcfb88-8447-41a4-96ad-5cf8788f2d7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494738021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3494738021
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.262660757
Short name T798
Test name
Test status
Simulation time 312227747 ps
CPU time 1.32 seconds
Started Aug 09 05:53:24 PM PDT 24
Finished Aug 09 05:53:26 PM PDT 24
Peak memory 201280 kb
Host smart-6501b570-8186-4264-8304-dc07a3270a42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262660757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.262660757
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3800866784
Short name T835
Test name
Test status
Simulation time 292709498 ps
CPU time 0.85 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:23 PM PDT 24
Peak memory 201324 kb
Host smart-e528c6ef-4f94-4ef0-a733-b3bd7039e636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800866784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3800866784
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.907539837
Short name T905
Test name
Test status
Simulation time 516873889 ps
CPU time 1.48 seconds
Started Aug 09 05:53:21 PM PDT 24
Finished Aug 09 05:53:23 PM PDT 24
Peak memory 201324 kb
Host smart-1745c58f-375a-4f2b-a105-41b62a1bb14c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907539837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.907539837
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3012725210
Short name T800
Test name
Test status
Simulation time 922634892 ps
CPU time 3.35 seconds
Started Aug 09 05:53:04 PM PDT 24
Finished Aug 09 05:53:07 PM PDT 24
Peak memory 201512 kb
Host smart-d28c4ee8-9530-435e-8775-6ec16601b33d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012725210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3012725210
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2683116779
Short name T117
Test name
Test status
Simulation time 24637199046 ps
CPU time 50.57 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:54:01 PM PDT 24
Peak memory 201560 kb
Host smart-dbf7b599-0df9-475f-a33f-2c3357bba30c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683116779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2683116779
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1735816070
Short name T115
Test name
Test status
Simulation time 909898261 ps
CPU time 1.24 seconds
Started Aug 09 05:53:16 PM PDT 24
Finished Aug 09 05:53:17 PM PDT 24
Peak memory 201200 kb
Host smart-bfbda44c-563b-4f73-8bfc-ac9cb01a4171
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735816070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1735816070
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3585069516
Short name T854
Test name
Test status
Simulation time 420681338 ps
CPU time 1.34 seconds
Started Aug 09 05:53:07 PM PDT 24
Finished Aug 09 05:53:08 PM PDT 24
Peak memory 201684 kb
Host smart-7f5e343b-f440-42fb-82e0-8019cd7e4105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585069516 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3585069516
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.188338174
Short name T116
Test name
Test status
Simulation time 344866572 ps
CPU time 1.03 seconds
Started Aug 09 05:53:05 PM PDT 24
Finished Aug 09 05:53:06 PM PDT 24
Peak memory 201356 kb
Host smart-80a19742-c5f3-4a8a-9c0d-ed55cf141df3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188338174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.188338174
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2921343132
Short name T851
Test name
Test status
Simulation time 507509800 ps
CPU time 0.99 seconds
Started Aug 09 05:53:07 PM PDT 24
Finished Aug 09 05:53:08 PM PDT 24
Peak memory 201340 kb
Host smart-1710f354-320a-4263-abe4-5932da292fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921343132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2921343132
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1930421116
Short name T834
Test name
Test status
Simulation time 2558870308 ps
CPU time 2.89 seconds
Started Aug 09 05:53:10 PM PDT 24
Finished Aug 09 05:53:13 PM PDT 24
Peak memory 201428 kb
Host smart-5564a720-6a9d-4802-a292-46dc4d479552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930421116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1930421116
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.300837430
Short name T843
Test name
Test status
Simulation time 535930623 ps
CPU time 2.83 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 217936 kb
Host smart-6be0af91-1dbe-43f7-940f-8d4cfa15c9fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300837430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.300837430
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2678465778
Short name T65
Test name
Test status
Simulation time 4240437555 ps
CPU time 6.66 seconds
Started Aug 09 05:53:07 PM PDT 24
Finished Aug 09 05:53:14 PM PDT 24
Peak memory 201664 kb
Host smart-aa85d3d1-202b-4949-af15-9171102bd07e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678465778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2678465778
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.525194124
Short name T819
Test name
Test status
Simulation time 484954138 ps
CPU time 1.17 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:25 PM PDT 24
Peak memory 201296 kb
Host smart-88f68e68-57ca-4a14-a633-78230098f220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525194124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.525194124
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.79763696
Short name T881
Test name
Test status
Simulation time 622970136 ps
CPU time 0.73 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:23 PM PDT 24
Peak memory 201312 kb
Host smart-f9afb38e-7466-4272-bc01-43e90c40b76c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79763696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.79763696
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.74625716
Short name T799
Test name
Test status
Simulation time 469479668 ps
CPU time 1.82 seconds
Started Aug 09 05:53:28 PM PDT 24
Finished Aug 09 05:53:30 PM PDT 24
Peak memory 201348 kb
Host smart-add87b51-5973-4341-9663-732aff476126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74625716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.74625716
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3513085057
Short name T890
Test name
Test status
Simulation time 415277326 ps
CPU time 0.92 seconds
Started Aug 09 05:53:22 PM PDT 24
Finished Aug 09 05:53:23 PM PDT 24
Peak memory 201368 kb
Host smart-19eca523-464c-4535-8242-a14583b1c0ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513085057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3513085057
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2230903457
Short name T896
Test name
Test status
Simulation time 424512453 ps
CPU time 1.59 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:25 PM PDT 24
Peak memory 201372 kb
Host smart-57be416e-9306-4a78-89bf-82c20ea673c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230903457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2230903457
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3571295557
Short name T842
Test name
Test status
Simulation time 355649842 ps
CPU time 1.5 seconds
Started Aug 09 05:53:25 PM PDT 24
Finished Aug 09 05:53:27 PM PDT 24
Peak memory 201296 kb
Host smart-a647ac28-2973-4ac7-bbf9-695e12dae1e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571295557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3571295557
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2909341314
Short name T871
Test name
Test status
Simulation time 418030109 ps
CPU time 1.49 seconds
Started Aug 09 05:53:23 PM PDT 24
Finished Aug 09 05:53:25 PM PDT 24
Peak memory 201196 kb
Host smart-a67b2fb7-91dc-4a13-881f-ad10bfb874c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909341314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2909341314
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.389466084
Short name T840
Test name
Test status
Simulation time 319893872 ps
CPU time 0.89 seconds
Started Aug 09 05:53:24 PM PDT 24
Finished Aug 09 05:53:25 PM PDT 24
Peak memory 201352 kb
Host smart-692fe3d0-c444-4fb5-9d6b-98678a4ba55e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389466084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.389466084
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.327175060
Short name T902
Test name
Test status
Simulation time 472525659 ps
CPU time 1.78 seconds
Started Aug 09 05:53:25 PM PDT 24
Finished Aug 09 05:53:26 PM PDT 24
Peak memory 201312 kb
Host smart-4018cf00-ec17-4a2b-9cee-20f1a9393e4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327175060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.327175060
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.198329779
Short name T877
Test name
Test status
Simulation time 293643826 ps
CPU time 1.31 seconds
Started Aug 09 05:53:21 PM PDT 24
Finished Aug 09 05:53:22 PM PDT 24
Peak memory 201248 kb
Host smart-466fcc45-c64f-409c-8f88-14a25191ae0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198329779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.198329779
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2310197795
Short name T849
Test name
Test status
Simulation time 466773230 ps
CPU time 1.4 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:13 PM PDT 24
Peak memory 201508 kb
Host smart-1a382e12-0ff0-445b-9d9b-1267283e6d41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310197795 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2310197795
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4211943712
Short name T107
Test name
Test status
Simulation time 588913870 ps
CPU time 1.13 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:53:12 PM PDT 24
Peak memory 201328 kb
Host smart-2f60dbc0-5db8-471b-afcd-f75b67c35af2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211943712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4211943712
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4023890004
Short name T805
Test name
Test status
Simulation time 475972768 ps
CPU time 1.73 seconds
Started Aug 09 05:53:15 PM PDT 24
Finished Aug 09 05:53:17 PM PDT 24
Peak memory 201232 kb
Host smart-e516d086-a458-4df3-92bd-1cab77c426d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023890004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.4023890004
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.595301458
Short name T810
Test name
Test status
Simulation time 5624401176 ps
CPU time 6.98 seconds
Started Aug 09 05:53:19 PM PDT 24
Finished Aug 09 05:53:26 PM PDT 24
Peak memory 201572 kb
Host smart-97b529db-0e47-4c20-9d58-1fd039f068bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595301458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.595301458
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3355226498
Short name T814
Test name
Test status
Simulation time 602764534 ps
CPU time 3.78 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:17 PM PDT 24
Peak memory 210844 kb
Host smart-0aa98578-32d1-4bcf-ad1a-1b102ed61384
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355226498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3355226498
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1112294284
Short name T322
Test name
Test status
Simulation time 7737705167 ps
CPU time 14.81 seconds
Started Aug 09 05:53:14 PM PDT 24
Finished Aug 09 05:53:29 PM PDT 24
Peak memory 201640 kb
Host smart-096408dc-b48a-4f53-b67c-48391869092c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112294284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1112294284
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2209416106
Short name T78
Test name
Test status
Simulation time 567129614 ps
CPU time 0.96 seconds
Started Aug 09 05:53:10 PM PDT 24
Finished Aug 09 05:53:11 PM PDT 24
Peak memory 201504 kb
Host smart-ee09aba2-5db6-4ac5-b889-8ac42d07fd96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209416106 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2209416106
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2808760699
Short name T113
Test name
Test status
Simulation time 361378720 ps
CPU time 1.57 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 201324 kb
Host smart-104687d6-2074-467d-a1ce-78bc0d29342d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808760699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2808760699
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3945946178
Short name T865
Test name
Test status
Simulation time 465333441 ps
CPU time 0.89 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:14 PM PDT 24
Peak memory 201344 kb
Host smart-2580fa88-a4cc-40b9-93ec-27b84dad64fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945946178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3945946178
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2899416462
Short name T858
Test name
Test status
Simulation time 4334937357 ps
CPU time 3.48 seconds
Started Aug 09 05:53:10 PM PDT 24
Finished Aug 09 05:53:14 PM PDT 24
Peak memory 201472 kb
Host smart-c980ce86-e504-4a29-9733-77221721c7c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899416462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2899416462
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1967893794
Short name T73
Test name
Test status
Simulation time 766164930 ps
CPU time 3.06 seconds
Started Aug 09 05:53:14 PM PDT 24
Finished Aug 09 05:53:17 PM PDT 24
Peak memory 201616 kb
Host smart-5393498d-30a3-4da8-b94b-76db2b715c80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967893794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1967893794
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1848622406
Short name T320
Test name
Test status
Simulation time 8275495260 ps
CPU time 19.84 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:32 PM PDT 24
Peak memory 201628 kb
Host smart-0802cdb8-c3b0-46be-83f0-f92ee9a28e31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848622406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1848622406
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.456537971
Short name T879
Test name
Test status
Simulation time 419719269 ps
CPU time 1.67 seconds
Started Aug 09 05:53:09 PM PDT 24
Finished Aug 09 05:53:11 PM PDT 24
Peak memory 201392 kb
Host smart-4df63aa1-8d2f-4a68-bc55-efa18d3cad06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456537971 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.456537971
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3905564540
Short name T109
Test name
Test status
Simulation time 483322165 ps
CPU time 0.91 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:13 PM PDT 24
Peak memory 201156 kb
Host smart-4ce3d218-c9b4-48b1-b30a-1d56086927bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905564540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3905564540
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.472981639
Short name T912
Test name
Test status
Simulation time 429129987 ps
CPU time 1.5 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:53:13 PM PDT 24
Peak memory 201268 kb
Host smart-c4b6f147-8f5f-4d8a-94a5-25df6f8dd3e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472981639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.472981639
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.172141369
Short name T897
Test name
Test status
Simulation time 2052233574 ps
CPU time 2.57 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 201344 kb
Host smart-fdbe48dd-1ca6-4b09-b8c8-f27087c1fccc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172141369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.172141369
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2254881188
Short name T876
Test name
Test status
Simulation time 558071481 ps
CPU time 1.72 seconds
Started Aug 09 05:53:17 PM PDT 24
Finished Aug 09 05:53:18 PM PDT 24
Peak memory 201640 kb
Host smart-b00da6d0-00c0-4da5-9d0e-5db9a20ea210
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254881188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2254881188
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3603232119
Short name T321
Test name
Test status
Simulation time 4077746352 ps
CPU time 3.49 seconds
Started Aug 09 05:53:10 PM PDT 24
Finished Aug 09 05:53:13 PM PDT 24
Peak memory 201560 kb
Host smart-4939391e-c6fe-4426-89e1-6ab5ff1f409c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603232119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3603232119
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3108096674
Short name T908
Test name
Test status
Simulation time 420328762 ps
CPU time 1.95 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:14 PM PDT 24
Peak memory 201516 kb
Host smart-ac9a54cf-8167-433e-8f8b-9504afcd8e37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108096674 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3108096674
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3126287757
Short name T903
Test name
Test status
Simulation time 406701809 ps
CPU time 1.86 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:53:13 PM PDT 24
Peak memory 201356 kb
Host smart-d392233d-2a2f-4c87-b099-aec5b294f0eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126287757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3126287757
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3924969874
Short name T875
Test name
Test status
Simulation time 364769834 ps
CPU time 1.02 seconds
Started Aug 09 05:53:14 PM PDT 24
Finished Aug 09 05:53:15 PM PDT 24
Peak memory 201292 kb
Host smart-9b71baf0-6718-49b8-8f74-3e105a041c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924969874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3924969874
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3137047919
Short name T837
Test name
Test status
Simulation time 2492379908 ps
CPU time 5.92 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:18 PM PDT 24
Peak memory 201244 kb
Host smart-3dad5a0a-b66a-43d1-a733-885c1460a255
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137047919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3137047919
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1957253368
Short name T887
Test name
Test status
Simulation time 4397246345 ps
CPU time 6.41 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:19 PM PDT 24
Peak memory 201668 kb
Host smart-75594996-5470-48aa-97b6-0a6b027cd3e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957253368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1957253368
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2213774087
Short name T86
Test name
Test status
Simulation time 447094542 ps
CPU time 0.97 seconds
Started Aug 09 05:53:13 PM PDT 24
Finished Aug 09 05:53:14 PM PDT 24
Peak memory 201436 kb
Host smart-293c1b7a-330a-4a80-813f-3730bf083541
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213774087 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2213774087
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3880581591
Short name T106
Test name
Test status
Simulation time 538757637 ps
CPU time 1.39 seconds
Started Aug 09 05:53:09 PM PDT 24
Finished Aug 09 05:53:10 PM PDT 24
Peak memory 201300 kb
Host smart-3c9830d5-fcc3-40db-8427-17a034973e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880581591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3880581591
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2717040290
Short name T893
Test name
Test status
Simulation time 442475733 ps
CPU time 0.81 seconds
Started Aug 09 05:53:17 PM PDT 24
Finished Aug 09 05:53:18 PM PDT 24
Peak memory 201348 kb
Host smart-47155176-61e4-4f85-9811-880c7e94eb14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717040290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2717040290
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.907978972
Short name T917
Test name
Test status
Simulation time 3892411623 ps
CPU time 8.52 seconds
Started Aug 09 05:53:12 PM PDT 24
Finished Aug 09 05:53:20 PM PDT 24
Peak memory 201636 kb
Host smart-2f426b73-db24-454d-b1cb-799a4d3c7e30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907978972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.907978972
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2083619106
Short name T911
Test name
Test status
Simulation time 634631372 ps
CPU time 1.77 seconds
Started Aug 09 05:53:15 PM PDT 24
Finished Aug 09 05:53:17 PM PDT 24
Peak memory 201640 kb
Host smart-1a19f931-869e-473a-949a-8016067a7a34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083619106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2083619106
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2288988170
Short name T69
Test name
Test status
Simulation time 3982552817 ps
CPU time 11.06 seconds
Started Aug 09 05:53:11 PM PDT 24
Finished Aug 09 05:53:22 PM PDT 24
Peak memory 201504 kb
Host smart-65eb2ee2-84dd-4f90-bc13-51c6ad79232e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288988170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2288988170
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1297147787
Short name T597
Test name
Test status
Simulation time 508736059 ps
CPU time 0.81 seconds
Started Aug 09 05:34:58 PM PDT 24
Finished Aug 09 05:34:58 PM PDT 24
Peak memory 201132 kb
Host smart-85be277f-a09f-46fc-983b-fbe92a80a442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297147787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1297147787
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2564361974
Short name T659
Test name
Test status
Simulation time 179376336543 ps
CPU time 100.81 seconds
Started Aug 09 05:34:59 PM PDT 24
Finished Aug 09 05:36:40 PM PDT 24
Peak memory 201372 kb
Host smart-ace0552e-5a1f-4055-a551-31495f9111f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564361974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2564361974
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.4235827911
Short name T218
Test name
Test status
Simulation time 502114510380 ps
CPU time 1182.17 seconds
Started Aug 09 05:34:59 PM PDT 24
Finished Aug 09 05:54:41 PM PDT 24
Peak memory 201444 kb
Host smart-d89aa822-4352-411e-a41b-83587b33b32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235827911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.4235827911
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1316801076
Short name T501
Test name
Test status
Simulation time 493766168755 ps
CPU time 227.12 seconds
Started Aug 09 05:34:46 PM PDT 24
Finished Aug 09 05:38:33 PM PDT 24
Peak memory 201372 kb
Host smart-07029f61-6e8e-43c0-84a0-8bb052032715
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316801076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1316801076
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2462467009
Short name T439
Test name
Test status
Simulation time 162635569994 ps
CPU time 62.17 seconds
Started Aug 09 05:34:49 PM PDT 24
Finished Aug 09 05:35:51 PM PDT 24
Peak memory 201444 kb
Host smart-1e74886b-96ba-4180-8f2a-d5ca35862a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462467009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2462467009
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2601502731
Short name T469
Test name
Test status
Simulation time 336723064961 ps
CPU time 208.93 seconds
Started Aug 09 05:34:49 PM PDT 24
Finished Aug 09 05:38:18 PM PDT 24
Peak memory 201424 kb
Host smart-296dc418-f614-4504-a647-ba36b8dbf7c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601502731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2601502731
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2110039274
Short name T756
Test name
Test status
Simulation time 408449974097 ps
CPU time 487.73 seconds
Started Aug 09 05:35:07 PM PDT 24
Finished Aug 09 05:43:15 PM PDT 24
Peak memory 201448 kb
Host smart-d015917f-db40-437f-ac0d-a374500d430f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110039274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2110039274
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1266928089
Short name T184
Test name
Test status
Simulation time 80163212458 ps
CPU time 276.5 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:39:40 PM PDT 24
Peak memory 201752 kb
Host smart-0d720f49-a601-4a04-9b0c-5a410be0489c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266928089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1266928089
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.4224985370
Short name T41
Test name
Test status
Simulation time 42559495122 ps
CPU time 95.73 seconds
Started Aug 09 05:34:53 PM PDT 24
Finished Aug 09 05:36:29 PM PDT 24
Peak memory 201336 kb
Host smart-7821fd96-a4c3-4d25-862d-1edfa102884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224985370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.4224985370
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.810840979
Short name T603
Test name
Test status
Simulation time 3936085449 ps
CPU time 3.3 seconds
Started Aug 09 05:35:00 PM PDT 24
Finished Aug 09 05:35:03 PM PDT 24
Peak memory 201208 kb
Host smart-43b4d013-3a37-4a3d-a29b-72cd76efe3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810840979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.810840979
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3873762557
Short name T71
Test name
Test status
Simulation time 7801555982 ps
CPU time 9.12 seconds
Started Aug 09 05:35:00 PM PDT 24
Finished Aug 09 05:35:09 PM PDT 24
Peak memory 218180 kb
Host smart-ffddffeb-147a-4654-ac7c-9b11f5234f65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873762557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3873762557
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1876077727
Short name T758
Test name
Test status
Simulation time 5479153898 ps
CPU time 12.59 seconds
Started Aug 09 05:35:01 PM PDT 24
Finished Aug 09 05:35:14 PM PDT 24
Peak memory 201320 kb
Host smart-8797bae4-0442-4669-9608-6e396c0635d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876077727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1876077727
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2818727799
Short name T148
Test name
Test status
Simulation time 345710385871 ps
CPU time 833.13 seconds
Started Aug 09 05:34:44 PM PDT 24
Finished Aug 09 05:48:37 PM PDT 24
Peak memory 201512 kb
Host smart-aa38a574-e3cb-4064-a297-7b5c168d59cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818727799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2818727799
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3906626289
Short name T96
Test name
Test status
Simulation time 59331206031 ps
CPU time 139.38 seconds
Started Aug 09 05:35:00 PM PDT 24
Finished Aug 09 05:37:20 PM PDT 24
Peak memory 209788 kb
Host smart-4172dca0-cb73-4028-91e3-e905d54c9751
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906626289 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3906626289
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3159480389
Short name T402
Test name
Test status
Simulation time 405952774 ps
CPU time 0.85 seconds
Started Aug 09 05:35:02 PM PDT 24
Finished Aug 09 05:35:03 PM PDT 24
Peak memory 201132 kb
Host smart-3e2f879c-c361-4650-84ea-3be7e33f12e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159480389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3159480389
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.4228537819
Short name T101
Test name
Test status
Simulation time 195795410089 ps
CPU time 130.77 seconds
Started Aug 09 05:35:03 PM PDT 24
Finished Aug 09 05:37:13 PM PDT 24
Peak memory 201396 kb
Host smart-fe4d5d7f-f98c-4358-8fd8-d04fdb6456dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228537819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.4228537819
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3452609031
Short name T153
Test name
Test status
Simulation time 489458204941 ps
CPU time 1156.28 seconds
Started Aug 09 05:34:53 PM PDT 24
Finished Aug 09 05:54:15 PM PDT 24
Peak memory 201372 kb
Host smart-0de74932-6888-4237-b24c-f7b8a130c3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452609031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3452609031
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.64387219
Short name T572
Test name
Test status
Simulation time 165931324940 ps
CPU time 103.27 seconds
Started Aug 09 05:35:02 PM PDT 24
Finished Aug 09 05:36:46 PM PDT 24
Peak memory 201372 kb
Host smart-8c1d6ede-4056-4636-a78f-8897925c6d03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=64387219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt_
fixed.64387219
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3210464040
Short name T130
Test name
Test status
Simulation time 493736133902 ps
CPU time 160.54 seconds
Started Aug 09 05:34:53 PM PDT 24
Finished Aug 09 05:37:34 PM PDT 24
Peak memory 201440 kb
Host smart-cb448dfc-fc20-468f-88d3-d0bcd33ca348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210464040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3210464040
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2416575805
Short name T344
Test name
Test status
Simulation time 321976348044 ps
CPU time 181.66 seconds
Started Aug 09 05:35:06 PM PDT 24
Finished Aug 09 05:38:08 PM PDT 24
Peak memory 201376 kb
Host smart-1ab4ceea-f44f-4cdc-b143-7631148d9a63
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416575805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2416575805
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1738414507
Short name T390
Test name
Test status
Simulation time 177077948797 ps
CPU time 53.36 seconds
Started Aug 09 05:35:02 PM PDT 24
Finished Aug 09 05:35:55 PM PDT 24
Peak memory 201336 kb
Host smart-7ee2cbee-6527-4580-9b6e-2c06bd8eb1f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738414507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1738414507
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2201637527
Short name T646
Test name
Test status
Simulation time 609902909727 ps
CPU time 1450.08 seconds
Started Aug 09 05:35:11 PM PDT 24
Finished Aug 09 05:59:22 PM PDT 24
Peak memory 201388 kb
Host smart-23523ee2-3b79-442e-bf1f-11396cbf786e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201637527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2201637527
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1578031509
Short name T557
Test name
Test status
Simulation time 36259940960 ps
CPU time 21.91 seconds
Started Aug 09 05:34:49 PM PDT 24
Finished Aug 09 05:35:11 PM PDT 24
Peak memory 201352 kb
Host smart-16e8460c-098a-4c88-a07b-794dea08560d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578031509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1578031509
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.949868307
Short name T476
Test name
Test status
Simulation time 5434002014 ps
CPU time 13.62 seconds
Started Aug 09 05:35:07 PM PDT 24
Finished Aug 09 05:35:21 PM PDT 24
Peak memory 201288 kb
Host smart-d5f0a52f-f909-4bb4-8fa8-7816d8dd062e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949868307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.949868307
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.550011358
Short name T492
Test name
Test status
Simulation time 6052326712 ps
CPU time 1.84 seconds
Started Aug 09 05:34:53 PM PDT 24
Finished Aug 09 05:34:55 PM PDT 24
Peak memory 201364 kb
Host smart-7997e9ee-db7a-4645-8bb1-f1806c2d391b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550011358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.550011358
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3775725947
Short name T644
Test name
Test status
Simulation time 330870462226 ps
CPU time 182.18 seconds
Started Aug 09 05:34:50 PM PDT 24
Finished Aug 09 05:37:52 PM PDT 24
Peak memory 201336 kb
Host smart-5c008e45-3e17-4c86-93df-cfbe178d6444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775725947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3775725947
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.975225401
Short name T500
Test name
Test status
Simulation time 103974621642 ps
CPU time 55.97 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:36:13 PM PDT 24
Peak memory 209736 kb
Host smart-bfb583b6-9f76-45d5-a4cd-02f416881419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975225401 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.975225401
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2565628156
Short name T376
Test name
Test status
Simulation time 556624985 ps
CPU time 0.93 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:35:15 PM PDT 24
Peak memory 201252 kb
Host smart-3f3eaa68-55c4-440a-a9ad-8214aa692e57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565628156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2565628156
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.902241748
Short name T167
Test name
Test status
Simulation time 357911604112 ps
CPU time 735.78 seconds
Started Aug 09 05:35:15 PM PDT 24
Finished Aug 09 05:47:31 PM PDT 24
Peak memory 201460 kb
Host smart-5f5da981-baa2-4317-8de8-259ab167debe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902241748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.902241748
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2083016444
Short name T607
Test name
Test status
Simulation time 163139658977 ps
CPU time 352.8 seconds
Started Aug 09 05:35:06 PM PDT 24
Finished Aug 09 05:40:59 PM PDT 24
Peak memory 201360 kb
Host smart-0a159843-f14c-4e1a-89fa-b90b636a8070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083016444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2083016444
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3692875151
Short name T212
Test name
Test status
Simulation time 330324728005 ps
CPU time 803.09 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:48:40 PM PDT 24
Peak memory 201448 kb
Host smart-70bc860f-380a-4bd4-a4fb-14dc6f77f1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692875151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3692875151
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1088545740
Short name T585
Test name
Test status
Simulation time 167067121282 ps
CPU time 42.01 seconds
Started Aug 09 05:35:15 PM PDT 24
Finished Aug 09 05:35:57 PM PDT 24
Peak memory 201412 kb
Host smart-e0c51a1a-5853-49e5-b2ea-c452cd20d30f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088545740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1088545740
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2707255490
Short name T543
Test name
Test status
Simulation time 491946607233 ps
CPU time 617.85 seconds
Started Aug 09 05:35:18 PM PDT 24
Finished Aug 09 05:45:36 PM PDT 24
Peak memory 201444 kb
Host smart-743b7c6c-eafe-4407-84d2-52bebbb4360f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707255490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2707255490
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2443516639
Short name T493
Test name
Test status
Simulation time 495536819356 ps
CPU time 258.12 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:39:43 PM PDT 24
Peak memory 201388 kb
Host smart-6607412f-f90c-4520-afff-2225655b4fd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443516639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2443516639
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.555067299
Short name T574
Test name
Test status
Simulation time 191818781621 ps
CPU time 109.63 seconds
Started Aug 09 05:35:21 PM PDT 24
Finished Aug 09 05:37:11 PM PDT 24
Peak memory 201364 kb
Host smart-c5603eb5-a3f1-4733-98be-74af0282f351
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555067299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.555067299
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.377792611
Short name T569
Test name
Test status
Simulation time 88068803310 ps
CPU time 310.6 seconds
Started Aug 09 05:35:09 PM PDT 24
Finished Aug 09 05:40:20 PM PDT 24
Peak memory 201696 kb
Host smart-904d9598-f454-430d-82e6-0c56a7c1cca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377792611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.377792611
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.4082057004
Short name T539
Test name
Test status
Simulation time 36939091706 ps
CPU time 22.85 seconds
Started Aug 09 05:35:07 PM PDT 24
Finished Aug 09 05:35:32 PM PDT 24
Peak memory 201356 kb
Host smart-05b00b4e-bb71-495b-b695-d8a088cbc09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082057004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.4082057004
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.190663580
Short name T347
Test name
Test status
Simulation time 4284454336 ps
CPU time 5.8 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:35:23 PM PDT 24
Peak memory 201524 kb
Host smart-983b8725-cfcd-4d37-8327-5e6e27ac081b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190663580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.190663580
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.231487695
Short name T498
Test name
Test status
Simulation time 5610610575 ps
CPU time 7.06 seconds
Started Aug 09 05:35:11 PM PDT 24
Finished Aug 09 05:35:18 PM PDT 24
Peak memory 201284 kb
Host smart-c44e1878-283e-4e99-8687-6a12bd233ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231487695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.231487695
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3770814361
Short name T85
Test name
Test status
Simulation time 270566250461 ps
CPU time 396.05 seconds
Started Aug 09 05:35:28 PM PDT 24
Finished Aug 09 05:42:04 PM PDT 24
Peak memory 210128 kb
Host smart-5e03c835-cec2-4332-8bc2-222215ed50ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770814361 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3770814361
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1224498346
Short name T541
Test name
Test status
Simulation time 528032976 ps
CPU time 0.93 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:35:13 PM PDT 24
Peak memory 201252 kb
Host smart-50b6109e-302f-4656-a905-e68c1f86f31c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224498346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1224498346
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2508096712
Short name T242
Test name
Test status
Simulation time 161190620987 ps
CPU time 111.46 seconds
Started Aug 09 05:35:07 PM PDT 24
Finished Aug 09 05:36:58 PM PDT 24
Peak memory 201460 kb
Host smart-9cfe1bfa-71ba-4f77-9fd1-70aa2f883a5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508096712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2508096712
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2305835408
Short name T595
Test name
Test status
Simulation time 534934697111 ps
CPU time 289.72 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:39:54 PM PDT 24
Peak memory 201372 kb
Host smart-1f1d272a-7548-4eb5-b85c-99d99b027cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305835408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2305835408
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2151857972
Short name T764
Test name
Test status
Simulation time 323499532217 ps
CPU time 758 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:47:55 PM PDT 24
Peak memory 201424 kb
Host smart-24feac4a-d8d8-4959-88d4-18be3e3f2a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151857972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2151857972
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3470579760
Short name T375
Test name
Test status
Simulation time 160296861512 ps
CPU time 257.47 seconds
Started Aug 09 05:35:16 PM PDT 24
Finished Aug 09 05:39:34 PM PDT 24
Peak memory 201372 kb
Host smart-5bcf7a9b-cb2f-45da-ad6e-91ab7d00ee9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470579760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3470579760
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2670541074
Short name T525
Test name
Test status
Simulation time 166021852385 ps
CPU time 357.19 seconds
Started Aug 09 05:35:15 PM PDT 24
Finished Aug 09 05:41:12 PM PDT 24
Peak memory 201364 kb
Host smart-95909408-d3bb-4bfd-b3bc-5712ae89beb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670541074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2670541074
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3758573755
Short name T712
Test name
Test status
Simulation time 498907168608 ps
CPU time 351.38 seconds
Started Aug 09 05:35:07 PM PDT 24
Finished Aug 09 05:41:03 PM PDT 24
Peak memory 201340 kb
Host smart-1fc97757-cfe1-4176-83d5-ae06d6210342
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758573755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3758573755
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3546990718
Short name T284
Test name
Test status
Simulation time 455212018031 ps
CPU time 949.03 seconds
Started Aug 09 05:35:05 PM PDT 24
Finished Aug 09 05:50:55 PM PDT 24
Peak memory 201368 kb
Host smart-64083f72-e09e-429d-9fba-523955aee2c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546990718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3546990718
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.4078910322
Short name T352
Test name
Test status
Simulation time 209211864349 ps
CPU time 478.57 seconds
Started Aug 09 05:35:30 PM PDT 24
Finished Aug 09 05:43:28 PM PDT 24
Peak memory 201324 kb
Host smart-124ae8df-d2eb-4a4a-8c32-b16dde273d94
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078910322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.4078910322
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.77335234
Short name T170
Test name
Test status
Simulation time 89281956803 ps
CPU time 483.52 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:43:16 PM PDT 24
Peak memory 201704 kb
Host smart-6b5c8757-5540-4269-b2a1-b06866a13489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77335234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.77335234
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1928873025
Short name T710
Test name
Test status
Simulation time 36518859122 ps
CPU time 8.76 seconds
Started Aug 09 05:35:23 PM PDT 24
Finished Aug 09 05:35:31 PM PDT 24
Peak memory 201340 kb
Host smart-2a09069e-de1c-4a8f-8cdb-a85f5b2deeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928873025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1928873025
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3392330299
Short name T639
Test name
Test status
Simulation time 3003152687 ps
CPU time 8.43 seconds
Started Aug 09 05:35:08 PM PDT 24
Finished Aug 09 05:35:17 PM PDT 24
Peak memory 201308 kb
Host smart-d08596d3-b7f2-42bf-8bf9-6feb221ba0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392330299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3392330299
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1846965505
Short name T461
Test name
Test status
Simulation time 5897806632 ps
CPU time 15.05 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:35:27 PM PDT 24
Peak memory 201316 kb
Host smart-4249b444-d7a4-4610-952b-bf55bed12c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846965505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1846965505
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3107338594
Short name T560
Test name
Test status
Simulation time 167819832986 ps
CPU time 373.68 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:41:31 PM PDT 24
Peak memory 201504 kb
Host smart-cb301c1f-874b-4407-8060-beb21410476f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107338594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3107338594
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.395907309
Short name T629
Test name
Test status
Simulation time 55879764106 ps
CPU time 134.5 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:37:32 PM PDT 24
Peak memory 218036 kb
Host smart-2b7e6cef-f855-40a0-8e3d-62cb5aed72b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395907309 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.395907309
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1351317669
Short name T373
Test name
Test status
Simulation time 429215487 ps
CPU time 1.43 seconds
Started Aug 09 05:35:20 PM PDT 24
Finished Aug 09 05:35:22 PM PDT 24
Peak memory 201248 kb
Host smart-691a5962-c426-4eeb-b49e-14edbe35b57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351317669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1351317669
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1689259105
Short name T238
Test name
Test status
Simulation time 161990517430 ps
CPU time 20.8 seconds
Started Aug 09 05:35:15 PM PDT 24
Finished Aug 09 05:35:36 PM PDT 24
Peak memory 201416 kb
Host smart-95214947-f393-4fdb-81c5-a78750b3cb00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689259105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1689259105
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3905483417
Short name T235
Test name
Test status
Simulation time 178907451310 ps
CPU time 209.34 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:38:47 PM PDT 24
Peak memory 201424 kb
Host smart-7e5202a8-d816-435b-b205-2559b4f82d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905483417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3905483417
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3271031260
Short name T655
Test name
Test status
Simulation time 325978836687 ps
CPU time 765.85 seconds
Started Aug 09 05:35:28 PM PDT 24
Finished Aug 09 05:48:14 PM PDT 24
Peak memory 201440 kb
Host smart-57f701eb-2396-402f-b6a7-0f56fe0f452a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271031260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3271031260
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.4036967756
Short name T363
Test name
Test status
Simulation time 160799586957 ps
CPU time 348.57 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:40:52 PM PDT 24
Peak memory 201344 kb
Host smart-5dbd2085-b71d-409c-827e-045c4a1fb484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036967756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.4036967756
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3493955988
Short name T536
Test name
Test status
Simulation time 489920914307 ps
CPU time 1105.84 seconds
Started Aug 09 05:35:20 PM PDT 24
Finished Aug 09 05:53:46 PM PDT 24
Peak memory 201324 kb
Host smart-545cb1f9-0504-4a57-bbc9-beb120e161d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493955988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3493955988
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3682872047
Short name T737
Test name
Test status
Simulation time 685674373197 ps
CPU time 1629.09 seconds
Started Aug 09 05:35:09 PM PDT 24
Finished Aug 09 06:02:18 PM PDT 24
Peak memory 201412 kb
Host smart-873745ae-3d61-49b0-8230-8b90f0d2a2f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682872047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3682872047
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.613827995
Short name T502
Test name
Test status
Simulation time 393433178293 ps
CPU time 213.8 seconds
Started Aug 09 05:35:03 PM PDT 24
Finished Aug 09 05:38:37 PM PDT 24
Peak memory 201476 kb
Host smart-8b481d9a-ebfd-43ab-b0a6-12859bb0806d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613827995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.613827995
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.643549647
Short name T329
Test name
Test status
Simulation time 82876326651 ps
CPU time 294.98 seconds
Started Aug 09 05:35:11 PM PDT 24
Finished Aug 09 05:40:06 PM PDT 24
Peak memory 201740 kb
Host smart-d0147024-1d8c-4a1b-8423-3b1f11118ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643549647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.643549647
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.262455679
Short name T645
Test name
Test status
Simulation time 45066261859 ps
CPU time 27.04 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:35:39 PM PDT 24
Peak memory 201284 kb
Host smart-d7d0249e-a18a-483f-9ee5-a6fbe5692a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262455679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.262455679
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3917950386
Short name T600
Test name
Test status
Simulation time 4163711180 ps
CPU time 3.4 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:35:21 PM PDT 24
Peak memory 201348 kb
Host smart-437303d8-a7c8-444f-bb99-4dac7dc56c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917950386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3917950386
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.768426203
Short name T763
Test name
Test status
Simulation time 6045844234 ps
CPU time 4.05 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:35:21 PM PDT 24
Peak memory 201312 kb
Host smart-cccf386d-1ae8-4a16-ba62-681f54bcbd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768426203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.768426203
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.631739712
Short name T264
Test name
Test status
Simulation time 674597704205 ps
CPU time 809.67 seconds
Started Aug 09 05:35:18 PM PDT 24
Finished Aug 09 05:48:48 PM PDT 24
Peak memory 201456 kb
Host smart-3ad88d89-0151-4dc7-ae01-19c95fec1f96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631739712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
631739712
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1891381517
Short name T740
Test name
Test status
Simulation time 20132815655 ps
CPU time 85.89 seconds
Started Aug 09 05:35:05 PM PDT 24
Finished Aug 09 05:36:31 PM PDT 24
Peak memory 210112 kb
Host smart-b558e0ee-a7f1-4ee5-82a7-ead2bfce4c04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891381517 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1891381517
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3809988457
Short name T727
Test name
Test status
Simulation time 161229194643 ps
CPU time 78.38 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:36:33 PM PDT 24
Peak memory 201472 kb
Host smart-888f6028-1338-4626-b00f-16f7c46eb3ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809988457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3809988457
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3890680857
Short name T612
Test name
Test status
Simulation time 160734202427 ps
CPU time 104.93 seconds
Started Aug 09 05:35:24 PM PDT 24
Finished Aug 09 05:37:09 PM PDT 24
Peak memory 201464 kb
Host smart-881ba8cd-d98c-47e1-86fd-6fc11b33d8b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890680857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3890680857
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3363157252
Short name T303
Test name
Test status
Simulation time 165226228345 ps
CPU time 192.88 seconds
Started Aug 09 05:35:20 PM PDT 24
Finished Aug 09 05:38:33 PM PDT 24
Peak memory 201304 kb
Host smart-e6f5cd2d-2f7e-4145-ad7f-037f6142c9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363157252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3363157252
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3711985632
Short name T418
Test name
Test status
Simulation time 333661929010 ps
CPU time 721.2 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:47:26 PM PDT 24
Peak memory 201364 kb
Host smart-e04d3926-630e-4077-9a13-cb2e214cc3a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711985632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3711985632
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3560332033
Short name T194
Test name
Test status
Simulation time 178664108722 ps
CPU time 89.28 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:36:47 PM PDT 24
Peak memory 201348 kb
Host smart-92910040-f8f2-4abc-a730-b0832679c2fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560332033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3560332033
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2123259407
Short name T511
Test name
Test status
Simulation time 614176049199 ps
CPU time 335.58 seconds
Started Aug 09 05:35:23 PM PDT 24
Finished Aug 09 05:40:59 PM PDT 24
Peak memory 201448 kb
Host smart-59b700c3-df3e-4f38-b188-64dc5d95715d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123259407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2123259407
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.515043243
Short name T326
Test name
Test status
Simulation time 108895132268 ps
CPU time 365.51 seconds
Started Aug 09 05:35:15 PM PDT 24
Finished Aug 09 05:41:21 PM PDT 24
Peak memory 201904 kb
Host smart-dbcb2179-faa4-423b-ad72-f5ac2738af17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515043243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.515043243
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3210811616
Short name T700
Test name
Test status
Simulation time 22589116026 ps
CPU time 13.39 seconds
Started Aug 09 05:35:19 PM PDT 24
Finished Aug 09 05:35:32 PM PDT 24
Peak memory 201272 kb
Host smart-f93c47a8-311c-4c57-aaf8-182cf8d8d7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210811616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3210811616
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1353674875
Short name T482
Test name
Test status
Simulation time 3984801615 ps
CPU time 3.07 seconds
Started Aug 09 05:35:21 PM PDT 24
Finished Aug 09 05:35:25 PM PDT 24
Peak memory 201356 kb
Host smart-f753d7bc-8e64-46b2-ad7b-3acdb83c2ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353674875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1353674875
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.669990139
Short name T334
Test name
Test status
Simulation time 5776173038 ps
CPU time 3.97 seconds
Started Aug 09 05:35:16 PM PDT 24
Finished Aug 09 05:35:20 PM PDT 24
Peak memory 201328 kb
Host smart-f95d1ffd-21d6-4137-b2d3-c13ba904ac05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669990139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.669990139
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3112659636
Short name T75
Test name
Test status
Simulation time 520878246 ps
CPU time 0.93 seconds
Started Aug 09 05:35:19 PM PDT 24
Finished Aug 09 05:35:20 PM PDT 24
Peak memory 201176 kb
Host smart-48ac24ed-05d7-4275-a6c9-36c7e2808988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112659636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3112659636
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3528291437
Short name T144
Test name
Test status
Simulation time 391230741678 ps
CPU time 185.12 seconds
Started Aug 09 05:35:15 PM PDT 24
Finished Aug 09 05:38:20 PM PDT 24
Peak memory 201440 kb
Host smart-ab36e981-6d2b-4be1-86ea-264353eb5631
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528291437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3528291437
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2914928848
Short name T257
Test name
Test status
Simulation time 349384384076 ps
CPU time 220.88 seconds
Started Aug 09 05:35:32 PM PDT 24
Finished Aug 09 05:39:13 PM PDT 24
Peak memory 201380 kb
Host smart-a4767e2b-9a57-445c-8897-d0c232a7e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914928848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2914928848
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.4005527265
Short name T720
Test name
Test status
Simulation time 169165290017 ps
CPU time 208.5 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:38:42 PM PDT 24
Peak memory 201476 kb
Host smart-6722fcf5-ca67-4bb0-bd08-e1b827be7e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005527265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.4005527265
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1475563310
Short name T642
Test name
Test status
Simulation time 480636251291 ps
CPU time 543.98 seconds
Started Aug 09 05:35:26 PM PDT 24
Finished Aug 09 05:44:31 PM PDT 24
Peak memory 201524 kb
Host smart-efe12760-a97a-45f9-b236-1208034d15fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475563310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1475563310
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3235208465
Short name T586
Test name
Test status
Simulation time 484991399576 ps
CPU time 600.65 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:45:26 PM PDT 24
Peak memory 201456 kb
Host smart-0e2d7e88-9cc3-459c-9ad8-682549cb94e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235208465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3235208465
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2832316642
Short name T787
Test name
Test status
Simulation time 331199411876 ps
CPU time 42.86 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:35:57 PM PDT 24
Peak memory 201400 kb
Host smart-478c3761-036f-4894-9ba7-063add22f5ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832316642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2832316642
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3338373179
Short name T628
Test name
Test status
Simulation time 411234603032 ps
CPU time 239.36 seconds
Started Aug 09 05:35:26 PM PDT 24
Finished Aug 09 05:39:25 PM PDT 24
Peak memory 201372 kb
Host smart-d53081d5-8f7d-413b-bd38-4e09b838a08e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338373179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3338373179
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3613030894
Short name T436
Test name
Test status
Simulation time 609221430896 ps
CPU time 138.59 seconds
Started Aug 09 05:35:29 PM PDT 24
Finished Aug 09 05:37:48 PM PDT 24
Peak memory 201412 kb
Host smart-ff615651-1f51-40bf-8b7b-0eec7a1e352d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613030894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3613030894
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1675384825
Short name T1
Test name
Test status
Simulation time 69085092467 ps
CPU time 220.65 seconds
Started Aug 09 05:35:19 PM PDT 24
Finished Aug 09 05:39:00 PM PDT 24
Peak memory 201852 kb
Host smart-a6bc6191-d162-4177-8b1e-1ee3713bd4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675384825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1675384825
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.4227932403
Short name T697
Test name
Test status
Simulation time 39318693233 ps
CPU time 47.64 seconds
Started Aug 09 05:35:09 PM PDT 24
Finished Aug 09 05:35:57 PM PDT 24
Peak memory 201308 kb
Host smart-6b9c067d-a2a1-4aed-afec-f0187fb340a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227932403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4227932403
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1267256675
Short name T353
Test name
Test status
Simulation time 3408739185 ps
CPU time 1.86 seconds
Started Aug 09 05:35:28 PM PDT 24
Finished Aug 09 05:35:30 PM PDT 24
Peak memory 201376 kb
Host smart-f2ed6d72-320a-49ee-ae63-764d686374f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267256675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1267256675
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4185025697
Short name T420
Test name
Test status
Simulation time 5672893679 ps
CPU time 13.24 seconds
Started Aug 09 05:35:22 PM PDT 24
Finished Aug 09 05:35:36 PM PDT 24
Peak memory 201320 kb
Host smart-42028530-8053-4afc-bcb4-e64908a0cecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185025697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4185025697
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2179735781
Short name T471
Test name
Test status
Simulation time 341268591750 ps
CPU time 653.13 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:46:18 PM PDT 24
Peak memory 201500 kb
Host smart-88c36ce3-3e2c-4e14-99e1-399d1a12cdf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179735781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2179735781
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3331252286
Short name T312
Test name
Test status
Simulation time 15439359539 ps
CPU time 29.24 seconds
Started Aug 09 05:35:29 PM PDT 24
Finished Aug 09 05:35:59 PM PDT 24
Peak memory 201664 kb
Host smart-6ee31719-85dd-476e-8b3b-40bef1cd78fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331252286 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3331252286
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1937751265
Short name T356
Test name
Test status
Simulation time 538743358 ps
CPU time 0.88 seconds
Started Aug 09 05:35:32 PM PDT 24
Finished Aug 09 05:35:33 PM PDT 24
Peak memory 201168 kb
Host smart-eb99751c-0dbe-4da9-9123-c309e13e04d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937751265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1937751265
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3923347659
Short name T579
Test name
Test status
Simulation time 170377392818 ps
CPU time 421.14 seconds
Started Aug 09 05:35:24 PM PDT 24
Finished Aug 09 05:42:25 PM PDT 24
Peak memory 201444 kb
Host smart-1278c489-fe6f-492a-8bd4-402376a6b0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923347659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3923347659
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3651773327
Short name T450
Test name
Test status
Simulation time 484830725455 ps
CPU time 368.78 seconds
Started Aug 09 05:35:20 PM PDT 24
Finished Aug 09 05:41:29 PM PDT 24
Peak memory 201440 kb
Host smart-0b8ba57a-0175-44e7-b181-7b9851e24114
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651773327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3651773327
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2054666051
Short name T718
Test name
Test status
Simulation time 327207136229 ps
CPU time 190.85 seconds
Started Aug 09 05:35:23 PM PDT 24
Finished Aug 09 05:38:34 PM PDT 24
Peak memory 201428 kb
Host smart-4ced7260-6ba6-4bdf-a95e-200e231412db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054666051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2054666051
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1168130945
Short name T388
Test name
Test status
Simulation time 325882784254 ps
CPU time 767.73 seconds
Started Aug 09 05:35:30 PM PDT 24
Finished Aug 09 05:48:18 PM PDT 24
Peak memory 201368 kb
Host smart-64f70c33-4bbf-4fd5-8479-dfdc7e59b650
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168130945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1168130945
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3003717959
Short name T256
Test name
Test status
Simulation time 563033327030 ps
CPU time 637.54 seconds
Started Aug 09 05:35:32 PM PDT 24
Finished Aug 09 05:46:10 PM PDT 24
Peak memory 201316 kb
Host smart-c2793ca9-7849-41ff-b55f-836ede210161
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003717959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3003717959
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2456868770
Short name T761
Test name
Test status
Simulation time 599058276799 ps
CPU time 935.88 seconds
Started Aug 09 05:35:22 PM PDT 24
Finished Aug 09 05:50:58 PM PDT 24
Peak memory 201440 kb
Host smart-e58339dd-50c0-4f80-a7a9-19b3e46023ed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456868770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2456868770
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.693062290
Short name T518
Test name
Test status
Simulation time 100450110961 ps
CPU time 394.53 seconds
Started Aug 09 05:35:30 PM PDT 24
Finished Aug 09 05:42:05 PM PDT 24
Peak memory 201836 kb
Host smart-21d5dbe9-3305-4d08-a766-383a61cd69bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693062290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.693062290
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.744961978
Short name T547
Test name
Test status
Simulation time 32471063697 ps
CPU time 7.21 seconds
Started Aug 09 05:35:16 PM PDT 24
Finished Aug 09 05:35:24 PM PDT 24
Peak memory 201536 kb
Host smart-434b7612-da45-4c29-a5fe-86c650849048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744961978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.744961978
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.484861025
Short name T667
Test name
Test status
Simulation time 4609544845 ps
CPU time 1.94 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:35:38 PM PDT 24
Peak memory 201368 kb
Host smart-72422726-e0f9-4960-9c23-fed673e23c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484861025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.484861025
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3507779170
Short name T490
Test name
Test status
Simulation time 5549139505 ps
CPU time 7.01 seconds
Started Aug 09 05:35:18 PM PDT 24
Finished Aug 09 05:35:25 PM PDT 24
Peak memory 201268 kb
Host smart-7fdc0422-9d09-42ba-9209-cd975c04e7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507779170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3507779170
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1195446016
Short name T621
Test name
Test status
Simulation time 167626732544 ps
CPU time 373.08 seconds
Started Aug 09 05:35:27 PM PDT 24
Finished Aug 09 05:41:41 PM PDT 24
Peak memory 201296 kb
Host smart-0c4215e7-d205-427a-a4e1-c38d1abe083c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195446016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1195446016
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1651866590
Short name T274
Test name
Test status
Simulation time 255860685479 ps
CPU time 255.11 seconds
Started Aug 09 05:35:22 PM PDT 24
Finished Aug 09 05:39:37 PM PDT 24
Peak memory 209944 kb
Host smart-6e520bdb-3164-4126-b63b-24f15afd32b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651866590 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1651866590
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.487721934
Short name T551
Test name
Test status
Simulation time 418035870 ps
CPU time 1.1 seconds
Started Aug 09 05:35:21 PM PDT 24
Finished Aug 09 05:35:22 PM PDT 24
Peak memory 201124 kb
Host smart-788d83a4-618e-4851-b01a-46958d582def
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487721934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.487721934
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.106845022
Short name T587
Test name
Test status
Simulation time 179795360947 ps
CPU time 164.5 seconds
Started Aug 09 05:35:21 PM PDT 24
Finished Aug 09 05:38:05 PM PDT 24
Peak memory 201448 kb
Host smart-7c9056c8-e05f-4951-b730-dea4d84e7175
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106845022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.106845022
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3873846202
Short name T285
Test name
Test status
Simulation time 346640854090 ps
CPU time 57.09 seconds
Started Aug 09 05:35:23 PM PDT 24
Finished Aug 09 05:36:21 PM PDT 24
Peak memory 201428 kb
Host smart-35877dee-a3f8-40c9-877d-3a1546a0c13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873846202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3873846202
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.687838742
Short name T649
Test name
Test status
Simulation time 171497667342 ps
CPU time 384.42 seconds
Started Aug 09 05:35:20 PM PDT 24
Finished Aug 09 05:41:45 PM PDT 24
Peak memory 201388 kb
Host smart-22974308-38a7-4f51-b6d9-0b25d3eaf7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687838742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.687838742
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2853556698
Short name T788
Test name
Test status
Simulation time 335625103066 ps
CPU time 742.02 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:47:47 PM PDT 24
Peak memory 201436 kb
Host smart-c780de1d-666b-414b-bda1-6489faa91353
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853556698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2853556698
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.4261906931
Short name T310
Test name
Test status
Simulation time 328014965204 ps
CPU time 460.45 seconds
Started Aug 09 05:35:26 PM PDT 24
Finished Aug 09 05:43:06 PM PDT 24
Peak memory 201432 kb
Host smart-3abc2977-2706-4db1-b7e6-70745319ae0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261906931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.4261906931
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3342104586
Short name T610
Test name
Test status
Simulation time 162724968279 ps
CPU time 98.77 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:36:53 PM PDT 24
Peak memory 201352 kb
Host smart-364e6bd9-b457-49ea-a821-04d989466447
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342104586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3342104586
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.275974477
Short name T155
Test name
Test status
Simulation time 478963102116 ps
CPU time 350.91 seconds
Started Aug 09 05:35:19 PM PDT 24
Finished Aug 09 05:41:11 PM PDT 24
Peak memory 201520 kb
Host smart-fbefd1e2-2268-417b-a237-1d92053616ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275974477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.275974477
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.4183209862
Short name T361
Test name
Test status
Simulation time 395008395187 ps
CPU time 231.94 seconds
Started Aug 09 05:35:26 PM PDT 24
Finished Aug 09 05:39:18 PM PDT 24
Peak memory 201404 kb
Host smart-efb7ed52-25fb-41b4-ab57-062fc9228e3c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183209862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.4183209862
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.4064801008
Short name T434
Test name
Test status
Simulation time 24515064603 ps
CPU time 52.46 seconds
Started Aug 09 05:35:22 PM PDT 24
Finished Aug 09 05:36:15 PM PDT 24
Peak memory 201316 kb
Host smart-75c29ae9-303b-4124-ad35-19951a2a3708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064801008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.4064801008
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1670940087
Short name T776
Test name
Test status
Simulation time 3520482216 ps
CPU time 2.57 seconds
Started Aug 09 05:35:22 PM PDT 24
Finished Aug 09 05:35:25 PM PDT 24
Peak memory 201308 kb
Host smart-96bf3620-27ea-4785-86ba-6514a5eac2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670940087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1670940087
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1517473040
Short name T4
Test name
Test status
Simulation time 5651097601 ps
CPU time 6.82 seconds
Started Aug 09 05:35:18 PM PDT 24
Finished Aug 09 05:35:25 PM PDT 24
Peak memory 201244 kb
Host smart-937512e6-5920-4c31-beae-c45db3fe8167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517473040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1517473040
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.241191184
Short name T601
Test name
Test status
Simulation time 310789454 ps
CPU time 1.31 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:35:37 PM PDT 24
Peak memory 201220 kb
Host smart-619e7744-14ef-4494-916f-908ee09e3faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241191184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.241191184
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2809013242
Short name T272
Test name
Test status
Simulation time 382441885660 ps
CPU time 256.56 seconds
Started Aug 09 05:35:30 PM PDT 24
Finished Aug 09 05:39:46 PM PDT 24
Peak memory 201384 kb
Host smart-1e0c14b9-8c26-4357-9715-b85b961a6fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809013242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2809013242
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2091818138
Short name T28
Test name
Test status
Simulation time 327689033072 ps
CPU time 115.23 seconds
Started Aug 09 05:35:30 PM PDT 24
Finished Aug 09 05:37:25 PM PDT 24
Peak memory 201360 kb
Host smart-f68d4cc2-e32f-47d7-b6ea-b97e6a92711f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091818138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2091818138
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2129109858
Short name T582
Test name
Test status
Simulation time 166363581445 ps
CPU time 39.2 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:36:04 PM PDT 24
Peak memory 201432 kb
Host smart-58d691ad-ac68-4506-811b-10660cd92a71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129109858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2129109858
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2872383430
Short name T314
Test name
Test status
Simulation time 331386251914 ps
CPU time 381.57 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:41:47 PM PDT 24
Peak memory 201456 kb
Host smart-696f11ba-25a8-4758-ab14-47770d2d014d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872383430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2872383430
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.4037199651
Short name T497
Test name
Test status
Simulation time 499807443800 ps
CPU time 722.69 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:47:28 PM PDT 24
Peak memory 201396 kb
Host smart-6526045a-9ef6-4c96-8358-e1f33c58dacf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037199651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.4037199651
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.215562841
Short name T704
Test name
Test status
Simulation time 365922869937 ps
CPU time 831.16 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:49:16 PM PDT 24
Peak memory 201444 kb
Host smart-9b6be81f-d353-4b87-9655-9a61f3943a55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215562841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.215562841
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.522865462
Short name T401
Test name
Test status
Simulation time 413299050294 ps
CPU time 238.83 seconds
Started Aug 09 05:35:27 PM PDT 24
Finished Aug 09 05:39:26 PM PDT 24
Peak memory 201448 kb
Host smart-e8f76f6b-cb49-4c1b-a437-432c19a616fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522865462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.522865462
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1475972947
Short name T778
Test name
Test status
Simulation time 38877290540 ps
CPU time 14.34 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:35:50 PM PDT 24
Peak memory 201316 kb
Host smart-2167d379-7799-4c29-92f5-831a3a2a871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475972947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1475972947
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.941847703
Short name T446
Test name
Test status
Simulation time 4478415599 ps
CPU time 11.1 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:35:41 PM PDT 24
Peak memory 201272 kb
Host smart-b2f29054-7c3b-47e7-8497-fc7568c80dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941847703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.941847703
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1204393972
Short name T491
Test name
Test status
Simulation time 5701242346 ps
CPU time 1.81 seconds
Started Aug 09 05:35:17 PM PDT 24
Finished Aug 09 05:35:19 PM PDT 24
Peak memory 201208 kb
Host smart-6e79cde3-979e-4376-a0ed-ced1a87c1c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204393972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1204393972
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1478741012
Short name T559
Test name
Test status
Simulation time 230034503872 ps
CPU time 292.48 seconds
Started Aug 09 05:35:24 PM PDT 24
Finished Aug 09 05:40:16 PM PDT 24
Peak memory 210184 kb
Host smart-1d15a88f-417e-4856-8a5f-35474c6ba75b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478741012 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1478741012
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3254873722
Short name T792
Test name
Test status
Simulation time 509711267 ps
CPU time 1.25 seconds
Started Aug 09 05:35:32 PM PDT 24
Finished Aug 09 05:35:34 PM PDT 24
Peak memory 201164 kb
Host smart-c9207568-82d2-484b-82dd-3382515b140b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254873722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3254873722
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1098997504
Short name T652
Test name
Test status
Simulation time 180463865376 ps
CPU time 65.55 seconds
Started Aug 09 05:35:30 PM PDT 24
Finished Aug 09 05:36:35 PM PDT 24
Peak memory 201328 kb
Host smart-986ae234-527b-45ad-a613-fe3e49548243
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098997504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1098997504
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1400370726
Short name T654
Test name
Test status
Simulation time 326991604039 ps
CPU time 179.07 seconds
Started Aug 09 05:35:28 PM PDT 24
Finished Aug 09 05:38:28 PM PDT 24
Peak memory 201368 kb
Host smart-c8ca8f82-bf4f-43cd-9781-afd7bd7ba942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400370726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1400370726
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.528993596
Short name T762
Test name
Test status
Simulation time 166913603446 ps
CPU time 107.3 seconds
Started Aug 09 05:35:16 PM PDT 24
Finished Aug 09 05:37:04 PM PDT 24
Peak memory 201384 kb
Host smart-eb0786d2-5223-4d96-9c62-6e25a10be57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528993596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.528993596
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3013237027
Short name T768
Test name
Test status
Simulation time 493059465989 ps
CPU time 1140.28 seconds
Started Aug 09 05:35:24 PM PDT 24
Finished Aug 09 05:54:24 PM PDT 24
Peak memory 201452 kb
Host smart-5ba946be-a630-4b2d-8496-61ee988275d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013237027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3013237027
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1869909603
Short name T286
Test name
Test status
Simulation time 326441223251 ps
CPU time 192.99 seconds
Started Aug 09 05:35:26 PM PDT 24
Finished Aug 09 05:38:40 PM PDT 24
Peak memory 201376 kb
Host smart-dbeca5b0-cea2-40cd-9dde-6c8c47389cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869909603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1869909603
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.624482179
Short name T658
Test name
Test status
Simulation time 324245256576 ps
CPU time 362.28 seconds
Started Aug 09 05:35:23 PM PDT 24
Finished Aug 09 05:41:26 PM PDT 24
Peak memory 201312 kb
Host smart-f0c88e63-6d45-4197-89e6-689a95bcc8e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=624482179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.624482179
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1646141543
Short name T172
Test name
Test status
Simulation time 360162593297 ps
CPU time 416.34 seconds
Started Aug 09 05:35:22 PM PDT 24
Finished Aug 09 05:42:18 PM PDT 24
Peak memory 201360 kb
Host smart-7e5f2683-582f-4d99-93da-a24e0b95b8ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646141543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1646141543
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1299468791
Short name T422
Test name
Test status
Simulation time 594716511287 ps
CPU time 158.38 seconds
Started Aug 09 05:35:18 PM PDT 24
Finished Aug 09 05:37:57 PM PDT 24
Peak memory 201404 kb
Host smart-c4d23908-a977-41b6-b98c-418c4722db08
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299468791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1299468791
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1623656992
Short name T104
Test name
Test status
Simulation time 131867023940 ps
CPU time 473.36 seconds
Started Aug 09 05:35:30 PM PDT 24
Finished Aug 09 05:43:24 PM PDT 24
Peak memory 201800 kb
Host smart-3f8b8e01-fd0e-4cc3-9094-50f5796cbca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623656992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1623656992
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2585823163
Short name T604
Test name
Test status
Simulation time 42782092318 ps
CPU time 97.03 seconds
Started Aug 09 05:35:27 PM PDT 24
Finished Aug 09 05:37:04 PM PDT 24
Peak memory 201300 kb
Host smart-fc673938-8e1a-4b4b-b75d-b06c031bc7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585823163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2585823163
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2087901623
Short name T477
Test name
Test status
Simulation time 4971482872 ps
CPU time 12.1 seconds
Started Aug 09 05:35:23 PM PDT 24
Finished Aug 09 05:35:35 PM PDT 24
Peak memory 201300 kb
Host smart-cf719209-2081-4aa2-a7f5-c06b8d517083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087901623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2087901623
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1048905414
Short name T777
Test name
Test status
Simulation time 5966246883 ps
CPU time 7.53 seconds
Started Aug 09 05:35:30 PM PDT 24
Finished Aug 09 05:35:38 PM PDT 24
Peak memory 201228 kb
Host smart-c770e928-faf0-4ba4-a901-5a1e85243550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048905414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1048905414
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2441218755
Short name T36
Test name
Test status
Simulation time 169090977579 ps
CPU time 281.71 seconds
Started Aug 09 05:35:29 PM PDT 24
Finished Aug 09 05:40:11 PM PDT 24
Peak memory 201448 kb
Host smart-d1698551-dad2-4d8e-837c-cac7a733177d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441218755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2441218755
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3681938541
Short name T584
Test name
Test status
Simulation time 26832586280 ps
CPU time 52.83 seconds
Started Aug 09 05:35:33 PM PDT 24
Finished Aug 09 05:36:26 PM PDT 24
Peak memory 209820 kb
Host smart-e0dff71f-c5a6-4ab6-87cc-4c100d70aed1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681938541 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3681938541
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.789276229
Short name T479
Test name
Test status
Simulation time 318884917 ps
CPU time 0.81 seconds
Started Aug 09 05:35:29 PM PDT 24
Finished Aug 09 05:35:30 PM PDT 24
Peak memory 201176 kb
Host smart-a33a1a7a-dec6-4743-9e96-5b35654cc770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789276229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.789276229
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3000407216
Short name T731
Test name
Test status
Simulation time 175911638376 ps
CPU time 214.29 seconds
Started Aug 09 05:35:30 PM PDT 24
Finished Aug 09 05:39:04 PM PDT 24
Peak memory 201452 kb
Host smart-ce9902c7-69a8-4936-98a9-7b775a5cdb0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000407216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3000407216
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2431240682
Short name T221
Test name
Test status
Simulation time 329489592669 ps
CPU time 173.44 seconds
Started Aug 09 05:35:33 PM PDT 24
Finished Aug 09 05:38:26 PM PDT 24
Peak memory 201416 kb
Host smart-4ba199d7-9b48-4f93-bc4d-8bf975f28f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431240682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2431240682
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2795862963
Short name T432
Test name
Test status
Simulation time 324698769267 ps
CPU time 386.97 seconds
Started Aug 09 05:35:33 PM PDT 24
Finished Aug 09 05:42:01 PM PDT 24
Peak memory 201436 kb
Host smart-520374c8-4de2-4e02-b68c-f4a152b28c3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795862963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2795862963
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3971248787
Short name T565
Test name
Test status
Simulation time 165167759656 ps
CPU time 376.21 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 05:41:51 PM PDT 24
Peak memory 201528 kb
Host smart-ac743d81-95c0-4917-837e-0ecb9c2ffb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971248787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3971248787
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1834511546
Short name T699
Test name
Test status
Simulation time 161728408779 ps
CPU time 179.77 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 05:38:34 PM PDT 24
Peak memory 201440 kb
Host smart-37edf64a-1e9b-4a28-a594-7b6434b856d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834511546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1834511546
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1902305024
Short name T351
Test name
Test status
Simulation time 205999831329 ps
CPU time 465.49 seconds
Started Aug 09 05:35:37 PM PDT 24
Finished Aug 09 05:43:23 PM PDT 24
Peak memory 201312 kb
Host smart-442f458f-a47c-422c-9bd1-2bbfaa982216
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902305024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1902305024
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.234580751
Short name T59
Test name
Test status
Simulation time 78310812087 ps
CPU time 351.4 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 05:41:26 PM PDT 24
Peak memory 201880 kb
Host smart-290f1e83-e404-4199-9758-8b9042421a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234580751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.234580751
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3091447513
Short name T785
Test name
Test status
Simulation time 31472709962 ps
CPU time 76.05 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 05:36:50 PM PDT 24
Peak memory 201308 kb
Host smart-e070be89-6571-4273-ab55-13bbfb80de36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091447513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3091447513
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2421138972
Short name T606
Test name
Test status
Simulation time 5134841588 ps
CPU time 7.06 seconds
Started Aug 09 05:35:27 PM PDT 24
Finished Aug 09 05:35:34 PM PDT 24
Peak memory 201292 kb
Host smart-bc2a6910-30c1-4d87-b0cd-d59220460788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421138972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2421138972
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1688153955
Short name T391
Test name
Test status
Simulation time 5797456282 ps
CPU time 4.3 seconds
Started Aug 09 05:35:29 PM PDT 24
Finished Aug 09 05:35:33 PM PDT 24
Peak memory 201356 kb
Host smart-cae9c20c-e8e7-4498-a57c-31af19654935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688153955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1688153955
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1847119483
Short name T410
Test name
Test status
Simulation time 16228250188 ps
CPU time 19.03 seconds
Started Aug 09 05:35:32 PM PDT 24
Finished Aug 09 05:35:51 PM PDT 24
Peak memory 201448 kb
Host smart-820958cb-a369-4523-8dbf-ba07c5ad4988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847119483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1847119483
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.210406937
Short name T22
Test name
Test status
Simulation time 36098825766 ps
CPU time 99.33 seconds
Started Aug 09 05:35:27 PM PDT 24
Finished Aug 09 05:37:07 PM PDT 24
Peak memory 218340 kb
Host smart-20b8fbdc-bfa4-4108-98b5-f3d4d033afe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210406937 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.210406937
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3482225053
Short name T444
Test name
Test status
Simulation time 301122433 ps
CPU time 1 seconds
Started Aug 09 05:35:10 PM PDT 24
Finished Aug 09 05:35:11 PM PDT 24
Peak memory 201160 kb
Host smart-c0891ce4-e858-4faf-abda-c96ae030b4ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482225053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3482225053
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3201469469
Short name T216
Test name
Test status
Simulation time 344879819792 ps
CPU time 109.08 seconds
Started Aug 09 05:35:15 PM PDT 24
Finished Aug 09 05:37:04 PM PDT 24
Peak memory 201384 kb
Host smart-1b708837-2e3b-4afa-95b2-a804819e046a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201469469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3201469469
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.232976076
Short name T688
Test name
Test status
Simulation time 167706918649 ps
CPU time 187.22 seconds
Started Aug 09 05:34:45 PM PDT 24
Finished Aug 09 05:37:53 PM PDT 24
Peak memory 201452 kb
Host smart-64f64e72-5c6a-45fd-b2ab-042b8bfd4c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232976076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.232976076
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2524798003
Short name T473
Test name
Test status
Simulation time 161293855168 ps
CPU time 57.39 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:36:02 PM PDT 24
Peak memory 201336 kb
Host smart-d01cf8fe-11f8-483c-b357-757f6b3def86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524798003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2524798003
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.495879105
Short name T472
Test name
Test status
Simulation time 161799258328 ps
CPU time 368.28 seconds
Started Aug 09 05:34:55 PM PDT 24
Finished Aug 09 05:41:04 PM PDT 24
Peak memory 201380 kb
Host smart-a703f35d-ae69-4724-8981-2df6d54692ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=495879105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.495879105
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1481345477
Short name T234
Test name
Test status
Simulation time 158037353362 ps
CPU time 94.7 seconds
Started Aug 09 05:35:03 PM PDT 24
Finished Aug 09 05:36:38 PM PDT 24
Peak memory 201432 kb
Host smart-749932de-36ed-4568-bd5d-90241ce4e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481345477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1481345477
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1148338980
Short name T47
Test name
Test status
Simulation time 493186555159 ps
CPU time 506.88 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:43:39 PM PDT 24
Peak memory 201336 kb
Host smart-ea7945ec-0e2f-46f6-8478-2ebd5a5dd637
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148338980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1148338980
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1485480006
Short name T453
Test name
Test status
Simulation time 532221849950 ps
CPU time 233.53 seconds
Started Aug 09 05:34:55 PM PDT 24
Finished Aug 09 05:38:48 PM PDT 24
Peak memory 201388 kb
Host smart-fa3ff760-a2c3-4d83-ab1e-7446fcc9dc64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485480006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1485480006
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3322226777
Short name T626
Test name
Test status
Simulation time 409296333534 ps
CPU time 247.44 seconds
Started Aug 09 05:34:47 PM PDT 24
Finished Aug 09 05:38:55 PM PDT 24
Peak memory 201464 kb
Host smart-f37fd14b-def6-48bc-a87d-0f227e655d02
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322226777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3322226777
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2289368740
Short name T507
Test name
Test status
Simulation time 97130778182 ps
CPU time 405.26 seconds
Started Aug 09 05:35:22 PM PDT 24
Finished Aug 09 05:42:07 PM PDT 24
Peak memory 201896 kb
Host smart-da1c7031-d585-467f-9ab2-682d7cb99a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289368740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2289368740
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.4265227205
Short name T684
Test name
Test status
Simulation time 46376406891 ps
CPU time 40.84 seconds
Started Aug 09 05:35:03 PM PDT 24
Finished Aug 09 05:35:44 PM PDT 24
Peak memory 201356 kb
Host smart-95670df0-e48c-47cb-b42a-8ebdb893513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265227205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.4265227205
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.804667211
Short name T438
Test name
Test status
Simulation time 5294865990 ps
CPU time 12.31 seconds
Started Aug 09 05:35:00 PM PDT 24
Finished Aug 09 05:35:12 PM PDT 24
Peak memory 201292 kb
Host smart-6d216ae3-28ea-4860-a936-25b0af1a4a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804667211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.804667211
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2604679973
Short name T80
Test name
Test status
Simulation time 4592069458 ps
CPU time 5.64 seconds
Started Aug 09 05:35:13 PM PDT 24
Finished Aug 09 05:35:19 PM PDT 24
Peak memory 217076 kb
Host smart-6a5d5032-9dcc-46d0-8ed0-e1e720fe90c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604679973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2604679973
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.313487758
Short name T424
Test name
Test status
Simulation time 5514590847 ps
CPU time 12.9 seconds
Started Aug 09 05:34:44 PM PDT 24
Finished Aug 09 05:34:57 PM PDT 24
Peak memory 201352 kb
Host smart-40bba03b-299a-4f9e-9f65-0477d3d89950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313487758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.313487758
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1712866487
Short name T732
Test name
Test status
Simulation time 83132688491 ps
CPU time 37.01 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:35:41 PM PDT 24
Peak memory 201236 kb
Host smart-095062cf-c6d2-4a7e-8a20-460003bb106a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712866487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1712866487
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2102383788
Short name T38
Test name
Test status
Simulation time 24402411703 ps
CPU time 60.02 seconds
Started Aug 09 05:35:05 PM PDT 24
Finished Aug 09 05:36:15 PM PDT 24
Peak memory 201516 kb
Host smart-cab203c7-b654-4370-afa6-abccbc2bf689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102383788 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2102383788
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3635834555
Short name T683
Test name
Test status
Simulation time 535577819 ps
CPU time 0.79 seconds
Started Aug 09 05:35:35 PM PDT 24
Finished Aug 09 05:35:36 PM PDT 24
Peak memory 201108 kb
Host smart-dc1b5685-def6-4d9a-b4d7-38aa42ec01a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635834555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3635834555
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1345535538
Short name T164
Test name
Test status
Simulation time 353344688718 ps
CPU time 76.9 seconds
Started Aug 09 05:35:29 PM PDT 24
Finished Aug 09 05:36:46 PM PDT 24
Peak memory 201412 kb
Host smart-eee44ba0-d1d5-49f8-af16-0418068f052e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345535538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1345535538
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.706281769
Short name T142
Test name
Test status
Simulation time 362466207393 ps
CPU time 261.1 seconds
Started Aug 09 05:35:26 PM PDT 24
Finished Aug 09 05:39:47 PM PDT 24
Peak memory 201436 kb
Host smart-6d0693b5-555e-4dde-a213-e0e5d960e4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706281769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.706281769
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1462397921
Short name T157
Test name
Test status
Simulation time 491715388072 ps
CPU time 518.15 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 05:44:13 PM PDT 24
Peak memory 201404 kb
Host smart-cb670f89-4311-4619-bca5-c5e695a9472a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462397921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1462397921
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2459433955
Short name T638
Test name
Test status
Simulation time 160757782508 ps
CPU time 362.19 seconds
Started Aug 09 05:35:50 PM PDT 24
Finished Aug 09 05:41:52 PM PDT 24
Peak memory 201448 kb
Host smart-7ff438a9-be6a-4a4d-8f30-0b656e5f429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459433955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2459433955
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2060308198
Short name T337
Test name
Test status
Simulation time 163926156856 ps
CPU time 159.42 seconds
Started Aug 09 05:35:33 PM PDT 24
Finished Aug 09 05:38:13 PM PDT 24
Peak memory 201396 kb
Host smart-7dae98f0-28e0-40aa-8dc8-3d6d0d033756
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060308198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2060308198
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1727221527
Short name T690
Test name
Test status
Simulation time 206283572597 ps
CPU time 53.59 seconds
Started Aug 09 05:35:32 PM PDT 24
Finished Aug 09 05:36:25 PM PDT 24
Peak memory 201316 kb
Host smart-86263f16-1860-4733-8e02-f0cea41a8128
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727221527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1727221527
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.4168919603
Short name T623
Test name
Test status
Simulation time 390299326101 ps
CPU time 401.82 seconds
Started Aug 09 05:35:38 PM PDT 24
Finished Aug 09 05:42:20 PM PDT 24
Peak memory 201336 kb
Host smart-17470a56-8323-4479-848f-fa483f141506
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168919603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.4168919603
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3104163589
Short name T328
Test name
Test status
Simulation time 81097096783 ps
CPU time 297.25 seconds
Started Aug 09 05:35:37 PM PDT 24
Finished Aug 09 05:40:34 PM PDT 24
Peak memory 201828 kb
Host smart-886f6628-f311-4aa8-b165-44c4308d384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104163589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3104163589
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3105972305
Short name T370
Test name
Test status
Simulation time 22494847934 ps
CPU time 26.18 seconds
Started Aug 09 05:35:29 PM PDT 24
Finished Aug 09 05:35:55 PM PDT 24
Peak memory 201352 kb
Host smart-590d84d6-69f6-4788-be0b-5c1e6ccda87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105972305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3105972305
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3735658882
Short name T377
Test name
Test status
Simulation time 5680088948 ps
CPU time 4 seconds
Started Aug 09 05:35:35 PM PDT 24
Finished Aug 09 05:35:39 PM PDT 24
Peak memory 201260 kb
Host smart-14bacd9f-1800-4ef5-9dbf-1e0fcba65f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735658882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3735658882
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.4150176899
Short name T553
Test name
Test status
Simulation time 5801099038 ps
CPU time 4.39 seconds
Started Aug 09 05:35:29 PM PDT 24
Finished Aug 09 05:35:34 PM PDT 24
Peak memory 201320 kb
Host smart-666e7a9e-481f-424f-9685-6d90e194a036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150176899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.4150176899
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.745614397
Short name T171
Test name
Test status
Simulation time 552865090254 ps
CPU time 1765.23 seconds
Started Aug 09 05:35:35 PM PDT 24
Finished Aug 09 06:05:01 PM PDT 24
Peak memory 209904 kb
Host smart-bbfb4684-eb30-4492-9c7b-e71b68fb9895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745614397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
745614397
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2895856326
Short name T317
Test name
Test status
Simulation time 1080785073755 ps
CPU time 547.49 seconds
Started Aug 09 05:35:35 PM PDT 24
Finished Aug 09 05:44:43 PM PDT 24
Peak memory 210172 kb
Host smart-aa37349b-476e-43cd-a571-cb77a9c13d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895856326 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2895856326
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.720247287
Short name T354
Test name
Test status
Simulation time 338296397 ps
CPU time 0.99 seconds
Started Aug 09 05:35:35 PM PDT 24
Finished Aug 09 05:35:36 PM PDT 24
Peak memory 201192 kb
Host smart-f311b02b-68ae-4c92-a9c0-b5199c658531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720247287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.720247287
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1026978838
Short name T288
Test name
Test status
Simulation time 323663251484 ps
CPU time 294.22 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:40:30 PM PDT 24
Peak memory 201480 kb
Host smart-ea3d9d85-67c4-4ff3-9b7a-ed33fc56c9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026978838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1026978838
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1978287068
Short name T693
Test name
Test status
Simulation time 332226029510 ps
CPU time 766.05 seconds
Started Aug 09 05:35:37 PM PDT 24
Finished Aug 09 05:48:23 PM PDT 24
Peak memory 201480 kb
Host smart-26ca046a-67a0-432a-9bd1-ce53421c5109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978287068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1978287068
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.419810606
Short name T515
Test name
Test status
Simulation time 169195726304 ps
CPU time 35.78 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 05:36:10 PM PDT 24
Peak memory 201464 kb
Host smart-549f3317-8ae5-4b16-ae8f-50946439ffeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=419810606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.419810606
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1745613813
Short name T581
Test name
Test status
Simulation time 487513347784 ps
CPU time 1071.39 seconds
Started Aug 09 05:35:32 PM PDT 24
Finished Aug 09 05:53:24 PM PDT 24
Peak memory 201396 kb
Host smart-efc16fe7-c54b-4d59-b6e7-6c8768cb836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745613813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1745613813
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.94097982
Short name T415
Test name
Test status
Simulation time 165812336116 ps
CPU time 104.17 seconds
Started Aug 09 05:35:35 PM PDT 24
Finished Aug 09 05:37:19 PM PDT 24
Peak memory 201448 kb
Host smart-e6e54969-6700-485b-85e3-36977db68d10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=94097982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed
.94097982
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.618389328
Short name T173
Test name
Test status
Simulation time 537593561556 ps
CPU time 420.55 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 05:42:35 PM PDT 24
Peak memory 201320 kb
Host smart-1d1ab05d-3cdb-42b5-a133-2f514fb7e268
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618389328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.618389328
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4099095814
Short name T640
Test name
Test status
Simulation time 199557319478 ps
CPU time 428.24 seconds
Started Aug 09 05:35:38 PM PDT 24
Finished Aug 09 05:42:47 PM PDT 24
Peak memory 201400 kb
Host smart-407f0206-ad9b-441c-a636-0b67dacb221b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099095814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.4099095814
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.848874063
Short name T57
Test name
Test status
Simulation time 90193426655 ps
CPU time 500.49 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:43:56 PM PDT 24
Peak memory 201836 kb
Host smart-9e5ec150-a4e9-4f57-a736-04301f4fdece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848874063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.848874063
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2435358442
Short name T414
Test name
Test status
Simulation time 32832126992 ps
CPU time 18.93 seconds
Started Aug 09 05:35:31 PM PDT 24
Finished Aug 09 05:35:50 PM PDT 24
Peak memory 201216 kb
Host smart-28057d1e-5072-4568-847c-d20b977d33e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435358442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2435358442
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2530189654
Short name T405
Test name
Test status
Simulation time 2994042853 ps
CPU time 2.26 seconds
Started Aug 09 05:35:33 PM PDT 24
Finished Aug 09 05:35:35 PM PDT 24
Peak memory 201344 kb
Host smart-33589e62-6af7-40e7-8222-0f2f4ea024ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530189654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2530189654
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3759259590
Short name T773
Test name
Test status
Simulation time 5964331746 ps
CPU time 4.53 seconds
Started Aug 09 05:35:27 PM PDT 24
Finished Aug 09 05:35:32 PM PDT 24
Peak memory 201292 kb
Host smart-c35ebdec-cc1e-4799-b1ef-4d66057fa8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759259590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3759259590
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1249775028
Short name T55
Test name
Test status
Simulation time 507848097028 ps
CPU time 1817.25 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 06:05:51 PM PDT 24
Peak memory 200408 kb
Host smart-7e1c1a61-d03f-4ae5-b86b-143272c7e4fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249775028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1249775028
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.524434763
Short name T435
Test name
Test status
Simulation time 452697555 ps
CPU time 1.58 seconds
Started Aug 09 05:35:39 PM PDT 24
Finished Aug 09 05:35:41 PM PDT 24
Peak memory 201256 kb
Host smart-1631c568-92cb-46b4-b614-d829ef5f7958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524434763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.524434763
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3833414442
Short name T316
Test name
Test status
Simulation time 325315844267 ps
CPU time 761.47 seconds
Started Aug 09 05:35:41 PM PDT 24
Finished Aug 09 05:48:23 PM PDT 24
Peak memory 201428 kb
Host smart-b74ca2e3-9bc0-43db-a289-7d6c46ab3b1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833414442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3833414442
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.529866781
Short name T239
Test name
Test status
Simulation time 328007914110 ps
CPU time 767.02 seconds
Started Aug 09 05:35:38 PM PDT 24
Finished Aug 09 05:48:25 PM PDT 24
Peak memory 201416 kb
Host smart-3451cf01-a4fb-4623-aa64-e6c5f39e26de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529866781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.529866781
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2725909475
Short name T752
Test name
Test status
Simulation time 499791505738 ps
CPU time 1126.89 seconds
Started Aug 09 05:35:41 PM PDT 24
Finished Aug 09 05:54:28 PM PDT 24
Peak memory 201448 kb
Host smart-0644e126-533e-4b69-8496-1017360a55e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725909475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2725909475
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2609662299
Short name T97
Test name
Test status
Simulation time 326156825125 ps
CPU time 81.25 seconds
Started Aug 09 05:35:40 PM PDT 24
Finished Aug 09 05:37:01 PM PDT 24
Peak memory 201420 kb
Host smart-7024fef6-a0ff-4172-b9b4-165750666551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609662299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2609662299
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.684350683
Short name T428
Test name
Test status
Simulation time 490369154969 ps
CPU time 567.63 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 05:45:02 PM PDT 24
Peak memory 201388 kb
Host smart-8c8305f9-cd32-42c1-b123-9bba0f5325f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=684350683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.684350683
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.91177936
Short name T661
Test name
Test status
Simulation time 203894830740 ps
CPU time 95.99 seconds
Started Aug 09 05:35:42 PM PDT 24
Finished Aug 09 05:37:18 PM PDT 24
Peak memory 200052 kb
Host smart-c41b3a62-40d8-457c-b605-9592d1b01d87
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91177936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.a
dc_ctrl_filters_wakeup_fixed.91177936
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.4079583066
Short name T180
Test name
Test status
Simulation time 90190108791 ps
CPU time 346.34 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 05:41:21 PM PDT 24
Peak memory 201788 kb
Host smart-8730b150-0359-4d64-ab00-1f3f0b39c687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079583066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.4079583066
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1346528052
Short name T371
Test name
Test status
Simulation time 42172793783 ps
CPU time 24.68 seconds
Started Aug 09 05:35:48 PM PDT 24
Finished Aug 09 05:36:13 PM PDT 24
Peak memory 201336 kb
Host smart-c6485fbe-18f3-4b09-a15c-c4a62024a17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346528052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1346528052
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1923550117
Short name T738
Test name
Test status
Simulation time 5281994716 ps
CPU time 4.08 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:35:40 PM PDT 24
Peak memory 201240 kb
Host smart-e0964352-937d-4be2-b6a9-0a40b270de7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923550117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1923550117
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1434038493
Short name T702
Test name
Test status
Simulation time 5728804718 ps
CPU time 4.32 seconds
Started Aug 09 05:35:37 PM PDT 24
Finished Aug 09 05:35:41 PM PDT 24
Peak memory 201332 kb
Host smart-59b81c7b-cc51-41f5-8238-48e2b942c9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434038493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1434038493
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3516271978
Short name T506
Test name
Test status
Simulation time 12186147782 ps
CPU time 27.5 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:36:03 PM PDT 24
Peak memory 201392 kb
Host smart-473a3fa5-37f4-4d14-bea7-143f6fb018a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516271978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3516271978
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1121159232
Short name T517
Test name
Test status
Simulation time 75229311652 ps
CPU time 83.35 seconds
Started Aug 09 05:35:35 PM PDT 24
Finished Aug 09 05:36:59 PM PDT 24
Peak memory 209868 kb
Host smart-f581a72c-e6a9-428c-8d3d-4621aab7a4c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121159232 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1121159232
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2130020882
Short name T619
Test name
Test status
Simulation time 314749325 ps
CPU time 1.23 seconds
Started Aug 09 05:35:40 PM PDT 24
Finished Aug 09 05:35:41 PM PDT 24
Peak memory 201124 kb
Host smart-1fdc6eb5-6e4d-46dd-960d-c34b798cbaf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130020882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2130020882
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1996945443
Short name T89
Test name
Test status
Simulation time 368550025466 ps
CPU time 596.22 seconds
Started Aug 09 05:35:46 PM PDT 24
Finished Aug 09 05:45:43 PM PDT 24
Peak memory 201412 kb
Host smart-9fa91ed8-374b-49eb-b781-6780043d5e88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996945443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1996945443
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2120050049
Short name T315
Test name
Test status
Simulation time 166499644367 ps
CPU time 47.98 seconds
Started Aug 09 05:35:42 PM PDT 24
Finished Aug 09 05:36:30 PM PDT 24
Peak memory 201428 kb
Host smart-a6b7fab6-58f5-42fc-8849-e182bc4453e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120050049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2120050049
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2196922103
Short name T452
Test name
Test status
Simulation time 164396691345 ps
CPU time 104.2 seconds
Started Aug 09 05:35:45 PM PDT 24
Finished Aug 09 05:37:30 PM PDT 24
Peak memory 201412 kb
Host smart-962f0296-87df-4f9c-8ed8-f854d9fdae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196922103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2196922103
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1269148903
Short name T751
Test name
Test status
Simulation time 326992218236 ps
CPU time 703.53 seconds
Started Aug 09 05:35:40 PM PDT 24
Finished Aug 09 05:47:23 PM PDT 24
Peak memory 201428 kb
Host smart-af82e2ba-5a00-4397-9e53-8c53aec44d40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269148903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1269148903
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3117030311
Short name T293
Test name
Test status
Simulation time 488031223697 ps
CPU time 1049.31 seconds
Started Aug 09 05:35:35 PM PDT 24
Finished Aug 09 05:53:05 PM PDT 24
Peak memory 201456 kb
Host smart-1b552d56-d398-4a42-beb6-c5c02bc1eb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117030311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3117030311
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3862689953
Short name T90
Test name
Test status
Simulation time 162620856000 ps
CPU time 86.14 seconds
Started Aug 09 05:35:38 PM PDT 24
Finished Aug 09 05:37:05 PM PDT 24
Peak memory 201412 kb
Host smart-ebaa48fb-c5fa-4331-a8bb-b7946a4e9213
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862689953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3862689953
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1351734784
Short name T196
Test name
Test status
Simulation time 185668424962 ps
CPU time 403.49 seconds
Started Aug 09 05:35:36 PM PDT 24
Finished Aug 09 05:42:20 PM PDT 24
Peak memory 201364 kb
Host smart-781c2c24-d901-4a94-84f5-8a655a1988b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351734784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1351734784
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4126805347
Short name T189
Test name
Test status
Simulation time 109261598740 ps
CPU time 484.44 seconds
Started Aug 09 05:35:40 PM PDT 24
Finished Aug 09 05:43:45 PM PDT 24
Peak memory 201828 kb
Host smart-6c595be8-f7b5-4354-883c-c6a938903210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126805347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4126805347
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.622774257
Short name T397
Test name
Test status
Simulation time 37220668323 ps
CPU time 22.63 seconds
Started Aug 09 05:35:43 PM PDT 24
Finished Aug 09 05:36:06 PM PDT 24
Peak memory 201360 kb
Host smart-39d04a79-2bed-412c-a3f3-ac579cdc5d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622774257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.622774257
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.215814809
Short name T673
Test name
Test status
Simulation time 4125398177 ps
CPU time 10.39 seconds
Started Aug 09 05:35:39 PM PDT 24
Finished Aug 09 05:35:50 PM PDT 24
Peak memory 201304 kb
Host smart-d029dc33-06a0-4f15-b045-b81bb3877b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215814809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.215814809
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1817611942
Short name T735
Test name
Test status
Simulation time 5809450887 ps
CPU time 4.28 seconds
Started Aug 09 05:35:46 PM PDT 24
Finished Aug 09 05:35:51 PM PDT 24
Peak memory 201208 kb
Host smart-115c4471-0bc5-4240-97c2-4f9c4908706d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817611942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1817611942
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.782981233
Short name T407
Test name
Test status
Simulation time 381352639 ps
CPU time 1.48 seconds
Started Aug 09 05:35:42 PM PDT 24
Finished Aug 09 05:35:44 PM PDT 24
Peak memory 201120 kb
Host smart-0d689e5f-60f2-4a7a-9ecf-c0dc49beffd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782981233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.782981233
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.40374792
Short name T98
Test name
Test status
Simulation time 177219747250 ps
CPU time 392.54 seconds
Started Aug 09 05:35:37 PM PDT 24
Finished Aug 09 05:42:09 PM PDT 24
Peak memory 201488 kb
Host smart-0c15952f-ebd7-474a-978b-c5ce08c3e822
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40374792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gatin
g.40374792
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.540437715
Short name T485
Test name
Test status
Simulation time 225107838232 ps
CPU time 129.24 seconds
Started Aug 09 05:35:39 PM PDT 24
Finished Aug 09 05:37:48 PM PDT 24
Peak memory 201420 kb
Host smart-702e25e1-df73-42a0-90e0-78e0b1291469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540437715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.540437715
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2869666208
Short name T298
Test name
Test status
Simulation time 331279404391 ps
CPU time 209.09 seconds
Started Aug 09 05:35:44 PM PDT 24
Finished Aug 09 05:39:13 PM PDT 24
Peak memory 201356 kb
Host smart-7328b3c1-062b-49ba-927a-a010d9ef3d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869666208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2869666208
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3688169585
Short name T730
Test name
Test status
Simulation time 330530664424 ps
CPU time 796.94 seconds
Started Aug 09 05:35:41 PM PDT 24
Finished Aug 09 05:48:58 PM PDT 24
Peak memory 201476 kb
Host smart-9a576d73-1b7c-477a-a80a-93a9f41a9099
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688169585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3688169585
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.218721739
Short name T790
Test name
Test status
Simulation time 161735711240 ps
CPU time 86.6 seconds
Started Aug 09 05:35:41 PM PDT 24
Finished Aug 09 05:37:08 PM PDT 24
Peak memory 201432 kb
Host smart-33552b6d-1f3c-4cf1-bed6-9b15c56465cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218721739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.218721739
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1166945311
Short name T357
Test name
Test status
Simulation time 327926147108 ps
CPU time 717.3 seconds
Started Aug 09 05:35:35 PM PDT 24
Finished Aug 09 05:47:32 PM PDT 24
Peak memory 201404 kb
Host smart-0b43d42c-4593-4bcd-ab52-80a1128a82d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166945311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1166945311
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3115950986
Short name T289
Test name
Test status
Simulation time 521287915057 ps
CPU time 310.26 seconds
Started Aug 09 05:35:37 PM PDT 24
Finished Aug 09 05:40:48 PM PDT 24
Peak memory 201444 kb
Host smart-22da4be1-4f6e-4df9-ba8a-ff2e5e4617f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115950986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3115950986
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1074180104
Short name T742
Test name
Test status
Simulation time 608687475589 ps
CPU time 289.59 seconds
Started Aug 09 05:35:46 PM PDT 24
Finished Aug 09 05:40:36 PM PDT 24
Peak memory 201468 kb
Host smart-c2a6dca4-61ad-43e4-8623-6a069e9c52db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074180104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1074180104
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3683893006
Short name T775
Test name
Test status
Simulation time 81526992028 ps
CPU time 431.94 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 05:42:46 PM PDT 24
Peak memory 201876 kb
Host smart-7e4382d9-dc1f-450c-a5e5-2ee1207ecbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683893006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3683893006
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2835629858
Short name T440
Test name
Test status
Simulation time 30083421889 ps
CPU time 61.59 seconds
Started Aug 09 05:35:44 PM PDT 24
Finished Aug 09 05:36:46 PM PDT 24
Peak memory 201344 kb
Host smart-0d0d07e3-0e40-4ee5-95d4-c2ddc7ce3e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835629858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2835629858
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.706228474
Short name T680
Test name
Test status
Simulation time 5022430086 ps
CPU time 4.04 seconds
Started Aug 09 05:35:33 PM PDT 24
Finished Aug 09 05:35:38 PM PDT 24
Peak memory 201252 kb
Host smart-f4f41cf0-abf1-4d99-a00d-b5bb7b86ce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706228474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.706228474
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2411694998
Short name T437
Test name
Test status
Simulation time 5820348414 ps
CPU time 7.82 seconds
Started Aug 09 05:35:50 PM PDT 24
Finished Aug 09 05:35:58 PM PDT 24
Peak memory 201284 kb
Host smart-a107417a-0c72-4d2c-a4cd-88eac504768d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411694998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2411694998
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.4278298005
Short name T267
Test name
Test status
Simulation time 165428474857 ps
CPU time 150.43 seconds
Started Aug 09 05:35:46 PM PDT 24
Finished Aug 09 05:38:16 PM PDT 24
Peak memory 218280 kb
Host smart-8dd790a9-b800-47d3-bde4-493cd4304ce4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278298005 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.4278298005
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.233856515
Short name T662
Test name
Test status
Simulation time 424589884 ps
CPU time 0.91 seconds
Started Aug 09 05:35:53 PM PDT 24
Finished Aug 09 05:35:54 PM PDT 24
Peak memory 201200 kb
Host smart-d7a34e39-0770-489c-9741-f825baa0a59d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233856515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.233856515
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2188620534
Short name T140
Test name
Test status
Simulation time 176116670923 ps
CPU time 89.32 seconds
Started Aug 09 05:35:38 PM PDT 24
Finished Aug 09 05:37:07 PM PDT 24
Peak memory 201360 kb
Host smart-3bc92dde-2054-4272-bf15-d38aa4bb01d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188620534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2188620534
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.159754271
Short name T611
Test name
Test status
Simulation time 487799930814 ps
CPU time 1012.37 seconds
Started Aug 09 05:35:50 PM PDT 24
Finished Aug 09 05:52:43 PM PDT 24
Peak memory 201436 kb
Host smart-de4adae6-f9d5-4f0b-b7fa-4b77efb55ce4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=159754271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.159754271
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3680035922
Short name T202
Test name
Test status
Simulation time 163943857491 ps
CPU time 57.94 seconds
Started Aug 09 05:35:45 PM PDT 24
Finished Aug 09 05:36:43 PM PDT 24
Peak memory 201420 kb
Host smart-e6522f5d-96e3-46ff-85d2-46b6ca07e044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680035922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3680035922
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.495106068
Short name T715
Test name
Test status
Simulation time 487392255811 ps
CPU time 1136.85 seconds
Started Aug 09 05:35:43 PM PDT 24
Finished Aug 09 05:54:40 PM PDT 24
Peak memory 201396 kb
Host smart-31a4ac0a-3d0e-4d56-b2f4-099752ef706d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=495106068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.495106068
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.917148826
Short name T225
Test name
Test status
Simulation time 175640189528 ps
CPU time 410.23 seconds
Started Aug 09 05:35:34 PM PDT 24
Finished Aug 09 05:42:25 PM PDT 24
Peak memory 201400 kb
Host smart-7e24c7e8-c84c-462a-8a25-5521e00e201c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917148826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.917148826
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3405961936
Short name T627
Test name
Test status
Simulation time 600969196940 ps
CPU time 1364.51 seconds
Started Aug 09 05:35:41 PM PDT 24
Finished Aug 09 05:58:26 PM PDT 24
Peak memory 201424 kb
Host smart-fe83841c-deba-4d56-a676-62c3beff4d42
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405961936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3405961936
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2728158391
Short name T411
Test name
Test status
Simulation time 79043061457 ps
CPU time 385.92 seconds
Started Aug 09 05:35:41 PM PDT 24
Finished Aug 09 05:42:07 PM PDT 24
Peak memory 201836 kb
Host smart-d7dc8a8a-c642-46ca-99ea-8dd876ff9c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728158391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2728158391
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.874893991
Short name T30
Test name
Test status
Simulation time 31332838307 ps
CPU time 70.29 seconds
Started Aug 09 05:35:46 PM PDT 24
Finished Aug 09 05:36:57 PM PDT 24
Peak memory 201292 kb
Host smart-7cffc4bd-4894-4212-8a45-0228aea2d97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874893991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.874893991
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3446399554
Short name T8
Test name
Test status
Simulation time 5656436973 ps
CPU time 1.77 seconds
Started Aug 09 05:35:41 PM PDT 24
Finished Aug 09 05:35:43 PM PDT 24
Peak memory 201312 kb
Host smart-ae9f903f-3dc8-47ea-b94e-9deb0cf4bec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446399554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3446399554
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3857101957
Short name T362
Test name
Test status
Simulation time 5735293052 ps
CPU time 4.54 seconds
Started Aug 09 05:35:43 PM PDT 24
Finished Aug 09 05:35:48 PM PDT 24
Peak memory 201564 kb
Host smart-1cc1f1b3-e482-4be2-aad4-0010ee6294ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857101957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3857101957
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.713880313
Short name T503
Test name
Test status
Simulation time 208621029089 ps
CPU time 104.52 seconds
Started Aug 09 05:35:51 PM PDT 24
Finished Aug 09 05:37:36 PM PDT 24
Peak memory 201376 kb
Host smart-b860ab69-5ef5-44d4-8d26-553f94b0d6ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713880313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
713880313
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.587031324
Short name T668
Test name
Test status
Simulation time 92009325463 ps
CPU time 84.42 seconds
Started Aug 09 05:35:50 PM PDT 24
Finished Aug 09 05:37:14 PM PDT 24
Peak memory 210124 kb
Host smart-1951116c-8251-4bde-8a42-4bfcc25fd9c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587031324 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.587031324
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2366565906
Short name T340
Test name
Test status
Simulation time 345638430 ps
CPU time 1.38 seconds
Started Aug 09 05:35:48 PM PDT 24
Finished Aug 09 05:35:50 PM PDT 24
Peak memory 201132 kb
Host smart-568d9766-52ea-4c62-b731-624c1eeeff9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366565906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2366565906
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.4001752426
Short name T516
Test name
Test status
Simulation time 483357650203 ps
CPU time 288.09 seconds
Started Aug 09 05:35:50 PM PDT 24
Finished Aug 09 05:40:38 PM PDT 24
Peak memory 201404 kb
Host smart-aa4c30e4-6345-407b-8e28-f744844bde45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001752426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.4001752426
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1067481942
Short name T297
Test name
Test status
Simulation time 490001075446 ps
CPU time 1095.35 seconds
Started Aug 09 05:35:43 PM PDT 24
Finished Aug 09 05:53:59 PM PDT 24
Peak memory 201664 kb
Host smart-28fb3069-7329-43cf-b4e4-67c34a895767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067481942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1067481942
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1743897153
Short name T625
Test name
Test status
Simulation time 169223288753 ps
CPU time 96.53 seconds
Started Aug 09 05:35:40 PM PDT 24
Finished Aug 09 05:37:17 PM PDT 24
Peak memory 201372 kb
Host smart-5c7cddd4-d1ae-4aa5-a1e2-fb46119e2818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743897153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1743897153
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.580899713
Short name T341
Test name
Test status
Simulation time 328567053229 ps
CPU time 748.56 seconds
Started Aug 09 05:35:44 PM PDT 24
Finished Aug 09 05:48:13 PM PDT 24
Peak memory 201672 kb
Host smart-bece8c63-370d-4be1-8eec-f2127176c325
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=580899713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.580899713
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1214920940
Short name T291
Test name
Test status
Simulation time 493617088584 ps
CPU time 1098.42 seconds
Started Aug 09 05:35:50 PM PDT 24
Finished Aug 09 05:54:08 PM PDT 24
Peak memory 201348 kb
Host smart-1538075e-c384-4eee-892a-13be8438ad26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214920940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1214920940
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2216706207
Short name T365
Test name
Test status
Simulation time 495043225175 ps
CPU time 560.58 seconds
Started Aug 09 05:35:43 PM PDT 24
Finished Aug 09 05:45:04 PM PDT 24
Peak memory 201312 kb
Host smart-be1e6aa3-7139-4fb0-b156-7e4d79316b3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216706207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2216706207
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1410722508
Short name T258
Test name
Test status
Simulation time 468543991201 ps
CPU time 1007.11 seconds
Started Aug 09 05:35:44 PM PDT 24
Finished Aug 09 05:52:31 PM PDT 24
Peak memory 201316 kb
Host smart-44aeeed0-4986-42f8-b85b-2e93ce16841a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410722508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1410722508
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.402164977
Short name T567
Test name
Test status
Simulation time 589253645664 ps
CPU time 1326.25 seconds
Started Aug 09 05:35:51 PM PDT 24
Finished Aug 09 05:57:57 PM PDT 24
Peak memory 201624 kb
Host smart-78377554-e2e8-404f-897b-c9b574a317ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402164977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.402164977
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1308551464
Short name T745
Test name
Test status
Simulation time 132711355528 ps
CPU time 477.05 seconds
Started Aug 09 05:35:46 PM PDT 24
Finished Aug 09 05:43:44 PM PDT 24
Peak memory 201688 kb
Host smart-39fc93f8-7e3c-4968-8ad7-f56565994797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308551464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1308551464
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1452051939
Short name T528
Test name
Test status
Simulation time 30335368865 ps
CPU time 44.91 seconds
Started Aug 09 05:35:47 PM PDT 24
Finished Aug 09 05:36:32 PM PDT 24
Peak memory 201332 kb
Host smart-f9669827-3b2e-4a25-808c-99b08ac36abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452051939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1452051939
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3143229221
Short name T648
Test name
Test status
Simulation time 3911166858 ps
CPU time 2.87 seconds
Started Aug 09 05:35:46 PM PDT 24
Finished Aug 09 05:35:49 PM PDT 24
Peak memory 201232 kb
Host smart-63142938-25c3-4c08-9124-22a57c695c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143229221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3143229221
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3606583365
Short name T409
Test name
Test status
Simulation time 5705794293 ps
CPU time 7.43 seconds
Started Aug 09 05:35:44 PM PDT 24
Finished Aug 09 05:35:52 PM PDT 24
Peak memory 201564 kb
Host smart-bb14aeb5-1ddf-4d02-8a4b-7656987bfaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606583365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3606583365
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3192811264
Short name T229
Test name
Test status
Simulation time 549712206173 ps
CPU time 324.29 seconds
Started Aug 09 05:35:52 PM PDT 24
Finished Aug 09 05:41:17 PM PDT 24
Peak memory 201460 kb
Host smart-ca1d4203-e6c5-4d5b-95b3-fad14e670bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192811264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3192811264
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.376511355
Short name T744
Test name
Test status
Simulation time 85761463461 ps
CPU time 197.56 seconds
Started Aug 09 05:35:50 PM PDT 24
Finished Aug 09 05:39:07 PM PDT 24
Peak memory 210124 kb
Host smart-6624df6f-1b75-4a9e-abd4-824a957ba6ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376511355 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.376511355
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1936017599
Short name T332
Test name
Test status
Simulation time 511941836 ps
CPU time 0.79 seconds
Started Aug 09 05:35:40 PM PDT 24
Finished Aug 09 05:35:41 PM PDT 24
Peak memory 201168 kb
Host smart-f843feb3-b545-47a4-9727-0a9de141e767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936017599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1936017599
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3570060783
Short name T760
Test name
Test status
Simulation time 551637468182 ps
CPU time 1235.95 seconds
Started Aug 09 05:35:47 PM PDT 24
Finished Aug 09 05:56:23 PM PDT 24
Peak memory 201420 kb
Host smart-3fbb5670-539c-445b-9b4f-382bd803769b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570060783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3570060783
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1104883246
Short name T678
Test name
Test status
Simulation time 488894692986 ps
CPU time 114.74 seconds
Started Aug 09 05:35:54 PM PDT 24
Finished Aug 09 05:37:48 PM PDT 24
Peak memory 201668 kb
Host smart-e7f43f9c-8c64-4e22-bbf9-bfa7f5be385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104883246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1104883246
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3560330584
Short name T620
Test name
Test status
Simulation time 320626582311 ps
CPU time 200.92 seconds
Started Aug 09 05:35:44 PM PDT 24
Finished Aug 09 05:39:05 PM PDT 24
Peak memory 201380 kb
Host smart-5e994b02-a8a0-4646-a9f5-4199cc02d273
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560330584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3560330584
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.784387181
Short name T276
Test name
Test status
Simulation time 490591243162 ps
CPU time 1127.71 seconds
Started Aug 09 05:35:42 PM PDT 24
Finished Aug 09 05:54:29 PM PDT 24
Peak memory 201392 kb
Host smart-9e52d847-8f3b-428a-8677-507ad5fe4a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784387181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.784387181
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1258987098
Short name T670
Test name
Test status
Simulation time 496411900710 ps
CPU time 908.95 seconds
Started Aug 09 05:35:45 PM PDT 24
Finished Aug 09 05:50:54 PM PDT 24
Peak memory 201324 kb
Host smart-a7f3a219-41fb-4604-b046-b7f76aa01ad5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258987098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1258987098
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4096343942
Short name T364
Test name
Test status
Simulation time 598443738182 ps
CPU time 1334.89 seconds
Started Aug 09 05:35:42 PM PDT 24
Finished Aug 09 05:57:57 PM PDT 24
Peak memory 201312 kb
Host smart-de9b35be-fd3b-49c1-897d-3d71c44be0da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096343942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4096343942
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2120004070
Short name T447
Test name
Test status
Simulation time 129796896278 ps
CPU time 479.72 seconds
Started Aug 09 05:35:43 PM PDT 24
Finished Aug 09 05:43:43 PM PDT 24
Peak memory 201704 kb
Host smart-a15b346e-5741-4e69-a757-a3ba2a632a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120004070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2120004070
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1666673514
Short name T780
Test name
Test status
Simulation time 41893251436 ps
CPU time 23.4 seconds
Started Aug 09 05:35:44 PM PDT 24
Finished Aug 09 05:36:08 PM PDT 24
Peak memory 201320 kb
Host smart-ba44110b-84f2-428c-83b5-2bfec950a454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666673514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1666673514
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3061711542
Short name T93
Test name
Test status
Simulation time 4253529523 ps
CPU time 1.6 seconds
Started Aug 09 05:35:43 PM PDT 24
Finished Aug 09 05:35:45 PM PDT 24
Peak memory 201300 kb
Host smart-5b9369bd-f2e5-422a-8804-e37da695d193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061711542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3061711542
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3840750212
Short name T483
Test name
Test status
Simulation time 6154500381 ps
CPU time 16.48 seconds
Started Aug 09 05:35:41 PM PDT 24
Finished Aug 09 05:35:58 PM PDT 24
Peak memory 201352 kb
Host smart-9152aab0-c972-463c-a2a7-412c393d6dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840750212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3840750212
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3276336188
Short name T534
Test name
Test status
Simulation time 723163699163 ps
CPU time 1578.35 seconds
Started Aug 09 05:35:44 PM PDT 24
Finished Aug 09 06:02:03 PM PDT 24
Peak memory 201424 kb
Host smart-556e0675-acf3-4877-88e0-44c51293de97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276336188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3276336188
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1301737033
Short name T602
Test name
Test status
Simulation time 82739918855 ps
CPU time 42.05 seconds
Started Aug 09 05:35:43 PM PDT 24
Finished Aug 09 05:36:25 PM PDT 24
Peak memory 210036 kb
Host smart-439b1649-2dea-4c25-a6ac-5f8b19f3d5ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301737033 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1301737033
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3207747395
Short name T520
Test name
Test status
Simulation time 454490751 ps
CPU time 0.87 seconds
Started Aug 09 05:35:44 PM PDT 24
Finished Aug 09 05:35:45 PM PDT 24
Peak memory 201148 kb
Host smart-a43e00fe-0f69-4f00-9668-893c5d7a7925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207747395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3207747395
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1627386319
Short name T741
Test name
Test status
Simulation time 323641275116 ps
CPU time 717.85 seconds
Started Aug 09 05:35:49 PM PDT 24
Finished Aug 09 05:47:47 PM PDT 24
Peak memory 201404 kb
Host smart-6b0fe4ec-2ba7-44cd-bd65-269e6f3372d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627386319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1627386319
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3611993776
Short name T219
Test name
Test status
Simulation time 161168863856 ps
CPU time 178.72 seconds
Started Aug 09 05:35:43 PM PDT 24
Finished Aug 09 05:38:42 PM PDT 24
Peak memory 201428 kb
Host smart-806677ca-7889-4dba-9f1f-38f79a388f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611993776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3611993776
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3181083666
Short name T783
Test name
Test status
Simulation time 161728051533 ps
CPU time 395.83 seconds
Started Aug 09 05:35:43 PM PDT 24
Finished Aug 09 05:42:19 PM PDT 24
Peak memory 201440 kb
Host smart-102896a9-4f79-44dd-acbf-3b151f560019
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181083666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3181083666
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1673711399
Short name T458
Test name
Test status
Simulation time 324886783591 ps
CPU time 770.78 seconds
Started Aug 09 05:35:44 PM PDT 24
Finished Aug 09 05:48:35 PM PDT 24
Peak memory 201424 kb
Host smart-a7918e54-1ae8-47b1-a7c9-91fb5a84bcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673711399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1673711399
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.813900308
Short name T480
Test name
Test status
Simulation time 165737052062 ps
CPU time 315.03 seconds
Started Aug 09 05:35:44 PM PDT 24
Finished Aug 09 05:40:59 PM PDT 24
Peak memory 201304 kb
Host smart-68ac8d1e-a7c7-4851-bffc-427644e0bed2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=813900308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.813900308
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.35622183
Short name T484
Test name
Test status
Simulation time 185601912601 ps
CPU time 90.19 seconds
Started Aug 09 05:35:50 PM PDT 24
Finished Aug 09 05:37:20 PM PDT 24
Peak memory 201308 kb
Host smart-a545eeb9-4800-4e03-b09d-c64b5a20a987
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35622183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_w
akeup.35622183
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3297321467
Short name T460
Test name
Test status
Simulation time 198151494167 ps
CPU time 221.18 seconds
Started Aug 09 05:35:44 PM PDT 24
Finished Aug 09 05:39:25 PM PDT 24
Peak memory 201384 kb
Host smart-30a2eea8-2eb4-46b1-9e64-91495b4fd610
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297321467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3297321467
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2327247125
Short name T325
Test name
Test status
Simulation time 122265839064 ps
CPU time 446.48 seconds
Started Aug 09 05:35:49 PM PDT 24
Finished Aug 09 05:43:15 PM PDT 24
Peak memory 201760 kb
Host smart-dcc8d43a-23ab-4922-ab6a-b8da663ba9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327247125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2327247125
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3270187916
Short name T462
Test name
Test status
Simulation time 44853312089 ps
CPU time 110.73 seconds
Started Aug 09 05:35:48 PM PDT 24
Finished Aug 09 05:37:39 PM PDT 24
Peak memory 201360 kb
Host smart-288d9d07-9fea-477a-ae71-01a179967f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270187916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3270187916
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.495017421
Short name T454
Test name
Test status
Simulation time 5436926105 ps
CPU time 14.28 seconds
Started Aug 09 05:35:46 PM PDT 24
Finished Aug 09 05:36:01 PM PDT 24
Peak memory 201208 kb
Host smart-43048efc-3100-4370-8122-99ed989657e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495017421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.495017421
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1992499888
Short name T555
Test name
Test status
Simulation time 5956492954 ps
CPU time 2.59 seconds
Started Aug 09 05:35:42 PM PDT 24
Finished Aug 09 05:35:45 PM PDT 24
Peak memory 201360 kb
Host smart-ad67bd34-2fce-48d2-ae5c-82ed7a7abe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992499888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1992499888
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3238221305
Short name T538
Test name
Test status
Simulation time 48735518779 ps
CPU time 110.3 seconds
Started Aug 09 05:35:46 PM PDT 24
Finished Aug 09 05:37:36 PM PDT 24
Peak memory 201320 kb
Host smart-baa1dcc6-494a-4b56-acdf-8daad684c5d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238221305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3238221305
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1882694880
Short name T39
Test name
Test status
Simulation time 162415298247 ps
CPU time 174.9 seconds
Started Aug 09 05:35:48 PM PDT 24
Finished Aug 09 05:38:43 PM PDT 24
Peak memory 210208 kb
Host smart-6cd5e2ef-f1b1-4725-9818-52d50767e53f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882694880 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1882694880
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1103875524
Short name T400
Test name
Test status
Simulation time 452893052 ps
CPU time 1.32 seconds
Started Aug 09 05:35:51 PM PDT 24
Finished Aug 09 05:35:53 PM PDT 24
Peak memory 201224 kb
Host smart-3bcb4594-ac6d-417f-984d-b3713358fe0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103875524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1103875524
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3406236221
Short name T263
Test name
Test status
Simulation time 521082182876 ps
CPU time 577.88 seconds
Started Aug 09 05:35:55 PM PDT 24
Finished Aug 09 05:45:33 PM PDT 24
Peak memory 201520 kb
Host smart-b4bd4af6-c77d-447c-a034-2986bf734d3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406236221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3406236221
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.717872333
Short name T767
Test name
Test status
Simulation time 179935853235 ps
CPU time 31.72 seconds
Started Aug 09 05:35:49 PM PDT 24
Finished Aug 09 05:36:21 PM PDT 24
Peak memory 201448 kb
Host smart-f37d3d1b-1bd4-4710-a2be-d531e73605a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717872333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.717872333
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4177013796
Short name T716
Test name
Test status
Simulation time 504266784019 ps
CPU time 325.18 seconds
Started Aug 09 05:35:49 PM PDT 24
Finished Aug 09 05:41:15 PM PDT 24
Peak memory 201360 kb
Host smart-ad818061-5c13-4853-b378-cea84abe8f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177013796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4177013796
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1511028712
Short name T589
Test name
Test status
Simulation time 162971115505 ps
CPU time 92.22 seconds
Started Aug 09 05:35:48 PM PDT 24
Finished Aug 09 05:37:20 PM PDT 24
Peak memory 201524 kb
Host smart-60cea4f8-2f0c-415a-b22e-0637b7ecc724
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511028712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1511028712
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2004814262
Short name T134
Test name
Test status
Simulation time 494650729064 ps
CPU time 628.02 seconds
Started Aug 09 05:35:51 PM PDT 24
Finished Aug 09 05:46:19 PM PDT 24
Peak memory 201420 kb
Host smart-98f74287-cf1b-4427-a07d-f6baa84c235e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004814262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2004814262
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.939395665
Short name T513
Test name
Test status
Simulation time 322873111454 ps
CPU time 376.82 seconds
Started Aug 09 05:35:47 PM PDT 24
Finished Aug 09 05:42:03 PM PDT 24
Peak memory 201372 kb
Host smart-77619565-4b67-49bd-8769-f09e9d58af2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=939395665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.939395665
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3883447570
Short name T199
Test name
Test status
Simulation time 536348096986 ps
CPU time 1263.38 seconds
Started Aug 09 05:35:50 PM PDT 24
Finished Aug 09 05:56:53 PM PDT 24
Peak memory 201296 kb
Host smart-95143d0e-9670-4111-8f31-f70967828116
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883447570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3883447570
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1693679669
Short name T470
Test name
Test status
Simulation time 413379602653 ps
CPU time 191.67 seconds
Started Aug 09 05:35:47 PM PDT 24
Finished Aug 09 05:38:59 PM PDT 24
Peak memory 201368 kb
Host smart-73c42775-f905-4571-b401-18d1bb80a83e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693679669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1693679669
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1144882059
Short name T179
Test name
Test status
Simulation time 101998881903 ps
CPU time 374.9 seconds
Started Aug 09 05:35:56 PM PDT 24
Finished Aug 09 05:42:11 PM PDT 24
Peak memory 201788 kb
Host smart-d1de8169-4b85-4ccc-a95f-f72ca7b0d096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144882059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1144882059
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.4052132401
Short name T634
Test name
Test status
Simulation time 21279086659 ps
CPU time 24.11 seconds
Started Aug 09 05:35:51 PM PDT 24
Finished Aug 09 05:36:16 PM PDT 24
Peak memory 201316 kb
Host smart-ed2e6ef4-dfbe-4212-b264-cccdb49b9753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052132401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4052132401
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1562159482
Short name T419
Test name
Test status
Simulation time 3190474910 ps
CPU time 8.22 seconds
Started Aug 09 05:35:55 PM PDT 24
Finished Aug 09 05:36:03 PM PDT 24
Peak memory 201224 kb
Host smart-cf21da14-7c96-4886-836f-74d6eef790f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562159482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1562159482
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.488377360
Short name T544
Test name
Test status
Simulation time 5929262753 ps
CPU time 8.28 seconds
Started Aug 09 05:35:46 PM PDT 24
Finished Aug 09 05:35:55 PM PDT 24
Peak memory 201356 kb
Host smart-27e015c1-ae13-4439-9816-e98feeaaacc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488377360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.488377360
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3357209533
Short name T455
Test name
Test status
Simulation time 427623870 ps
CPU time 0.99 seconds
Started Aug 09 05:35:10 PM PDT 24
Finished Aug 09 05:35:16 PM PDT 24
Peak memory 201260 kb
Host smart-ca344ad9-cff6-48c0-97ff-cc5b9a13a9b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357209533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3357209533
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.670576628
Short name T605
Test name
Test status
Simulation time 505553784910 ps
CPU time 87 seconds
Started Aug 09 05:35:10 PM PDT 24
Finished Aug 09 05:36:37 PM PDT 24
Peak memory 201416 kb
Host smart-a6ef5507-d046-4db5-b9bd-e664ad81a99e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670576628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.670576628
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3676622074
Short name T487
Test name
Test status
Simulation time 192312555022 ps
CPU time 230.3 seconds
Started Aug 09 05:35:05 PM PDT 24
Finished Aug 09 05:38:55 PM PDT 24
Peak memory 201460 kb
Host smart-81a48988-7f71-45c0-b393-ab0a403e5cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676622074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3676622074
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1275463023
Short name T154
Test name
Test status
Simulation time 321447059014 ps
CPU time 349.75 seconds
Started Aug 09 05:35:07 PM PDT 24
Finished Aug 09 05:41:01 PM PDT 24
Peak memory 201504 kb
Host smart-3e772251-1020-4cab-8663-7294e1c0de59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275463023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1275463023
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.4243089850
Short name T523
Test name
Test status
Simulation time 494763200387 ps
CPU time 306.12 seconds
Started Aug 09 05:34:54 PM PDT 24
Finished Aug 09 05:40:00 PM PDT 24
Peak memory 201476 kb
Host smart-9254b2b2-4153-4a7a-ade9-3a628bcc5bcf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243089850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.4243089850
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1157665700
Short name T374
Test name
Test status
Simulation time 169677927316 ps
CPU time 28.96 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:35:43 PM PDT 24
Peak memory 201416 kb
Host smart-2a3ef041-9454-49f9-b8a2-eb53d2c8033a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157665700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1157665700
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.4181297597
Short name T577
Test name
Test status
Simulation time 169745509286 ps
CPU time 401.85 seconds
Started Aug 09 05:34:55 PM PDT 24
Finished Aug 09 05:41:37 PM PDT 24
Peak memory 201348 kb
Host smart-4599079b-57be-432d-8ff4-3919eedd3f96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181297597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.4181297597
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3724790508
Short name T566
Test name
Test status
Simulation time 203377250217 ps
CPU time 481.9 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:43:17 PM PDT 24
Peak memory 201716 kb
Host smart-8d2212cd-0139-44a2-adea-d713a5e37571
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724790508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3724790508
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2957034699
Short name T360
Test name
Test status
Simulation time 591984966391 ps
CPU time 1319.82 seconds
Started Aug 09 05:35:16 PM PDT 24
Finished Aug 09 05:57:16 PM PDT 24
Peak memory 201312 kb
Host smart-cc397b08-60d7-4e2d-af3e-d6b93f39e579
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957034699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2957034699
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1679863419
Short name T504
Test name
Test status
Simulation time 74678739120 ps
CPU time 419.84 seconds
Started Aug 09 05:35:24 PM PDT 24
Finished Aug 09 05:42:24 PM PDT 24
Peak memory 201872 kb
Host smart-652527da-0cd5-48b4-abf7-0f38b0496bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679863419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1679863419
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3980072107
Short name T686
Test name
Test status
Simulation time 29199045975 ps
CPU time 64.94 seconds
Started Aug 09 05:35:11 PM PDT 24
Finished Aug 09 05:36:16 PM PDT 24
Peak memory 201264 kb
Host smart-f63766bf-3f94-4838-b4a5-f98d339ca02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980072107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3980072107
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2411776852
Short name T46
Test name
Test status
Simulation time 5399265503 ps
CPU time 7.39 seconds
Started Aug 09 05:34:58 PM PDT 24
Finished Aug 09 05:35:05 PM PDT 24
Peak memory 201212 kb
Host smart-946974e0-24f6-4eaf-9157-d92da09cdd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411776852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2411776852
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1738432744
Short name T70
Test name
Test status
Simulation time 7799292895 ps
CPU time 19.23 seconds
Started Aug 09 05:35:02 PM PDT 24
Finished Aug 09 05:35:21 PM PDT 24
Peak memory 218124 kb
Host smart-4f5e928d-52ef-4554-b952-2b8a17a31f3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738432744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1738432744
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3328874488
Short name T339
Test name
Test status
Simulation time 5828318272 ps
CPU time 14.69 seconds
Started Aug 09 05:35:18 PM PDT 24
Finished Aug 09 05:35:33 PM PDT 24
Peak memory 201356 kb
Host smart-0d44f981-462c-457b-8345-ffc84c16d0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328874488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3328874488
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.484084650
Short name T237
Test name
Test status
Simulation time 624449158638 ps
CPU time 747.94 seconds
Started Aug 09 05:34:59 PM PDT 24
Finished Aug 09 05:47:28 PM PDT 24
Peak memory 201776 kb
Host smart-fc2dabce-af03-4115-abcd-c90426aa9bed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484084650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.484084650
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3751352265
Short name T21
Test name
Test status
Simulation time 87827833092 ps
CPU time 245.71 seconds
Started Aug 09 05:35:00 PM PDT 24
Finished Aug 09 05:39:06 PM PDT 24
Peak memory 210092 kb
Host smart-90b7a121-4bb4-4ba7-a3e9-f42e05a855e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751352265 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3751352265
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.950994124
Short name T593
Test name
Test status
Simulation time 400825193 ps
CPU time 1.07 seconds
Started Aug 09 05:35:57 PM PDT 24
Finished Aug 09 05:35:59 PM PDT 24
Peak memory 201236 kb
Host smart-ad16a069-6311-49ca-8de6-5058f652acf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950994124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.950994124
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1025376352
Short name T249
Test name
Test status
Simulation time 197308622690 ps
CPU time 247.77 seconds
Started Aug 09 05:35:57 PM PDT 24
Finished Aug 09 05:40:05 PM PDT 24
Peak memory 201400 kb
Host smart-ccf50e25-2aa9-451d-97a8-adcc2984bf8a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025376352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1025376352
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.752998484
Short name T728
Test name
Test status
Simulation time 158799655202 ps
CPU time 359.41 seconds
Started Aug 09 05:35:50 PM PDT 24
Finished Aug 09 05:41:50 PM PDT 24
Peak memory 201444 kb
Host smart-1c073648-425b-4b5a-a3de-f8fe0afea8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752998484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.752998484
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3953640844
Short name T406
Test name
Test status
Simulation time 161229245094 ps
CPU time 95.6 seconds
Started Aug 09 05:35:54 PM PDT 24
Finished Aug 09 05:37:29 PM PDT 24
Peak memory 201504 kb
Host smart-f846b568-5364-4579-8085-e8a7f1f7306a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953640844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3953640844
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.698016698
Short name T228
Test name
Test status
Simulation time 503552639038 ps
CPU time 1151.12 seconds
Started Aug 09 05:35:51 PM PDT 24
Finished Aug 09 05:55:03 PM PDT 24
Peak memory 201336 kb
Host smart-9ba59f0b-5735-4260-bfd1-0c1b31db84fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698016698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.698016698
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1893300851
Short name T40
Test name
Test status
Simulation time 165011352706 ps
CPU time 174.87 seconds
Started Aug 09 05:35:59 PM PDT 24
Finished Aug 09 05:38:54 PM PDT 24
Peak memory 201424 kb
Host smart-8706baf8-4a34-4d1d-ab11-4899f7262d23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893300851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1893300851
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1778903893
Short name T724
Test name
Test status
Simulation time 585225841021 ps
CPU time 323.65 seconds
Started Aug 09 05:35:59 PM PDT 24
Finished Aug 09 05:41:22 PM PDT 24
Peak memory 201392 kb
Host smart-f3e37f4a-30ff-4c09-b169-6860d27ee274
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778903893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1778903893
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2308799479
Short name T753
Test name
Test status
Simulation time 92321042682 ps
CPU time 354.34 seconds
Started Aug 09 05:35:59 PM PDT 24
Finished Aug 09 05:41:54 PM PDT 24
Peak memory 201780 kb
Host smart-6812acef-ce22-433d-a683-50e4a9aef0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308799479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2308799479
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1093097831
Short name T733
Test name
Test status
Simulation time 36008960580 ps
CPU time 79.94 seconds
Started Aug 09 05:35:57 PM PDT 24
Finished Aug 09 05:37:17 PM PDT 24
Peak memory 201324 kb
Host smart-ed3c0252-2529-456e-96cf-d9c262ff5218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093097831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1093097831
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.443362803
Short name T558
Test name
Test status
Simulation time 5094828733 ps
CPU time 3.7 seconds
Started Aug 09 05:35:58 PM PDT 24
Finished Aug 09 05:36:02 PM PDT 24
Peak memory 201356 kb
Host smart-bb0e01ab-4395-4b6a-a225-2f0b2c96bbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443362803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.443362803
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.122035511
Short name T529
Test name
Test status
Simulation time 5901590327 ps
CPU time 4.81 seconds
Started Aug 09 05:35:56 PM PDT 24
Finished Aug 09 05:36:01 PM PDT 24
Peak memory 201328 kb
Host smart-727a0a67-b764-4d58-9fe3-591fda32ee83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122035511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.122035511
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3072458277
Short name T181
Test name
Test status
Simulation time 110741209663 ps
CPU time 110.55 seconds
Started Aug 09 05:35:57 PM PDT 24
Finished Aug 09 05:37:48 PM PDT 24
Peak memory 210196 kb
Host smart-04562f27-79c5-43f2-8825-f4a706e542e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072458277 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3072458277
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.756091237
Short name T633
Test name
Test status
Simulation time 332164365 ps
CPU time 1.39 seconds
Started Aug 09 05:35:58 PM PDT 24
Finished Aug 09 05:35:59 PM PDT 24
Peak memory 201408 kb
Host smart-385415c0-6a7e-4837-8f33-66ebe186a8d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756091237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.756091237
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2447864390
Short name T739
Test name
Test status
Simulation time 333029038386 ps
CPU time 147.68 seconds
Started Aug 09 05:35:57 PM PDT 24
Finished Aug 09 05:38:25 PM PDT 24
Peak memory 201356 kb
Host smart-a9d229bf-6148-4af0-8f9c-cc831c7ff8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447864390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2447864390
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.251441675
Short name T210
Test name
Test status
Simulation time 158837779481 ps
CPU time 87.76 seconds
Started Aug 09 05:35:57 PM PDT 24
Finished Aug 09 05:37:25 PM PDT 24
Peak memory 201484 kb
Host smart-8cfdcd4c-c35d-43e8-af3e-637c5ffb336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251441675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.251441675
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1667825402
Short name T561
Test name
Test status
Simulation time 319721530745 ps
CPU time 754.7 seconds
Started Aug 09 05:35:58 PM PDT 24
Finished Aug 09 05:48:33 PM PDT 24
Peak memory 201400 kb
Host smart-b0617278-6b90-4064-b7c1-706813b954eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667825402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1667825402
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2538864494
Short name T570
Test name
Test status
Simulation time 331983272966 ps
CPU time 121.13 seconds
Started Aug 09 05:35:58 PM PDT 24
Finished Aug 09 05:37:59 PM PDT 24
Peak memory 201444 kb
Host smart-a5fc2172-d8e0-4e3a-bf6c-6dce6aa813ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538864494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2538864494
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3740456555
Short name T653
Test name
Test status
Simulation time 329611540428 ps
CPU time 755.83 seconds
Started Aug 09 05:35:56 PM PDT 24
Finished Aug 09 05:48:32 PM PDT 24
Peak memory 201392 kb
Host smart-58ea283e-1ed9-4662-94e7-3444894c39f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740456555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3740456555
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.440230466
Short name T156
Test name
Test status
Simulation time 368027548586 ps
CPU time 121.21 seconds
Started Aug 09 05:36:02 PM PDT 24
Finished Aug 09 05:38:03 PM PDT 24
Peak memory 201392 kb
Host smart-a0bcf4d0-7c4b-4274-ac10-cf69add97b22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440230466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.440230466
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2251971116
Short name T495
Test name
Test status
Simulation time 400897676564 ps
CPU time 894.32 seconds
Started Aug 09 05:35:58 PM PDT 24
Finished Aug 09 05:50:52 PM PDT 24
Peak memory 201464 kb
Host smart-64d88b37-8461-4a34-a301-343428afa0d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251971116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2251971116
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1290883812
Short name T599
Test name
Test status
Simulation time 37844888546 ps
CPU time 22.02 seconds
Started Aug 09 05:35:57 PM PDT 24
Finished Aug 09 05:36:19 PM PDT 24
Peak memory 201292 kb
Host smart-c6e24487-fabf-4f30-8e53-f25791f89439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290883812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1290883812
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.666672819
Short name T459
Test name
Test status
Simulation time 4029870190 ps
CPU time 3.41 seconds
Started Aug 09 05:35:56 PM PDT 24
Finished Aug 09 05:36:00 PM PDT 24
Peak memory 201236 kb
Host smart-28d80a47-bc19-4cdd-bf31-2be07310b11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666672819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.666672819
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.211444736
Short name T449
Test name
Test status
Simulation time 5903538935 ps
CPU time 14.4 seconds
Started Aug 09 05:36:01 PM PDT 24
Finished Aug 09 05:36:16 PM PDT 24
Peak memory 201276 kb
Host smart-59ab01a1-3cb3-439c-8968-fabfa911808f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211444736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.211444736
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2572393507
Short name T34
Test name
Test status
Simulation time 167628388022 ps
CPU time 12.86 seconds
Started Aug 09 05:36:00 PM PDT 24
Finished Aug 09 05:36:13 PM PDT 24
Peak memory 201296 kb
Host smart-3e5835e9-8fb0-422f-b0b7-7404164f0bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572393507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2572393507
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2702669335
Short name T24
Test name
Test status
Simulation time 20256491557 ps
CPU time 24.12 seconds
Started Aug 09 05:35:58 PM PDT 24
Finished Aug 09 05:36:22 PM PDT 24
Peak memory 209732 kb
Host smart-dbeb3b05-44ec-4404-8d7d-1ab0e8db6fd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702669335 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2702669335
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1631325607
Short name T76
Test name
Test status
Simulation time 488030261 ps
CPU time 1.48 seconds
Started Aug 09 05:36:05 PM PDT 24
Finished Aug 09 05:36:07 PM PDT 24
Peak memory 201204 kb
Host smart-067ac586-db14-420c-8bde-f4be17428468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631325607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1631325607
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2026023306
Short name T663
Test name
Test status
Simulation time 164035984081 ps
CPU time 99.23 seconds
Started Aug 09 05:36:01 PM PDT 24
Finished Aug 09 05:37:40 PM PDT 24
Peak memory 201480 kb
Host smart-59d4015a-136f-4c48-a3b9-bacd9d05fe53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026023306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2026023306
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2210328422
Short name T573
Test name
Test status
Simulation time 346113115550 ps
CPU time 413.12 seconds
Started Aug 09 05:36:05 PM PDT 24
Finished Aug 09 05:42:58 PM PDT 24
Peak memory 201424 kb
Host smart-540f7f0a-9038-4e0c-843f-e865b5a3acce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210328422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2210328422
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.455479392
Short name T578
Test name
Test status
Simulation time 167808389794 ps
CPU time 123.23 seconds
Started Aug 09 05:36:03 PM PDT 24
Finished Aug 09 05:38:06 PM PDT 24
Peak memory 201284 kb
Host smart-93824178-4d78-49cf-9cf7-fa2787909ae4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=455479392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.455479392
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3714772734
Short name T135
Test name
Test status
Simulation time 496021233387 ps
CPU time 1179.7 seconds
Started Aug 09 05:35:55 PM PDT 24
Finished Aug 09 05:55:35 PM PDT 24
Peak memory 201460 kb
Host smart-8588cb42-899a-49d0-877f-2a62081c6548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714772734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3714772734
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.4194825921
Short name T590
Test name
Test status
Simulation time 491669057397 ps
CPU time 1060.65 seconds
Started Aug 09 05:36:01 PM PDT 24
Finished Aug 09 05:53:41 PM PDT 24
Peak memory 201272 kb
Host smart-078b1409-8d3e-4968-86a8-c92ba9c5e30f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194825921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.4194825921
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1488227834
Short name T379
Test name
Test status
Simulation time 396020880407 ps
CPU time 236.7 seconds
Started Aug 09 05:36:02 PM PDT 24
Finished Aug 09 05:39:59 PM PDT 24
Peak memory 201400 kb
Host smart-962f6dcc-7ca0-4ccf-8e39-f6ab9d135bd8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488227834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1488227834
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2890914754
Short name T330
Test name
Test status
Simulation time 68169386371 ps
CPU time 258.62 seconds
Started Aug 09 05:36:03 PM PDT 24
Finished Aug 09 05:40:22 PM PDT 24
Peak memory 201740 kb
Host smart-52ed9424-4d91-4ba7-a5a6-1d775e4ed51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890914754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2890914754
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3921732310
Short name T549
Test name
Test status
Simulation time 30833232613 ps
CPU time 17.03 seconds
Started Aug 09 05:36:03 PM PDT 24
Finished Aug 09 05:36:20 PM PDT 24
Peak memory 201360 kb
Host smart-6f37b39a-a5d9-4a00-9da7-b7366f553bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921732310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3921732310
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3898687960
Short name T692
Test name
Test status
Simulation time 3599223481 ps
CPU time 2.48 seconds
Started Aug 09 05:36:03 PM PDT 24
Finished Aug 09 05:36:06 PM PDT 24
Peak memory 201268 kb
Host smart-5181417d-8fb5-47f5-b96d-60e73ee4c893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898687960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3898687960
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2086676730
Short name T651
Test name
Test status
Simulation time 6224588642 ps
CPU time 16.22 seconds
Started Aug 09 05:35:57 PM PDT 24
Finished Aug 09 05:36:13 PM PDT 24
Peak memory 201272 kb
Host smart-9d83b056-1098-4c69-aa47-3a35bd8ecb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086676730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2086676730
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.254129495
Short name T23
Test name
Test status
Simulation time 50174167388 ps
CPU time 209.03 seconds
Started Aug 09 05:36:04 PM PDT 24
Finished Aug 09 05:39:33 PM PDT 24
Peak memory 210148 kb
Host smart-f972c326-708a-4e78-8e0c-de204a28d281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254129495 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.254129495
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.4263576220
Short name T533
Test name
Test status
Simulation time 412789303 ps
CPU time 0.85 seconds
Started Aug 09 05:36:06 PM PDT 24
Finished Aug 09 05:36:07 PM PDT 24
Peak memory 201256 kb
Host smart-8af120a6-759f-4142-81a4-76144e0f1327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263576220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.4263576220
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3854400579
Short name T44
Test name
Test status
Simulation time 208288915133 ps
CPU time 114.37 seconds
Started Aug 09 05:36:08 PM PDT 24
Finished Aug 09 05:38:02 PM PDT 24
Peak memory 201408 kb
Host smart-263f4b35-b6da-474d-b508-dc699af492b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854400579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3854400579
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.4085249522
Short name T489
Test name
Test status
Simulation time 334347460154 ps
CPU time 745.09 seconds
Started Aug 09 05:36:06 PM PDT 24
Finished Aug 09 05:48:31 PM PDT 24
Peak memory 201432 kb
Host smart-cf547261-f82e-4e74-a6b5-be5bc00125f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085249522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.4085249522
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3703614352
Short name T138
Test name
Test status
Simulation time 161489377087 ps
CPU time 85.49 seconds
Started Aug 09 05:36:09 PM PDT 24
Finished Aug 09 05:37:35 PM PDT 24
Peak memory 201336 kb
Host smart-6607916a-3fcd-4f23-812b-ecb3215b40c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703614352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3703614352
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.291736332
Short name T613
Test name
Test status
Simulation time 164791458366 ps
CPU time 60.08 seconds
Started Aug 09 05:36:07 PM PDT 24
Finished Aug 09 05:37:07 PM PDT 24
Peak memory 201460 kb
Host smart-46329280-d03b-4519-b839-07c0a98d4c84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=291736332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.291736332
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2190655810
Short name T540
Test name
Test status
Simulation time 163304959643 ps
CPU time 93.97 seconds
Started Aug 09 05:36:01 PM PDT 24
Finished Aug 09 05:37:35 PM PDT 24
Peak memory 201460 kb
Host smart-42488ddc-09a7-4a32-86d7-6213c9e4fd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190655810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2190655810
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1352067936
Short name T345
Test name
Test status
Simulation time 488113290372 ps
CPU time 304.03 seconds
Started Aug 09 05:36:09 PM PDT 24
Finished Aug 09 05:41:13 PM PDT 24
Peak memory 201420 kb
Host smart-857cc98a-1a22-4b4f-ba88-58b67f041fe3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352067936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1352067936
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2962207252
Short name T637
Test name
Test status
Simulation time 366613967985 ps
CPU time 922.79 seconds
Started Aug 09 05:36:10 PM PDT 24
Finished Aug 09 05:51:33 PM PDT 24
Peak memory 201392 kb
Host smart-c77603b2-d06a-4fce-816a-1e8627ef6faa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962207252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2962207252
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2365582293
Short name T665
Test name
Test status
Simulation time 397181366281 ps
CPU time 236.56 seconds
Started Aug 09 05:36:08 PM PDT 24
Finished Aug 09 05:40:04 PM PDT 24
Peak memory 201320 kb
Host smart-bcee0ef7-c300-4fe3-ae1f-b5f566307b72
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365582293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2365582293
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.448604810
Short name T178
Test name
Test status
Simulation time 70951661976 ps
CPU time 279.66 seconds
Started Aug 09 05:36:08 PM PDT 24
Finished Aug 09 05:40:48 PM PDT 24
Peak memory 201824 kb
Host smart-1e41906f-8d73-48cb-912f-89b4c847ddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448604810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.448604810
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.766890863
Short name T554
Test name
Test status
Simulation time 43235300254 ps
CPU time 99.54 seconds
Started Aug 09 05:36:09 PM PDT 24
Finished Aug 09 05:37:49 PM PDT 24
Peak memory 201356 kb
Host smart-7d2a79cd-d85b-447a-a752-65d89acdeaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766890863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.766890863
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.773699997
Short name T378
Test name
Test status
Simulation time 3667829396 ps
CPU time 2.64 seconds
Started Aug 09 05:36:05 PM PDT 24
Finished Aug 09 05:36:08 PM PDT 24
Peak memory 201372 kb
Host smart-054369b6-4d43-4dff-a2f4-f768271a898a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773699997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.773699997
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.4188869117
Short name T416
Test name
Test status
Simulation time 5950020152 ps
CPU time 7.15 seconds
Started Aug 09 05:36:01 PM PDT 24
Finished Aug 09 05:36:08 PM PDT 24
Peak memory 201348 kb
Host smart-9d53dd7e-3def-4cab-90bb-d78c0e35b4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188869117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4188869117
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3906039045
Short name T213
Test name
Test status
Simulation time 504813603423 ps
CPU time 629.24 seconds
Started Aug 09 05:36:09 PM PDT 24
Finished Aug 09 05:46:38 PM PDT 24
Peak memory 201692 kb
Host smart-67245deb-55ba-42d0-ad7b-4227362b2e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906039045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3906039045
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3089224491
Short name T706
Test name
Test status
Simulation time 382082884 ps
CPU time 0.83 seconds
Started Aug 09 05:36:12 PM PDT 24
Finished Aug 09 05:36:13 PM PDT 24
Peak memory 201260 kb
Host smart-e9e0c4fb-a33a-465a-8512-64a74ec1583d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089224491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3089224491
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.86416634
Short name T214
Test name
Test status
Simulation time 323356299685 ps
CPU time 563.32 seconds
Started Aug 09 05:36:14 PM PDT 24
Finished Aug 09 05:45:37 PM PDT 24
Peak memory 201488 kb
Host smart-3aceb603-877c-407a-8090-d239c11eb429
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86416634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gatin
g.86416634
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2342519827
Short name T161
Test name
Test status
Simulation time 371572761690 ps
CPU time 126.72 seconds
Started Aug 09 05:36:13 PM PDT 24
Finished Aug 09 05:38:20 PM PDT 24
Peak memory 201408 kb
Host smart-745bcd46-e690-4075-b30f-376454594a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342519827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2342519827
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3126493556
Short name T583
Test name
Test status
Simulation time 322883422053 ps
CPU time 182.68 seconds
Started Aug 09 05:36:13 PM PDT 24
Finished Aug 09 05:39:16 PM PDT 24
Peak memory 201500 kb
Host smart-a2f3c180-4691-4102-b909-2d01c48228b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126493556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3126493556
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3428130904
Short name T333
Test name
Test status
Simulation time 161747421138 ps
CPU time 358.49 seconds
Started Aug 09 05:36:14 PM PDT 24
Finished Aug 09 05:42:13 PM PDT 24
Peak memory 201476 kb
Host smart-bb6fd1af-d982-4cb4-8a04-3b2c2b006c77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428130904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3428130904
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2584624760
Short name T139
Test name
Test status
Simulation time 499850914937 ps
CPU time 267.21 seconds
Started Aug 09 05:36:14 PM PDT 24
Finished Aug 09 05:40:41 PM PDT 24
Peak memory 201452 kb
Host smart-c41b7629-f52e-45e4-b070-b740d08802f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584624760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2584624760
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2011782792
Short name T417
Test name
Test status
Simulation time 165606165944 ps
CPU time 93.9 seconds
Started Aug 09 05:36:17 PM PDT 24
Finished Aug 09 05:37:51 PM PDT 24
Peak memory 201384 kb
Host smart-d456d27d-98b5-43e1-a38c-79c8f3cd54e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011782792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2011782792
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.473059094
Short name T159
Test name
Test status
Simulation time 183741704821 ps
CPU time 112.19 seconds
Started Aug 09 05:36:14 PM PDT 24
Finished Aug 09 05:38:07 PM PDT 24
Peak memory 201316 kb
Host smart-32f22190-1d7b-4b5f-8baf-255e939d840b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473059094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.473059094
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2259893932
Short name T719
Test name
Test status
Simulation time 197488665652 ps
CPU time 242.39 seconds
Started Aug 09 05:36:13 PM PDT 24
Finished Aug 09 05:40:16 PM PDT 24
Peak memory 201380 kb
Host smart-1cbbd01c-b2d3-4785-8dd5-75fbfe1a9633
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259893932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2259893932
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.4224345957
Short name T723
Test name
Test status
Simulation time 92941905258 ps
CPU time 320.12 seconds
Started Aug 09 05:36:14 PM PDT 24
Finished Aug 09 05:41:34 PM PDT 24
Peak memory 201824 kb
Host smart-b1e5e64f-c0b1-4e9e-b766-44648c4ea2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224345957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.4224345957
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1243992798
Short name T791
Test name
Test status
Simulation time 39437118636 ps
CPU time 44.61 seconds
Started Aug 09 05:36:13 PM PDT 24
Finished Aug 09 05:36:58 PM PDT 24
Peak memory 201220 kb
Host smart-c6193a75-570a-4235-a189-63a4c5bf80f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243992798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1243992798
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3847855544
Short name T562
Test name
Test status
Simulation time 4420056831 ps
CPU time 1.65 seconds
Started Aug 09 05:36:14 PM PDT 24
Finished Aug 09 05:36:16 PM PDT 24
Peak memory 201320 kb
Host smart-78b6b0a2-8093-4e02-8984-70d2777dae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847855544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3847855544
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.576883125
Short name T711
Test name
Test status
Simulation time 5686777592 ps
CPU time 13.77 seconds
Started Aug 09 05:36:06 PM PDT 24
Finished Aug 09 05:36:20 PM PDT 24
Peak memory 201252 kb
Host smart-3c409e78-25ae-4b5b-960f-ea3dc0c3cd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576883125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.576883125
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3066907171
Short name T630
Test name
Test status
Simulation time 28527180069 ps
CPU time 144.42 seconds
Started Aug 09 05:36:14 PM PDT 24
Finished Aug 09 05:38:38 PM PDT 24
Peak memory 210084 kb
Host smart-a72e8e6b-82f0-4e46-a9f2-8d8cdd4f973f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066907171 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3066907171
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1542080815
Short name T95
Test name
Test status
Simulation time 473291353 ps
CPU time 0.86 seconds
Started Aug 09 05:36:21 PM PDT 24
Finished Aug 09 05:36:22 PM PDT 24
Peak memory 201116 kb
Host smart-7c2ccc58-b881-46cd-ae90-838af1c90ce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542080815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1542080815
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2709878520
Short name T292
Test name
Test status
Simulation time 353867933994 ps
CPU time 784.73 seconds
Started Aug 09 05:36:20 PM PDT 24
Finished Aug 09 05:49:25 PM PDT 24
Peak memory 201376 kb
Host smart-737477b5-b70d-4895-a09c-feea62a91814
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709878520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2709878520
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3421601408
Short name T643
Test name
Test status
Simulation time 491183464495 ps
CPU time 489.15 seconds
Started Aug 09 05:36:19 PM PDT 24
Finished Aug 09 05:44:28 PM PDT 24
Peak memory 201536 kb
Host smart-d317cd6d-67dc-4919-a437-270d6923530d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421601408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3421601408
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3849821217
Short name T84
Test name
Test status
Simulation time 492291610844 ps
CPU time 973.53 seconds
Started Aug 09 05:36:20 PM PDT 24
Finished Aug 09 05:52:33 PM PDT 24
Peak memory 201340 kb
Host smart-c8be0464-c34b-4b53-a511-2a6244ee9a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849821217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3849821217
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.346852292
Short name T43
Test name
Test status
Simulation time 325907646247 ps
CPU time 321.4 seconds
Started Aug 09 05:36:20 PM PDT 24
Finished Aug 09 05:41:42 PM PDT 24
Peak memory 201380 kb
Host smart-d4096643-a50e-46cd-b81d-f20f67f608a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=346852292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.346852292
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1336181493
Short name T32
Test name
Test status
Simulation time 460887315568 ps
CPU time 108.43 seconds
Started Aug 09 05:36:21 PM PDT 24
Finished Aug 09 05:38:09 PM PDT 24
Peak memory 201372 kb
Host smart-d9bf113f-de9e-4370-b454-ebc7f011b01d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336181493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1336181493
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.976183223
Short name T546
Test name
Test status
Simulation time 402585205133 ps
CPU time 233.93 seconds
Started Aug 09 05:36:18 PM PDT 24
Finished Aug 09 05:40:12 PM PDT 24
Peak memory 201412 kb
Host smart-166e5aa3-5de6-48eb-b457-655e35922f31
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976183223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.976183223
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.249558689
Short name T183
Test name
Test status
Simulation time 115272806508 ps
CPU time 408.03 seconds
Started Aug 09 05:36:19 PM PDT 24
Finished Aug 09 05:43:07 PM PDT 24
Peak memory 201796 kb
Host smart-de7092c8-63f6-46a8-9293-60d23580b027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249558689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.249558689
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3653306846
Short name T531
Test name
Test status
Simulation time 22208406562 ps
CPU time 6.91 seconds
Started Aug 09 05:36:18 PM PDT 24
Finished Aug 09 05:36:25 PM PDT 24
Peak memory 201332 kb
Host smart-59b94e28-0c48-4034-87be-1aac45284c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653306846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3653306846
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.854526137
Short name T404
Test name
Test status
Simulation time 4961711463 ps
CPU time 3.34 seconds
Started Aug 09 05:36:21 PM PDT 24
Finished Aug 09 05:36:24 PM PDT 24
Peak memory 201272 kb
Host smart-8b6042dc-3c89-4a42-a114-0e745e3abf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854526137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.854526137
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1595460135
Short name T664
Test name
Test status
Simulation time 5654964241 ps
CPU time 7.06 seconds
Started Aug 09 05:36:14 PM PDT 24
Finished Aug 09 05:36:21 PM PDT 24
Peak memory 201288 kb
Host smart-f923e421-3e63-4719-aeaf-cea8db25960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595460135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1595460135
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1498344175
Short name T187
Test name
Test status
Simulation time 205579659121 ps
CPU time 822.96 seconds
Started Aug 09 05:36:20 PM PDT 24
Finished Aug 09 05:50:03 PM PDT 24
Peak memory 218092 kb
Host smart-3d341df3-882c-46cd-9d9d-317aa2597836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498344175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1498344175
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.4121797410
Short name T486
Test name
Test status
Simulation time 326717682 ps
CPU time 0.76 seconds
Started Aug 09 05:36:27 PM PDT 24
Finished Aug 09 05:36:28 PM PDT 24
Peak memory 201104 kb
Host smart-793130d4-ca11-461a-9866-e9f54747e53a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121797410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.4121797410
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1531017703
Short name T580
Test name
Test status
Simulation time 350459671813 ps
CPU time 415.75 seconds
Started Aug 09 05:36:27 PM PDT 24
Finished Aug 09 05:43:22 PM PDT 24
Peak memory 201464 kb
Host smart-2be8b586-01cc-4a46-9db2-260878be60d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531017703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1531017703
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4017460318
Short name T227
Test name
Test status
Simulation time 161677547302 ps
CPU time 90.11 seconds
Started Aug 09 05:36:19 PM PDT 24
Finished Aug 09 05:37:49 PM PDT 24
Peak memory 201336 kb
Host smart-e27687b9-5373-4c40-8fb4-872c8759fc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017460318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4017460318
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.344860549
Short name T576
Test name
Test status
Simulation time 164614860955 ps
CPU time 339.46 seconds
Started Aug 09 05:36:26 PM PDT 24
Finished Aug 09 05:42:06 PM PDT 24
Peak memory 201304 kb
Host smart-f77e12a7-6aba-4b30-a223-511c9ed9ae63
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=344860549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.344860549
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2823322759
Short name T198
Test name
Test status
Simulation time 162113139548 ps
CPU time 182.15 seconds
Started Aug 09 05:36:22 PM PDT 24
Finished Aug 09 05:39:25 PM PDT 24
Peak memory 201292 kb
Host smart-b23cedb0-fb49-4a81-9b36-6074a7cf320a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823322759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2823322759
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2743598716
Short name T509
Test name
Test status
Simulation time 333528113146 ps
CPU time 689.21 seconds
Started Aug 09 05:36:20 PM PDT 24
Finished Aug 09 05:47:49 PM PDT 24
Peak memory 201456 kb
Host smart-25f146dc-1974-4faa-90a3-131cd7dd0cbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743598716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2743598716
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.67868383
Short name T145
Test name
Test status
Simulation time 178207233503 ps
CPU time 192.73 seconds
Started Aug 09 05:36:25 PM PDT 24
Finished Aug 09 05:39:38 PM PDT 24
Peak memory 201304 kb
Host smart-01228e5f-88dc-47b8-b659-f21fe6bf25a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67868383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_w
akeup.67868383
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1471650283
Short name T468
Test name
Test status
Simulation time 409567333914 ps
CPU time 92.52 seconds
Started Aug 09 05:36:25 PM PDT 24
Finished Aug 09 05:37:57 PM PDT 24
Peak memory 201312 kb
Host smart-72346b29-47aa-4765-ab4b-7b3b710a30a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471650283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1471650283
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3215609535
Short name T679
Test name
Test status
Simulation time 34540111502 ps
CPU time 27.25 seconds
Started Aug 09 05:36:25 PM PDT 24
Finished Aug 09 05:36:52 PM PDT 24
Peak memory 201208 kb
Host smart-a7d368d7-0a14-4ee8-8a32-9aa003c782a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215609535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3215609535
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1959908663
Short name T466
Test name
Test status
Simulation time 5712543824 ps
CPU time 7.72 seconds
Started Aug 09 05:36:24 PM PDT 24
Finished Aug 09 05:36:32 PM PDT 24
Peak memory 201312 kb
Host smart-96d876b8-67a0-4ea7-b19f-d7f97ca689fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959908663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1959908663
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1229172420
Short name T496
Test name
Test status
Simulation time 5945365084 ps
CPU time 14.59 seconds
Started Aug 09 05:36:19 PM PDT 24
Finished Aug 09 05:36:34 PM PDT 24
Peak memory 201268 kb
Host smart-bd01035b-234a-4bfe-becb-a7f8abebf9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229172420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1229172420
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3409850378
Short name T240
Test name
Test status
Simulation time 210419013755 ps
CPU time 224.09 seconds
Started Aug 09 05:36:25 PM PDT 24
Finished Aug 09 05:40:09 PM PDT 24
Peak memory 201472 kb
Host smart-c52e76b8-04f6-4a3c-9547-d89b37d99a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409850378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3409850378
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.900602888
Short name T323
Test name
Test status
Simulation time 170028693940 ps
CPU time 596.9 seconds
Started Aug 09 05:36:25 PM PDT 24
Finished Aug 09 05:46:22 PM PDT 24
Peak memory 210156 kb
Host smart-6568272b-184d-4417-b56c-9cb9e9bd2be6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900602888 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.900602888
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3919901429
Short name T571
Test name
Test status
Simulation time 477693747 ps
CPU time 0.86 seconds
Started Aug 09 05:36:39 PM PDT 24
Finished Aug 09 05:36:40 PM PDT 24
Peak memory 201124 kb
Host smart-92332add-5754-4826-92ad-465c0fb337fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919901429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3919901429
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.236513898
Short name T300
Test name
Test status
Simulation time 508931076676 ps
CPU time 75.31 seconds
Started Aug 09 05:36:32 PM PDT 24
Finished Aug 09 05:37:48 PM PDT 24
Peak memory 201456 kb
Host smart-0968769c-3af5-4cc9-813b-d620cbeea8ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236513898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.236513898
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.50894179
Short name T781
Test name
Test status
Simulation time 485944694866 ps
CPU time 1060.37 seconds
Started Aug 09 05:36:31 PM PDT 24
Finished Aug 09 05:54:11 PM PDT 24
Peak memory 201432 kb
Host smart-102756c5-c809-47a9-8fc8-9b69350f2c8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=50894179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt
_fixed.50894179
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1420209471
Short name T669
Test name
Test status
Simulation time 165117681578 ps
CPU time 96.08 seconds
Started Aug 09 05:36:32 PM PDT 24
Finished Aug 09 05:38:08 PM PDT 24
Peak memory 201516 kb
Host smart-69057326-5245-42c6-b7b9-0c8f25a45c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420209471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1420209471
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1007306940
Short name T368
Test name
Test status
Simulation time 485221791529 ps
CPU time 267.87 seconds
Started Aug 09 05:36:32 PM PDT 24
Finished Aug 09 05:41:00 PM PDT 24
Peak memory 201332 kb
Host smart-fc190e63-9c2f-485e-852c-033405a06d11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007306940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1007306940
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2808230950
Short name T6
Test name
Test status
Simulation time 595007263762 ps
CPU time 350.09 seconds
Started Aug 09 05:36:33 PM PDT 24
Finished Aug 09 05:42:23 PM PDT 24
Peak memory 201456 kb
Host smart-f91b3ea5-ffa4-43df-84a0-cac3b974c809
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808230950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2808230950
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.60961035
Short name T103
Test name
Test status
Simulation time 134010158077 ps
CPU time 593.37 seconds
Started Aug 09 05:36:37 PM PDT 24
Finished Aug 09 05:46:30 PM PDT 24
Peak memory 201820 kb
Host smart-71708088-4381-4c10-8922-be82dd494d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60961035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.60961035
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.53897206
Short name T687
Test name
Test status
Simulation time 36708365945 ps
CPU time 19.34 seconds
Started Aug 09 05:36:37 PM PDT 24
Finished Aug 09 05:36:57 PM PDT 24
Peak memory 201300 kb
Host smart-c9c1a524-3e8d-4d5c-bb4f-756759b9a7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53897206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.53897206
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1490512292
Short name T348
Test name
Test status
Simulation time 3765468192 ps
CPU time 6.93 seconds
Started Aug 09 05:36:31 PM PDT 24
Finished Aug 09 05:36:38 PM PDT 24
Peak memory 201244 kb
Host smart-0ae48365-8a70-4406-8994-393ef2f2811e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490512292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1490512292
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1712049468
Short name T443
Test name
Test status
Simulation time 5718109983 ps
CPU time 13.12 seconds
Started Aug 09 05:36:23 PM PDT 24
Finished Aug 09 05:36:36 PM PDT 24
Peak memory 201312 kb
Host smart-6ab454cf-aaac-4eec-ada5-de7493497cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712049468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1712049468
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.4267054700
Short name T757
Test name
Test status
Simulation time 683214990658 ps
CPU time 781.17 seconds
Started Aug 09 05:36:38 PM PDT 24
Finished Aug 09 05:49:39 PM PDT 24
Peak memory 210012 kb
Host smart-574d78f0-56e0-4fb2-9ac6-267bba85566e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267054700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.4267054700
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3393853104
Short name T20
Test name
Test status
Simulation time 72261597355 ps
CPU time 153.24 seconds
Started Aug 09 05:36:39 PM PDT 24
Finished Aug 09 05:39:12 PM PDT 24
Peak memory 218008 kb
Host smart-874bface-2581-4324-b4a6-9c8494511974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393853104 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3393853104
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.404600217
Short name T14
Test name
Test status
Simulation time 514310071 ps
CPU time 1.59 seconds
Started Aug 09 05:36:44 PM PDT 24
Finished Aug 09 05:36:46 PM PDT 24
Peak memory 201256 kb
Host smart-2d454c21-2e26-48c0-8b83-424e66e5cec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404600217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.404600217
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2781705703
Short name T127
Test name
Test status
Simulation time 511218607328 ps
CPU time 997.86 seconds
Started Aug 09 05:36:39 PM PDT 24
Finished Aug 09 05:53:17 PM PDT 24
Peak memory 201304 kb
Host smart-0aa38d9a-77b9-4e29-a74b-355deb06d194
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781705703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2781705703
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.965408321
Short name T193
Test name
Test status
Simulation time 362896664023 ps
CPU time 853.19 seconds
Started Aug 09 05:36:39 PM PDT 24
Finished Aug 09 05:50:52 PM PDT 24
Peak memory 201460 kb
Host smart-84c8457a-0cc3-428a-91f8-0f660a34d502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965408321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.965408321
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.872074606
Short name T287
Test name
Test status
Simulation time 164247626032 ps
CPU time 110.06 seconds
Started Aug 09 05:36:37 PM PDT 24
Finished Aug 09 05:38:27 PM PDT 24
Peak memory 201336 kb
Host smart-5416a50e-bd7f-443e-9afa-a71b386fe226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872074606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.872074606
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.4228811020
Short name T451
Test name
Test status
Simulation time 492996293996 ps
CPU time 1175.12 seconds
Started Aug 09 05:36:37 PM PDT 24
Finished Aug 09 05:56:12 PM PDT 24
Peak memory 201636 kb
Host smart-c05aeb8a-c278-432e-af07-9d846a97e7e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228811020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.4228811020
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1503510946
Short name T279
Test name
Test status
Simulation time 486250080044 ps
CPU time 285.86 seconds
Started Aug 09 05:36:38 PM PDT 24
Finished Aug 09 05:41:24 PM PDT 24
Peak memory 201448 kb
Host smart-eb9d4b47-e2d4-495d-8d69-d2f9e86cfd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503510946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1503510946
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3882613338
Short name T384
Test name
Test status
Simulation time 494248466231 ps
CPU time 104.35 seconds
Started Aug 09 05:36:37 PM PDT 24
Finished Aug 09 05:38:21 PM PDT 24
Peak memory 201404 kb
Host smart-aa94ed19-42f1-4bfe-ba1b-1dbc2d3777c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882613338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3882613338
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.172904707
Short name T674
Test name
Test status
Simulation time 173273947546 ps
CPU time 414.38 seconds
Started Aug 09 05:36:37 PM PDT 24
Finished Aug 09 05:43:32 PM PDT 24
Peak memory 201296 kb
Host smart-d1c316dc-c860-4d80-9246-e69202908181
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172904707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.172904707
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2073038976
Short name T526
Test name
Test status
Simulation time 609524904933 ps
CPU time 672.68 seconds
Started Aug 09 05:36:38 PM PDT 24
Finished Aug 09 05:47:51 PM PDT 24
Peak memory 201456 kb
Host smart-74fb426a-3a45-4115-bea8-9271692091c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073038976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2073038976
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1786401544
Short name T488
Test name
Test status
Simulation time 65970643821 ps
CPU time 249.9 seconds
Started Aug 09 05:36:43 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 201728 kb
Host smart-39d2e325-a8be-48b2-995b-100452dbbb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786401544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1786401544
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3279395691
Short name T575
Test name
Test status
Simulation time 22842514344 ps
CPU time 49.48 seconds
Started Aug 09 05:36:36 PM PDT 24
Finished Aug 09 05:37:26 PM PDT 24
Peak memory 201332 kb
Host smart-f3426e83-eb10-4273-86e7-4aea5c0dc605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279395691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3279395691
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2739714850
Short name T729
Test name
Test status
Simulation time 3527803016 ps
CPU time 2.39 seconds
Started Aug 09 05:36:37 PM PDT 24
Finished Aug 09 05:36:39 PM PDT 24
Peak memory 201292 kb
Host smart-cb73fc6c-44ea-44d6-9584-a2915b051b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739714850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2739714850
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1543174708
Short name T749
Test name
Test status
Simulation time 5770933151 ps
CPU time 3.94 seconds
Started Aug 09 05:36:36 PM PDT 24
Finished Aug 09 05:36:40 PM PDT 24
Peak memory 201328 kb
Host smart-3ce85868-503b-4d70-a048-70c61e2c0f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543174708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1543174708
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1783787645
Short name T271
Test name
Test status
Simulation time 173771112363 ps
CPU time 107.44 seconds
Started Aug 09 05:36:42 PM PDT 24
Finished Aug 09 05:38:29 PM PDT 24
Peak memory 201376 kb
Host smart-1d554a25-231a-4e26-9f8d-29b36f5de729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783787645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1783787645
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1422948360
Short name T713
Test name
Test status
Simulation time 468782783 ps
CPU time 1.64 seconds
Started Aug 09 05:36:51 PM PDT 24
Finished Aug 09 05:36:53 PM PDT 24
Peak memory 201208 kb
Host smart-7bffa9e4-5711-4ab9-9159-5fa9941eaf9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422948360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1422948360
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2812506665
Short name T412
Test name
Test status
Simulation time 188707415408 ps
CPU time 407.36 seconds
Started Aug 09 05:36:50 PM PDT 24
Finished Aug 09 05:43:38 PM PDT 24
Peak memory 201432 kb
Host smart-66c9c424-4a60-465e-a62d-a9b317daabbc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812506665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2812506665
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2443160089
Short name T494
Test name
Test status
Simulation time 161595549400 ps
CPU time 376.2 seconds
Started Aug 09 05:36:43 PM PDT 24
Finished Aug 09 05:42:59 PM PDT 24
Peak memory 201404 kb
Host smart-b54633cd-0c0e-4972-8f69-8677f038bad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443160089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2443160089
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2690220940
Short name T421
Test name
Test status
Simulation time 326121205598 ps
CPU time 680.79 seconds
Started Aug 09 05:36:45 PM PDT 24
Finished Aug 09 05:48:06 PM PDT 24
Peak memory 201516 kb
Host smart-55ab7deb-6c59-4d94-bc8e-41b195df8f02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690220940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2690220940
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2628385842
Short name T280
Test name
Test status
Simulation time 165830245748 ps
CPU time 36.14 seconds
Started Aug 09 05:36:42 PM PDT 24
Finished Aug 09 05:37:18 PM PDT 24
Peak memory 201352 kb
Host smart-68846766-0f05-4679-be0f-5b791c156175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628385842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2628385842
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1349202932
Short name T689
Test name
Test status
Simulation time 159697638182 ps
CPU time 362.7 seconds
Started Aug 09 05:36:44 PM PDT 24
Finished Aug 09 05:42:47 PM PDT 24
Peak memory 201436 kb
Host smart-11480060-1b91-441d-af13-339d109ef232
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349202932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1349202932
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.737967263
Short name T254
Test name
Test status
Simulation time 357530538708 ps
CPU time 400.82 seconds
Started Aug 09 05:36:44 PM PDT 24
Finished Aug 09 05:43:25 PM PDT 24
Peak memory 201404 kb
Host smart-13d2a356-bbeb-4282-90e0-0ab402d4d2d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737967263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.737967263
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3172491556
Short name T467
Test name
Test status
Simulation time 401584066882 ps
CPU time 483.34 seconds
Started Aug 09 05:36:49 PM PDT 24
Finished Aug 09 05:44:53 PM PDT 24
Peak memory 201456 kb
Host smart-ce3e4871-f91a-4b47-a759-bacb6f8cace0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172491556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3172491556
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1015153630
Short name T772
Test name
Test status
Simulation time 122066585661 ps
CPU time 588.73 seconds
Started Aug 09 05:36:52 PM PDT 24
Finished Aug 09 05:46:41 PM PDT 24
Peak memory 201688 kb
Host smart-055a8f92-3a73-45c9-be9e-e3d6a4453288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015153630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1015153630
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1739266986
Short name T338
Test name
Test status
Simulation time 28498657522 ps
CPU time 63.34 seconds
Started Aug 09 05:36:50 PM PDT 24
Finished Aug 09 05:37:53 PM PDT 24
Peak memory 201312 kb
Host smart-b5f34fd2-83ff-4855-b36b-ba0297c16275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739266986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1739266986
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1883172634
Short name T530
Test name
Test status
Simulation time 4698125116 ps
CPU time 3.42 seconds
Started Aug 09 05:36:52 PM PDT 24
Finished Aug 09 05:36:56 PM PDT 24
Peak memory 201224 kb
Host smart-3d9f44bf-07eb-40ac-82cc-b3af1f8f7896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883172634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1883172634
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3042466091
Short name T564
Test name
Test status
Simulation time 5661761921 ps
CPU time 4 seconds
Started Aug 09 05:36:43 PM PDT 24
Finished Aug 09 05:36:47 PM PDT 24
Peak memory 201320 kb
Host smart-ddc7dc48-4d2a-475a-9282-74a98b7e9845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042466091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3042466091
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1218579369
Short name T220
Test name
Test status
Simulation time 164806867728 ps
CPU time 398.18 seconds
Started Aug 09 05:36:49 PM PDT 24
Finished Aug 09 05:43:27 PM PDT 24
Peak memory 201440 kb
Host smart-31e5db1a-b01b-4f78-a6a9-2b030385c4d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218579369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1218579369
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3556495253
Short name T37
Test name
Test status
Simulation time 87278610880 ps
CPU time 221.06 seconds
Started Aug 09 05:36:49 PM PDT 24
Finished Aug 09 05:40:30 PM PDT 24
Peak memory 210204 kb
Host smart-e78ca76c-6e3f-409e-8eb9-70097faa8244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556495253 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3556495253
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.965349047
Short name T694
Test name
Test status
Simulation time 444503586 ps
CPU time 0.84 seconds
Started Aug 09 05:35:01 PM PDT 24
Finished Aug 09 05:35:02 PM PDT 24
Peak memory 201128 kb
Host smart-cc547127-f905-41a0-8e14-693745c41abb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965349047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.965349047
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3771382324
Short name T505
Test name
Test status
Simulation time 370932244224 ps
CPU time 319.02 seconds
Started Aug 09 05:35:19 PM PDT 24
Finished Aug 09 05:40:38 PM PDT 24
Peak memory 201412 kb
Host smart-b5d4b9b0-9821-4be5-93ec-7f38879c0589
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771382324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3771382324
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2128537654
Short name T717
Test name
Test status
Simulation time 325207203724 ps
CPU time 185.82 seconds
Started Aug 09 05:35:05 PM PDT 24
Finished Aug 09 05:38:11 PM PDT 24
Peak memory 201392 kb
Host smart-6c532a0a-b9d8-4d01-b20f-afc60be2a4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128537654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2128537654
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2550456231
Short name T705
Test name
Test status
Simulation time 491164068423 ps
CPU time 219.04 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:38:53 PM PDT 24
Peak memory 201324 kb
Host smart-392ecb49-fdc9-4847-b7e4-5cab2f8a4c5b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550456231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2550456231
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3759287314
Short name T385
Test name
Test status
Simulation time 160071503306 ps
CPU time 364.63 seconds
Started Aug 09 05:35:02 PM PDT 24
Finished Aug 09 05:41:07 PM PDT 24
Peak memory 201312 kb
Host smart-4245a7bc-cc2d-4f08-8066-935c32e7c887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759287314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3759287314
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2018846849
Short name T748
Test name
Test status
Simulation time 318904817716 ps
CPU time 693.37 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:46:38 PM PDT 24
Peak memory 201400 kb
Host smart-fdfdc5f9-ad78-4130-a424-539987844813
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018846849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2018846849
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3263642832
Short name T779
Test name
Test status
Simulation time 177789341861 ps
CPU time 218.95 seconds
Started Aug 09 05:34:51 PM PDT 24
Finished Aug 09 05:38:30 PM PDT 24
Peak memory 201388 kb
Host smart-0ec88e2c-e2d5-4e25-995f-77442ae25f5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263642832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3263642832
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3386062311
Short name T542
Test name
Test status
Simulation time 590584060338 ps
CPU time 635.66 seconds
Started Aug 09 05:35:11 PM PDT 24
Finished Aug 09 05:45:47 PM PDT 24
Peak memory 201420 kb
Host smart-a499979e-dfbc-4850-905d-a348c180153e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386062311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3386062311
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2298908008
Short name T182
Test name
Test status
Simulation time 124501934380 ps
CPU time 504.97 seconds
Started Aug 09 05:35:08 PM PDT 24
Finished Aug 09 05:43:33 PM PDT 24
Peak memory 201924 kb
Host smart-75fda6e1-8fa8-42cd-87bc-ad5be026a2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298908008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2298908008
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.79845715
Short name T598
Test name
Test status
Simulation time 29321289170 ps
CPU time 18 seconds
Started Aug 09 05:35:01 PM PDT 24
Finished Aug 09 05:35:19 PM PDT 24
Peak memory 201296 kb
Host smart-1bf436f1-de43-43e7-af3c-20285216d760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79845715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.79845715
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1595643776
Short name T413
Test name
Test status
Simulation time 2939078796 ps
CPU time 7.18 seconds
Started Aug 09 05:35:03 PM PDT 24
Finished Aug 09 05:35:10 PM PDT 24
Peak memory 201268 kb
Host smart-d0f9c2ad-f21e-4b4a-b91e-0ff77ae6369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595643776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1595643776
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2424068522
Short name T81
Test name
Test status
Simulation time 8001954728 ps
CPU time 5.75 seconds
Started Aug 09 05:34:57 PM PDT 24
Finished Aug 09 05:35:03 PM PDT 24
Peak memory 218312 kb
Host smart-cb1ca589-fb75-4a81-b46c-62f9117899a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424068522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2424068522
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2144291547
Short name T759
Test name
Test status
Simulation time 5944702293 ps
CPU time 14.77 seconds
Started Aug 09 05:35:07 PM PDT 24
Finished Aug 09 05:35:22 PM PDT 24
Peak memory 201360 kb
Host smart-ec056a4c-6eac-40b3-9fb9-041fafac5712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144291547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2144291547
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1298725465
Short name T532
Test name
Test status
Simulation time 163719563521 ps
CPU time 198.57 seconds
Started Aug 09 05:34:59 PM PDT 24
Finished Aug 09 05:38:18 PM PDT 24
Peak memory 201408 kb
Host smart-20590006-cbc9-47a0-b37b-36de8997e3a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298725465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1298725465
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1717798795
Short name T231
Test name
Test status
Simulation time 329467065969 ps
CPU time 179.77 seconds
Started Aug 09 05:35:21 PM PDT 24
Finished Aug 09 05:38:21 PM PDT 24
Peak memory 209724 kb
Host smart-e1df0de3-faa8-490c-8cca-bf074d57a809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717798795 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1717798795
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2477013002
Short name T685
Test name
Test status
Simulation time 525150969 ps
CPU time 0.78 seconds
Started Aug 09 05:36:56 PM PDT 24
Finished Aug 09 05:36:57 PM PDT 24
Peak memory 201192 kb
Host smart-25388e97-8807-4e8d-a514-813255fbab26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477013002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2477013002
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1530832319
Short name T313
Test name
Test status
Simulation time 214195831068 ps
CPU time 474.4 seconds
Started Aug 09 05:36:57 PM PDT 24
Finished Aug 09 05:44:52 PM PDT 24
Peak memory 201456 kb
Host smart-f5b273c4-4776-42de-9e71-2d451a5d19f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530832319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1530832319
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3174147057
Short name T299
Test name
Test status
Simulation time 487113890887 ps
CPU time 995.31 seconds
Started Aug 09 05:36:55 PM PDT 24
Finished Aug 09 05:53:30 PM PDT 24
Peak memory 201376 kb
Host smart-5f755b06-3243-49d8-b9c6-a8b3f4d6341c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174147057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3174147057
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2297128993
Short name T294
Test name
Test status
Simulation time 170145819924 ps
CPU time 104.69 seconds
Started Aug 09 05:36:49 PM PDT 24
Finished Aug 09 05:38:34 PM PDT 24
Peak memory 201476 kb
Host smart-ce9f15bd-7405-4453-b3f3-3e5e6c40c79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297128993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2297128993
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1138354764
Short name T433
Test name
Test status
Simulation time 168120940679 ps
CPU time 394.79 seconds
Started Aug 09 05:36:48 PM PDT 24
Finished Aug 09 05:43:23 PM PDT 24
Peak memory 201312 kb
Host smart-29b9d5b0-90ee-48b8-a41a-3b6522d58444
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138354764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1138354764
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2517170625
Short name T556
Test name
Test status
Simulation time 492353611117 ps
CPU time 1156.55 seconds
Started Aug 09 05:36:49 PM PDT 24
Finished Aug 09 05:56:06 PM PDT 24
Peak memory 201468 kb
Host smart-af75d19c-0f29-41f9-acdd-a63454c36a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517170625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2517170625
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.72495364
Short name T143
Test name
Test status
Simulation time 323088669727 ps
CPU time 180.55 seconds
Started Aug 09 05:36:49 PM PDT 24
Finished Aug 09 05:39:50 PM PDT 24
Peak memory 201428 kb
Host smart-5c277498-3816-4eb4-845d-c9e45ab2e667
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=72495364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed
.72495364
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2433473112
Short name T647
Test name
Test status
Simulation time 375541637793 ps
CPU time 810.94 seconds
Started Aug 09 05:36:49 PM PDT 24
Finished Aug 09 05:50:20 PM PDT 24
Peak memory 201404 kb
Host smart-26cd82c4-1d57-43aa-9de0-2daa704981bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433473112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2433473112
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4087974629
Short name T389
Test name
Test status
Simulation time 607845291033 ps
CPU time 716.11 seconds
Started Aug 09 05:36:56 PM PDT 24
Finished Aug 09 05:48:52 PM PDT 24
Peak memory 201448 kb
Host smart-777ef37d-31e4-41df-b91e-6c374efe7c11
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087974629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4087974629
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.4198825664
Short name T666
Test name
Test status
Simulation time 77988495301 ps
CPU time 271 seconds
Started Aug 09 05:36:57 PM PDT 24
Finished Aug 09 05:41:28 PM PDT 24
Peak memory 201748 kb
Host smart-5a4dbe98-c0cc-4f54-8c83-2fd043dafa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198825664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4198825664
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3255949636
Short name T708
Test name
Test status
Simulation time 44412646495 ps
CPU time 21.12 seconds
Started Aug 09 05:36:57 PM PDT 24
Finished Aug 09 05:37:18 PM PDT 24
Peak memory 201224 kb
Host smart-3c26ae1c-3dfc-4ecc-861c-fa3c16da9016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255949636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3255949636
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1812983701
Short name T709
Test name
Test status
Simulation time 3794012938 ps
CPU time 9.63 seconds
Started Aug 09 05:36:57 PM PDT 24
Finished Aug 09 05:37:07 PM PDT 24
Peak memory 201308 kb
Host smart-2b14795b-727d-4397-a733-904cb7084d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812983701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1812983701
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2042715909
Short name T394
Test name
Test status
Simulation time 5707777593 ps
CPU time 10.42 seconds
Started Aug 09 05:36:50 PM PDT 24
Finished Aug 09 05:37:01 PM PDT 24
Peak memory 201280 kb
Host smart-943dc997-2c68-42ae-8e02-130c853ed755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042715909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2042715909
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3804263248
Short name T54
Test name
Test status
Simulation time 184229543348 ps
CPU time 558.63 seconds
Started Aug 09 05:36:56 PM PDT 24
Finished Aug 09 05:46:15 PM PDT 24
Peak memory 201872 kb
Host smart-4f6d6238-23c0-4675-8f88-8758be8411c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804263248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3804263248
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3249233596
Short name T346
Test name
Test status
Simulation time 542153858 ps
CPU time 0.95 seconds
Started Aug 09 05:37:09 PM PDT 24
Finished Aug 09 05:37:10 PM PDT 24
Peak memory 201260 kb
Host smart-63460033-fcd9-4f3f-8975-64b4c84e4c05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249233596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3249233596
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1614301872
Short name T393
Test name
Test status
Simulation time 484383387598 ps
CPU time 928.61 seconds
Started Aug 09 05:37:01 PM PDT 24
Finished Aug 09 05:52:30 PM PDT 24
Peak memory 201444 kb
Host smart-52f94969-e6b9-42f5-b6fe-a982ae3e8b03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614301872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1614301872
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2280037448
Short name T311
Test name
Test status
Simulation time 487137925829 ps
CPU time 571.92 seconds
Started Aug 09 05:37:03 PM PDT 24
Finished Aug 09 05:46:35 PM PDT 24
Peak memory 201360 kb
Host smart-81bcc634-9e22-4d11-aba1-1a25a5965ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280037448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2280037448
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3645704384
Short name T474
Test name
Test status
Simulation time 328525787692 ps
CPU time 170.51 seconds
Started Aug 09 05:37:02 PM PDT 24
Finished Aug 09 05:39:53 PM PDT 24
Peak memory 201452 kb
Host smart-55bddd14-64cb-44e6-9bb6-2f129d7a7f3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645704384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3645704384
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.4075583222
Short name T150
Test name
Test status
Simulation time 348834801855 ps
CPU time 86.22 seconds
Started Aug 09 05:37:03 PM PDT 24
Finished Aug 09 05:38:30 PM PDT 24
Peak memory 201428 kb
Host smart-325d1e68-5525-4363-8ee6-220b1d19ab36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075583222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.4075583222
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3882330611
Short name T696
Test name
Test status
Simulation time 597945624918 ps
CPU time 1292.61 seconds
Started Aug 09 05:37:02 PM PDT 24
Finished Aug 09 05:58:35 PM PDT 24
Peak memory 201428 kb
Host smart-3a6ca385-4aed-40b6-b932-b1cedacd134c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882330611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3882330611
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2485631873
Short name T456
Test name
Test status
Simulation time 89034829762 ps
CPU time 290.31 seconds
Started Aug 09 05:37:11 PM PDT 24
Finished Aug 09 05:42:01 PM PDT 24
Peak memory 201776 kb
Host smart-38479538-57d0-4a6f-ac5d-c014ec2e0888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485631873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2485631873
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1039394363
Short name T698
Test name
Test status
Simulation time 23934828603 ps
CPU time 48.95 seconds
Started Aug 09 05:37:08 PM PDT 24
Finished Aug 09 05:37:57 PM PDT 24
Peak memory 201328 kb
Host smart-3268867e-2d58-4dca-8d74-08bfa1bbf2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039394363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1039394363
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2969362230
Short name T615
Test name
Test status
Simulation time 3395505991 ps
CPU time 8.29 seconds
Started Aug 09 05:37:08 PM PDT 24
Finished Aug 09 05:37:17 PM PDT 24
Peak memory 201220 kb
Host smart-4639b76b-aaca-45fa-900b-59dbea0cc6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969362230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2969362230
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.861685019
Short name T367
Test name
Test status
Simulation time 5896162987 ps
CPU time 14.66 seconds
Started Aug 09 05:37:04 PM PDT 24
Finished Aug 09 05:37:18 PM PDT 24
Peak memory 201272 kb
Host smart-e42e5eca-ac45-48a1-9528-bd82889d1b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861685019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.861685019
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2018867150
Short name T395
Test name
Test status
Simulation time 367104593 ps
CPU time 0.83 seconds
Started Aug 09 05:37:16 PM PDT 24
Finished Aug 09 05:37:17 PM PDT 24
Peak memory 201164 kb
Host smart-48c1b3b7-93c7-4b75-9138-8c365c48747a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018867150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2018867150
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2201449663
Short name T676
Test name
Test status
Simulation time 175637651611 ps
CPU time 91.64 seconds
Started Aug 09 05:37:16 PM PDT 24
Finished Aug 09 05:38:48 PM PDT 24
Peak memory 201400 kb
Host smart-23175cc5-3a0d-4a84-a0f7-886071a1583c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201449663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2201449663
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1488644705
Short name T734
Test name
Test status
Simulation time 163264430116 ps
CPU time 397.93 seconds
Started Aug 09 05:37:16 PM PDT 24
Finished Aug 09 05:43:55 PM PDT 24
Peak memory 201436 kb
Host smart-99982c22-93cb-43f4-a481-a8c03e7779fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488644705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1488644705
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3763843631
Short name T133
Test name
Test status
Simulation time 162227225528 ps
CPU time 92.04 seconds
Started Aug 09 05:37:18 PM PDT 24
Finished Aug 09 05:38:50 PM PDT 24
Peak memory 201296 kb
Host smart-c42471db-cf05-4a0c-bca8-a335c9d646ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763843631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3763843631
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1518811426
Short name T248
Test name
Test status
Simulation time 479608744976 ps
CPU time 1204.84 seconds
Started Aug 09 05:37:16 PM PDT 24
Finished Aug 09 05:57:22 PM PDT 24
Peak memory 201412 kb
Host smart-6ecd8d2f-dbd0-4fec-9e2c-a0b66098cd08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518811426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1518811426
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.9174039
Short name T519
Test name
Test status
Simulation time 158334574259 ps
CPU time 86.91 seconds
Started Aug 09 05:37:17 PM PDT 24
Finished Aug 09 05:38:44 PM PDT 24
Peak memory 201380 kb
Host smart-80d7c464-ae83-4278-97d0-614db8ff04c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=9174039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed.9174039
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1073250188
Short name T671
Test name
Test status
Simulation time 351704185537 ps
CPU time 100.81 seconds
Started Aug 09 05:37:16 PM PDT 24
Finished Aug 09 05:38:57 PM PDT 24
Peak memory 201392 kb
Host smart-30c5fcce-6c74-4eaa-8028-f8999397af75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073250188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1073250188
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2104937978
Short name T396
Test name
Test status
Simulation time 392379119842 ps
CPU time 823.16 seconds
Started Aug 09 05:37:16 PM PDT 24
Finished Aug 09 05:50:59 PM PDT 24
Peak memory 201396 kb
Host smart-5c07af21-7df1-49a6-a1c1-0223a207ce6a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104937978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2104937978
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3414396577
Short name T191
Test name
Test status
Simulation time 120025228899 ps
CPU time 484.25 seconds
Started Aug 09 05:37:18 PM PDT 24
Finished Aug 09 05:45:23 PM PDT 24
Peak memory 201688 kb
Host smart-b3ab54a0-b825-4f2d-97a8-9c81d490a86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414396577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3414396577
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.977719556
Short name T771
Test name
Test status
Simulation time 42813968108 ps
CPU time 27.25 seconds
Started Aug 09 05:37:17 PM PDT 24
Finished Aug 09 05:37:44 PM PDT 24
Peak memory 201308 kb
Host smart-388fec4a-efb2-49d3-b861-6b082e230aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977719556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.977719556
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1989247310
Short name T635
Test name
Test status
Simulation time 4468442881 ps
CPU time 3.03 seconds
Started Aug 09 05:37:16 PM PDT 24
Finished Aug 09 05:37:19 PM PDT 24
Peak memory 201344 kb
Host smart-ad7bc646-c301-4313-a9e5-4ebf8fa2862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989247310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1989247310
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1101465895
Short name T426
Test name
Test status
Simulation time 5652950333 ps
CPU time 6.75 seconds
Started Aug 09 05:37:08 PM PDT 24
Finished Aug 09 05:37:15 PM PDT 24
Peak memory 201268 kb
Host smart-7a3e5d7c-c58c-48b0-83d2-5c34a05f941f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101465895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1101465895
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.766236574
Short name T233
Test name
Test status
Simulation time 255700571405 ps
CPU time 276.23 seconds
Started Aug 09 05:37:16 PM PDT 24
Finished Aug 09 05:41:52 PM PDT 24
Peak memory 218188 kb
Host smart-33368e5a-2469-4132-b861-2d98298b53ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766236574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
766236574
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.588364
Short name T26
Test name
Test status
Simulation time 36614366349 ps
CPU time 85.49 seconds
Started Aug 09 05:37:16 PM PDT 24
Finished Aug 09 05:38:41 PM PDT 24
Peak memory 209780 kb
Host smart-a75cfcec-aa20-43cb-815a-c69c7e5e0404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588364 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.588364
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3604575629
Short name T594
Test name
Test status
Simulation time 297287548 ps
CPU time 1.26 seconds
Started Aug 09 05:37:33 PM PDT 24
Finished Aug 09 05:37:35 PM PDT 24
Peak memory 201248 kb
Host smart-2edabd3b-f5fe-4307-aacc-719b99b6013f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604575629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3604575629
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2787395797
Short name T151
Test name
Test status
Simulation time 360023710806 ps
CPU time 48.61 seconds
Started Aug 09 05:37:30 PM PDT 24
Finished Aug 09 05:38:18 PM PDT 24
Peak memory 201420 kb
Host smart-84fbd1c5-2c4a-41f9-bd9c-ac317f3da266
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787395797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2787395797
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1936171715
Short name T222
Test name
Test status
Simulation time 170437665355 ps
CPU time 109.71 seconds
Started Aug 09 05:37:29 PM PDT 24
Finished Aug 09 05:39:19 PM PDT 24
Peak memory 201384 kb
Host smart-92f480a0-52cf-40f1-8b31-dd34952ed660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936171715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1936171715
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1202895878
Short name T399
Test name
Test status
Simulation time 340086510853 ps
CPU time 218.6 seconds
Started Aug 09 05:37:24 PM PDT 24
Finished Aug 09 05:41:02 PM PDT 24
Peak memory 201404 kb
Host smart-08ae2c5f-f5c8-44fe-b32e-d9f26bed3d99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202895878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1202895878
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2140294842
Short name T736
Test name
Test status
Simulation time 486929718381 ps
CPU time 1041.4 seconds
Started Aug 09 05:37:22 PM PDT 24
Finished Aug 09 05:54:44 PM PDT 24
Peak memory 201488 kb
Host smart-b6e55a0b-439b-4cc8-bebd-9d58853a6efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140294842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2140294842
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1749066646
Short name T358
Test name
Test status
Simulation time 334210919075 ps
CPU time 288.14 seconds
Started Aug 09 05:37:22 PM PDT 24
Finished Aug 09 05:42:11 PM PDT 24
Peak memory 201404 kb
Host smart-a20469e2-6a07-408a-a703-5d3fd7c458cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749066646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1749066646
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1181389845
Short name T743
Test name
Test status
Simulation time 163533024379 ps
CPU time 92.47 seconds
Started Aug 09 05:37:22 PM PDT 24
Finished Aug 09 05:38:54 PM PDT 24
Peak memory 201496 kb
Host smart-afbd9631-680a-4320-9abf-bd36431e67fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181389845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1181389845
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.741729089
Short name T382
Test name
Test status
Simulation time 207221853517 ps
CPU time 115.32 seconds
Started Aug 09 05:37:22 PM PDT 24
Finished Aug 09 05:39:17 PM PDT 24
Peak memory 201368 kb
Host smart-02df54ee-856b-4cc9-84cf-2ae4f6491e91
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741729089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.741729089
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2533556958
Short name T176
Test name
Test status
Simulation time 119651482527 ps
CPU time 404.53 seconds
Started Aug 09 05:37:29 PM PDT 24
Finished Aug 09 05:44:13 PM PDT 24
Peak memory 201776 kb
Host smart-0283d54f-dc19-405c-8978-67bce9ca1dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533556958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2533556958
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2406818868
Short name T386
Test name
Test status
Simulation time 30552536379 ps
CPU time 31.3 seconds
Started Aug 09 05:37:28 PM PDT 24
Finished Aug 09 05:37:59 PM PDT 24
Peak memory 201268 kb
Host smart-7840230d-f8d3-4b13-aced-7ec16133ac9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406818868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2406818868
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1210847435
Short name T463
Test name
Test status
Simulation time 4406386839 ps
CPU time 11.03 seconds
Started Aug 09 05:37:31 PM PDT 24
Finished Aug 09 05:37:42 PM PDT 24
Peak memory 201208 kb
Host smart-8a8e5375-bafd-4e3f-90c6-a1f99b410854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210847435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1210847435
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2757425139
Short name T703
Test name
Test status
Simulation time 5845570914 ps
CPU time 13.5 seconds
Started Aug 09 05:37:23 PM PDT 24
Finished Aug 09 05:37:37 PM PDT 24
Peak memory 201328 kb
Host smart-ddfe2d99-85d1-459a-b840-9cea057e3a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757425139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2757425139
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1962054060
Short name T588
Test name
Test status
Simulation time 163088832666 ps
CPU time 358.52 seconds
Started Aug 09 05:37:35 PM PDT 24
Finished Aug 09 05:43:34 PM PDT 24
Peak memory 201488 kb
Host smart-996e36ef-49f4-4593-a695-eed980b62805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962054060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1962054060
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.4072077395
Short name T50
Test name
Test status
Simulation time 80005626835 ps
CPU time 172.69 seconds
Started Aug 09 05:37:36 PM PDT 24
Finished Aug 09 05:40:29 PM PDT 24
Peak memory 209964 kb
Host smart-32cd8dbc-a87a-46af-9df7-445b3b0c8bb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072077395 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.4072077395
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3387237734
Short name T521
Test name
Test status
Simulation time 375016600 ps
CPU time 1.41 seconds
Started Aug 09 05:37:40 PM PDT 24
Finished Aug 09 05:37:41 PM PDT 24
Peak memory 201184 kb
Host smart-c43ac9c8-f31d-4731-a9d2-9f457f143466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387237734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3387237734
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.513893386
Short name T681
Test name
Test status
Simulation time 360072682419 ps
CPU time 72.84 seconds
Started Aug 09 05:37:35 PM PDT 24
Finished Aug 09 05:38:48 PM PDT 24
Peak memory 201380 kb
Host smart-7a9450b2-591c-4e1e-8daf-886e4a708ba3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513893386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.513893386
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2252629364
Short name T750
Test name
Test status
Simulation time 170371439419 ps
CPU time 393.79 seconds
Started Aug 09 05:37:36 PM PDT 24
Finished Aug 09 05:44:10 PM PDT 24
Peak memory 201316 kb
Host smart-f49837bc-c7c9-4290-a16c-2d12dcb56dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252629364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2252629364
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2205459531
Short name T592
Test name
Test status
Simulation time 496055569307 ps
CPU time 1132.02 seconds
Started Aug 09 05:37:35 PM PDT 24
Finished Aug 09 05:56:27 PM PDT 24
Peak memory 201400 kb
Host smart-e23fb60e-86ec-4356-81f9-07769c6347bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205459531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2205459531
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3955626194
Short name T423
Test name
Test status
Simulation time 170028999257 ps
CPU time 80.49 seconds
Started Aug 09 05:37:35 PM PDT 24
Finished Aug 09 05:38:56 PM PDT 24
Peak memory 201488 kb
Host smart-8c154e56-f194-4214-8d8e-1d2226491b34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955626194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3955626194
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.264479346
Short name T131
Test name
Test status
Simulation time 327740842825 ps
CPU time 58.48 seconds
Started Aug 09 05:37:35 PM PDT 24
Finished Aug 09 05:38:33 PM PDT 24
Peak memory 201460 kb
Host smart-c755ff75-9baa-48a7-a96a-6aced9384931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264479346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.264479346
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.452694785
Short name T701
Test name
Test status
Simulation time 162803649904 ps
CPU time 318.71 seconds
Started Aug 09 05:37:33 PM PDT 24
Finished Aug 09 05:42:51 PM PDT 24
Peak memory 201388 kb
Host smart-be4d2096-2c35-4b87-b3c9-34137576c46c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=452694785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.452694785
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.681528682
Short name T13
Test name
Test status
Simulation time 602836725282 ps
CPU time 112.45 seconds
Started Aug 09 05:37:37 PM PDT 24
Finished Aug 09 05:39:29 PM PDT 24
Peak memory 201424 kb
Host smart-28a4579b-27f4-4ea1-967b-b2aedb1d0095
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681528682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.681528682
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2942713339
Short name T596
Test name
Test status
Simulation time 82556392499 ps
CPU time 303.25 seconds
Started Aug 09 05:37:44 PM PDT 24
Finished Aug 09 05:42:48 PM PDT 24
Peak memory 201808 kb
Host smart-383ba0b2-a594-4b71-af0f-bbcc0d65a301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942713339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2942713339
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3614469918
Short name T548
Test name
Test status
Simulation time 37326121057 ps
CPU time 42.37 seconds
Started Aug 09 05:37:40 PM PDT 24
Finished Aug 09 05:38:22 PM PDT 24
Peak memory 201296 kb
Host smart-dfbf3dbd-dc48-434f-aa7f-d33af85147ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614469918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3614469918
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1691715760
Short name T430
Test name
Test status
Simulation time 5038202759 ps
CPU time 5.27 seconds
Started Aug 09 05:37:44 PM PDT 24
Finished Aug 09 05:37:49 PM PDT 24
Peak memory 201340 kb
Host smart-fa3a56bd-92aa-4107-af65-ff24a19cde0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691715760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1691715760
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3025181127
Short name T126
Test name
Test status
Simulation time 5882504890 ps
CPU time 14.89 seconds
Started Aug 09 05:37:37 PM PDT 24
Finished Aug 09 05:37:52 PM PDT 24
Peak memory 201276 kb
Host smart-fb096479-0f12-40af-bddb-1df89934fd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025181127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3025181127
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2178242976
Short name T475
Test name
Test status
Simulation time 50430047363 ps
CPU time 122.5 seconds
Started Aug 09 05:37:43 PM PDT 24
Finished Aug 09 05:39:46 PM PDT 24
Peak memory 201356 kb
Host smart-642dd8e2-76fa-4826-8190-54535ff6d12e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178242976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2178242976
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.259181667
Short name T695
Test name
Test status
Simulation time 38925593089 ps
CPU time 113.58 seconds
Started Aug 09 05:37:38 PM PDT 24
Finished Aug 09 05:39:32 PM PDT 24
Peak memory 210240 kb
Host smart-50155317-c6c5-4b2c-9f25-697ecb5a0d27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259181667 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.259181667
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3121752384
Short name T398
Test name
Test status
Simulation time 411584901 ps
CPU time 0.77 seconds
Started Aug 09 05:37:52 PM PDT 24
Finished Aug 09 05:37:53 PM PDT 24
Peak memory 201248 kb
Host smart-be9d5b88-01e8-4caf-9be2-f84e40a3aff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121752384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3121752384
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.518145767
Short name T268
Test name
Test status
Simulation time 166364586457 ps
CPU time 195.33 seconds
Started Aug 09 05:37:52 PM PDT 24
Finished Aug 09 05:41:07 PM PDT 24
Peak memory 201388 kb
Host smart-08b78d1e-19a6-4410-87f3-d75d51d13f14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518145767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.518145767
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1914900980
Short name T278
Test name
Test status
Simulation time 494074491440 ps
CPU time 1120.54 seconds
Started Aug 09 05:37:54 PM PDT 24
Finished Aug 09 05:56:34 PM PDT 24
Peak memory 201328 kb
Host smart-ca8cb2e6-468b-409b-9fd6-baa40cebe053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914900980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1914900980
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2004189709
Short name T11
Test name
Test status
Simulation time 487375741704 ps
CPU time 543.52 seconds
Started Aug 09 05:37:49 PM PDT 24
Finished Aug 09 05:46:53 PM PDT 24
Peak memory 201388 kb
Host smart-22ece258-2773-478a-82fd-88d65ba1d6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004189709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2004189709
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.559230942
Short name T392
Test name
Test status
Simulation time 337641488520 ps
CPU time 388.74 seconds
Started Aug 09 05:37:49 PM PDT 24
Finished Aug 09 05:44:18 PM PDT 24
Peak memory 201312 kb
Host smart-ed18c4b5-6ae2-4fad-923d-ed89633d817f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=559230942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.559230942
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3290475829
Short name T215
Test name
Test status
Simulation time 488065793368 ps
CPU time 706.18 seconds
Started Aug 09 05:37:48 PM PDT 24
Finished Aug 09 05:49:35 PM PDT 24
Peak memory 201416 kb
Host smart-098c0ffc-b2fb-4c4a-b541-cc4e3f6d1eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290475829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3290475829
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3615685636
Short name T359
Test name
Test status
Simulation time 160006665807 ps
CPU time 343.97 seconds
Started Aug 09 05:37:48 PM PDT 24
Finished Aug 09 05:43:32 PM PDT 24
Peak memory 201480 kb
Host smart-7c64f6ff-9e77-4cb2-9697-5dd6e822c345
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615685636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3615685636
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.305469981
Short name T136
Test name
Test status
Simulation time 535940519720 ps
CPU time 172.18 seconds
Started Aug 09 05:37:49 PM PDT 24
Finished Aug 09 05:40:41 PM PDT 24
Peak memory 201472 kb
Host smart-a791e01d-6751-49d5-9b80-79301d091fb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305469981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.305469981
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2477141940
Short name T465
Test name
Test status
Simulation time 408425043759 ps
CPU time 910.89 seconds
Started Aug 09 05:37:49 PM PDT 24
Finished Aug 09 05:53:01 PM PDT 24
Peak memory 201324 kb
Host smart-a31269cd-a5be-4df6-9d83-1ea5d39b171c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477141940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2477141940
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.837245634
Short name T722
Test name
Test status
Simulation time 107615344266 ps
CPU time 329.73 seconds
Started Aug 09 05:37:57 PM PDT 24
Finished Aug 09 05:43:27 PM PDT 24
Peak memory 201820 kb
Host smart-a57f9ea9-f82b-47cb-a5d8-493f364dd8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837245634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.837245634
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1495128227
Short name T56
Test name
Test status
Simulation time 35148639341 ps
CPU time 59.02 seconds
Started Aug 09 05:37:54 PM PDT 24
Finished Aug 09 05:38:53 PM PDT 24
Peak memory 201356 kb
Host smart-e9e4d45d-0354-40d5-b30f-a45396402c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495128227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1495128227
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4117816400
Short name T355
Test name
Test status
Simulation time 4645572662 ps
CPU time 3.15 seconds
Started Aug 09 05:37:54 PM PDT 24
Finished Aug 09 05:37:57 PM PDT 24
Peak memory 201292 kb
Host smart-3b1d9f2a-b7ce-4a97-bedf-d96b8c5bfbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117816400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4117816400
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1885935574
Short name T789
Test name
Test status
Simulation time 5937263234 ps
CPU time 12.48 seconds
Started Aug 09 05:37:44 PM PDT 24
Finished Aug 09 05:37:57 PM PDT 24
Peak memory 201348 kb
Host smart-94c2a5a6-84fc-43ee-aaeb-edbaaa237929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885935574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1885935574
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2064735495
Short name T725
Test name
Test status
Simulation time 171197770131 ps
CPU time 97.35 seconds
Started Aug 09 05:37:53 PM PDT 24
Finished Aug 09 05:39:31 PM PDT 24
Peak memory 201436 kb
Host smart-d31aa85c-7d94-42f5-8e97-eaf2f684279e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064735495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2064735495
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.28529500
Short name T175
Test name
Test status
Simulation time 59439391749 ps
CPU time 179.84 seconds
Started Aug 09 05:37:53 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 217920 kb
Host smart-bb00a03c-7ac5-44b7-ae69-002e50f0899f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28529500 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.28529500
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3119504779
Short name T366
Test name
Test status
Simulation time 467668851 ps
CPU time 0.88 seconds
Started Aug 09 05:37:59 PM PDT 24
Finished Aug 09 05:38:00 PM PDT 24
Peak memory 201104 kb
Host smart-17f2ecb7-20c0-4c32-852c-a5787ae41172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119504779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3119504779
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3472973557
Short name T158
Test name
Test status
Simulation time 339802179329 ps
CPU time 74.87 seconds
Started Aug 09 05:37:54 PM PDT 24
Finished Aug 09 05:39:09 PM PDT 24
Peak memory 201368 kb
Host smart-e2e38ebc-fb49-46f0-a541-a753e3cea5ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472973557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3472973557
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.399919501
Short name T211
Test name
Test status
Simulation time 331966806078 ps
CPU time 775.31 seconds
Started Aug 09 05:37:54 PM PDT 24
Finished Aug 09 05:50:49 PM PDT 24
Peak memory 201384 kb
Host smart-d80b7336-7faa-4aeb-8d75-ac39ef72c56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399919501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.399919501
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3721658055
Short name T535
Test name
Test status
Simulation time 167151202558 ps
CPU time 86.45 seconds
Started Aug 09 05:37:53 PM PDT 24
Finished Aug 09 05:39:20 PM PDT 24
Peak memory 201492 kb
Host smart-ea66b270-4c6d-4541-82f9-6d8eb904b9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721658055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3721658055
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1875992066
Short name T52
Test name
Test status
Simulation time 496285588201 ps
CPU time 1043.44 seconds
Started Aug 09 05:37:53 PM PDT 24
Finished Aug 09 05:55:17 PM PDT 24
Peak memory 201400 kb
Host smart-fe47bbcc-b929-4509-bab8-a61ee9de2fe8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875992066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1875992066
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1166293234
Short name T83
Test name
Test status
Simulation time 330048395289 ps
CPU time 742.25 seconds
Started Aug 09 05:37:53 PM PDT 24
Finished Aug 09 05:50:15 PM PDT 24
Peak memory 201520 kb
Host smart-6a267695-01d1-4157-a688-ff4d0eb78af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166293234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1166293234
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2521575035
Short name T478
Test name
Test status
Simulation time 330685486542 ps
CPU time 726.85 seconds
Started Aug 09 05:37:56 PM PDT 24
Finished Aug 09 05:50:03 PM PDT 24
Peak memory 201424 kb
Host smart-f361aaae-0a63-47f9-8a82-db63ad2ae38b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521575035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2521575035
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1115817791
Short name T51
Test name
Test status
Simulation time 176538849103 ps
CPU time 420.14 seconds
Started Aug 09 05:37:53 PM PDT 24
Finished Aug 09 05:44:54 PM PDT 24
Peak memory 201452 kb
Host smart-f027e571-17c2-4818-8f01-8ee8bc70d94e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115817791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1115817791
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2664635585
Short name T657
Test name
Test status
Simulation time 601925610765 ps
CPU time 1249.3 seconds
Started Aug 09 05:37:56 PM PDT 24
Finished Aug 09 05:58:45 PM PDT 24
Peak memory 201332 kb
Host smart-1fe03a94-ccf9-4c74-ba74-e42f23b6b18c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664635585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2664635585
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3336706783
Short name T91
Test name
Test status
Simulation time 113495234932 ps
CPU time 424.28 seconds
Started Aug 09 05:37:54 PM PDT 24
Finished Aug 09 05:44:58 PM PDT 24
Peak memory 201848 kb
Host smart-92db1315-1a06-4dfc-b2d9-79a4e6ba52d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336706783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3336706783
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4264650003
Short name T537
Test name
Test status
Simulation time 45031183386 ps
CPU time 9.93 seconds
Started Aug 09 05:37:53 PM PDT 24
Finished Aug 09 05:38:04 PM PDT 24
Peak memory 201376 kb
Host smart-9dd6f3f9-eb4f-49b9-8e5b-7d05e4a81429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264650003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4264650003
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2113234012
Short name T747
Test name
Test status
Simulation time 3788821866 ps
CPU time 2.92 seconds
Started Aug 09 05:37:54 PM PDT 24
Finished Aug 09 05:37:57 PM PDT 24
Peak memory 201260 kb
Host smart-15039d6f-f199-4ebb-822e-5d07120c8872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113234012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2113234012
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3047089393
Short name T614
Test name
Test status
Simulation time 6091551151 ps
CPU time 7.36 seconds
Started Aug 09 05:37:54 PM PDT 24
Finished Aug 09 05:38:02 PM PDT 24
Peak memory 201276 kb
Host smart-26e5fb74-18ef-4ce4-8720-752a3a4ad82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047089393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3047089393
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1893774773
Short name T714
Test name
Test status
Simulation time 190942154748 ps
CPU time 418.84 seconds
Started Aug 09 05:37:59 PM PDT 24
Finished Aug 09 05:44:58 PM PDT 24
Peak memory 201380 kb
Host smart-e8a7b8e7-8ebe-46b1-acd2-3523ccf9dc91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893774773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1893774773
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2728767246
Short name T15
Test name
Test status
Simulation time 95615408967 ps
CPU time 103 seconds
Started Aug 09 05:38:01 PM PDT 24
Finished Aug 09 05:39:45 PM PDT 24
Peak memory 209724 kb
Host smart-1be17363-dcd5-4884-a9ac-a473b45dff2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728767246 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2728767246
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2483818730
Short name T445
Test name
Test status
Simulation time 462849803 ps
CPU time 0.83 seconds
Started Aug 09 05:38:13 PM PDT 24
Finished Aug 09 05:38:13 PM PDT 24
Peak memory 201120 kb
Host smart-1d49fee8-db9a-41c8-8a85-6e4458c9f33d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483818730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2483818730
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3221806515
Short name T146
Test name
Test status
Simulation time 395221982329 ps
CPU time 176.42 seconds
Started Aug 09 05:38:06 PM PDT 24
Finished Aug 09 05:41:02 PM PDT 24
Peak memory 201420 kb
Host smart-fc0334db-cf66-4261-8deb-219245583a7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221806515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3221806515
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4256259365
Short name T641
Test name
Test status
Simulation time 482148839627 ps
CPU time 114.34 seconds
Started Aug 09 05:38:01 PM PDT 24
Finished Aug 09 05:39:56 PM PDT 24
Peak memory 201372 kb
Host smart-8af9fcc7-32ca-4de6-a5b5-22db0d0e660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256259365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4256259365
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3813329119
Short name T563
Test name
Test status
Simulation time 334495448758 ps
CPU time 179.51 seconds
Started Aug 09 05:38:00 PM PDT 24
Finished Aug 09 05:40:59 PM PDT 24
Peak memory 201388 kb
Host smart-015d0178-d71c-4655-bc96-c51c4c95b247
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813329119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3813329119
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3521670248
Short name T726
Test name
Test status
Simulation time 163403472345 ps
CPU time 194.56 seconds
Started Aug 09 05:37:59 PM PDT 24
Finished Aug 09 05:41:14 PM PDT 24
Peak memory 201444 kb
Host smart-3a5af273-d60d-480d-8936-34e76bc9086d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521670248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3521670248
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2132737534
Short name T508
Test name
Test status
Simulation time 165223715606 ps
CPU time 347.84 seconds
Started Aug 09 05:37:59 PM PDT 24
Finished Aug 09 05:43:47 PM PDT 24
Peak memory 201408 kb
Host smart-d27b4cb9-4727-40f0-85db-e9019141921e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132737534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2132737534
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2376963126
Short name T261
Test name
Test status
Simulation time 282966895024 ps
CPU time 308.38 seconds
Started Aug 09 05:38:06 PM PDT 24
Finished Aug 09 05:43:14 PM PDT 24
Peak memory 201444 kb
Host smart-7f669df7-3f94-4ad2-b059-147995a55354
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376963126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2376963126
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3402997920
Short name T2
Test name
Test status
Simulation time 617007435682 ps
CPU time 350.66 seconds
Started Aug 09 05:38:05 PM PDT 24
Finished Aug 09 05:43:56 PM PDT 24
Peak memory 201448 kb
Host smart-4c9518d2-8ac1-48a2-9d45-0b3cc38c04ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402997920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3402997920
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3187538469
Short name T632
Test name
Test status
Simulation time 64797691315 ps
CPU time 249.03 seconds
Started Aug 09 05:38:12 PM PDT 24
Finished Aug 09 05:42:21 PM PDT 24
Peak memory 201736 kb
Host smart-375ae48a-5201-42c3-9dcd-f8d8e3548706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187538469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3187538469
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1974105674
Short name T765
Test name
Test status
Simulation time 26678558131 ps
CPU time 6.54 seconds
Started Aug 09 05:38:06 PM PDT 24
Finished Aug 09 05:38:12 PM PDT 24
Peak memory 201336 kb
Host smart-15cfad0f-68ed-41f4-902e-f22fbaf10719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974105674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1974105674
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.4053837443
Short name T380
Test name
Test status
Simulation time 3189080931 ps
CPU time 2.04 seconds
Started Aug 09 05:38:06 PM PDT 24
Finished Aug 09 05:38:08 PM PDT 24
Peak memory 201224 kb
Host smart-ab50c52e-0374-4b3c-98b1-2c671c422c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053837443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.4053837443
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.13456713
Short name T350
Test name
Test status
Simulation time 6149244860 ps
CPU time 3.17 seconds
Started Aug 09 05:38:00 PM PDT 24
Finished Aug 09 05:38:03 PM PDT 24
Peak memory 201292 kb
Host smart-f606d35e-9bbd-4157-aa54-17eaf4c4cc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13456713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.13456713
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.4056704838
Short name T387
Test name
Test status
Simulation time 520099311 ps
CPU time 1.68 seconds
Started Aug 09 05:38:22 PM PDT 24
Finished Aug 09 05:38:24 PM PDT 24
Peak memory 201204 kb
Host smart-4d7cd868-5821-4ce0-995d-295376921f20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056704838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.4056704838
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3941278284
Short name T152
Test name
Test status
Simulation time 333428436422 ps
CPU time 174.76 seconds
Started Aug 09 05:38:19 PM PDT 24
Finished Aug 09 05:41:14 PM PDT 24
Peak memory 201320 kb
Host smart-9fb66052-b533-40a7-bf56-8de85cb62a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941278284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3941278284
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3911017943
Short name T522
Test name
Test status
Simulation time 161575128869 ps
CPU time 204.48 seconds
Started Aug 09 05:38:14 PM PDT 24
Finished Aug 09 05:41:39 PM PDT 24
Peak memory 201412 kb
Host smart-05ebac6f-3ccc-45f6-ae5a-7fcb4abaeafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911017943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3911017943
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3107299867
Short name T105
Test name
Test status
Simulation time 327250010056 ps
CPU time 735.52 seconds
Started Aug 09 05:38:12 PM PDT 24
Finished Aug 09 05:50:27 PM PDT 24
Peak memory 201408 kb
Host smart-3235f257-a207-4dda-8a74-fcba12a0c922
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107299867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3107299867
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1518358402
Short name T721
Test name
Test status
Simulation time 500204842996 ps
CPU time 328.75 seconds
Started Aug 09 05:38:12 PM PDT 24
Finished Aug 09 05:43:40 PM PDT 24
Peak memory 201444 kb
Host smart-70bb4663-ac92-43c1-8673-52bd4e0b25da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518358402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1518358402
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.217212754
Short name T746
Test name
Test status
Simulation time 326350985142 ps
CPU time 803.27 seconds
Started Aug 09 05:38:11 PM PDT 24
Finished Aug 09 05:51:34 PM PDT 24
Peak memory 201312 kb
Host smart-0b19cc1d-807c-403c-9ed0-a9373828ee0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=217212754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.217212754
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.4142966976
Short name T232
Test name
Test status
Simulation time 352142446974 ps
CPU time 406.45 seconds
Started Aug 09 05:38:12 PM PDT 24
Finished Aug 09 05:44:59 PM PDT 24
Peak memory 201384 kb
Host smart-353651ea-21fe-46d9-87af-48a86021a99b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142966976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.4142966976
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3802133987
Short name T408
Test name
Test status
Simulation time 602736544007 ps
CPU time 415.24 seconds
Started Aug 09 05:38:16 PM PDT 24
Finished Aug 09 05:45:12 PM PDT 24
Peak memory 201480 kb
Host smart-37ef4e23-30b6-403d-9fd2-ca5ea3eba388
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802133987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3802133987
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3965327368
Short name T616
Test name
Test status
Simulation time 79256436064 ps
CPU time 414.1 seconds
Started Aug 09 05:38:16 PM PDT 24
Finished Aug 09 05:45:10 PM PDT 24
Peak memory 201748 kb
Host smart-9034e81f-b2da-4dff-a643-eef999d14c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965327368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3965327368
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.66378424
Short name T672
Test name
Test status
Simulation time 31456391433 ps
CPU time 70.88 seconds
Started Aug 09 05:38:17 PM PDT 24
Finished Aug 09 05:39:28 PM PDT 24
Peak memory 201292 kb
Host smart-9d595dd2-90da-444c-b257-2c2825f69356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66378424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.66378424
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.67758379
Short name T349
Test name
Test status
Simulation time 3091580891 ps
CPU time 3.8 seconds
Started Aug 09 05:38:18 PM PDT 24
Finished Aug 09 05:38:22 PM PDT 24
Peak memory 201236 kb
Host smart-0f789a48-37de-44ef-84e0-542902816ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67758379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.67758379
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3239892548
Short name T429
Test name
Test status
Simulation time 5892285588 ps
CPU time 3.63 seconds
Started Aug 09 05:38:15 PM PDT 24
Finished Aug 09 05:38:19 PM PDT 24
Peak memory 201272 kb
Host smart-b886828a-267c-405c-93a1-70649b9813c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239892548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3239892548
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1798202455
Short name T308
Test name
Test status
Simulation time 253894263462 ps
CPU time 72.92 seconds
Started Aug 09 05:38:23 PM PDT 24
Finished Aug 09 05:39:36 PM PDT 24
Peak memory 210392 kb
Host smart-952276f5-d945-4c54-957a-1596816fd6da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798202455 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1798202455
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3218784491
Short name T624
Test name
Test status
Simulation time 466819095 ps
CPU time 0.81 seconds
Started Aug 09 05:38:41 PM PDT 24
Finished Aug 09 05:38:42 PM PDT 24
Peak memory 201156 kb
Host smart-836cd371-6a7c-4510-83f3-eb72db0582bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218784491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3218784491
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2818421383
Short name T295
Test name
Test status
Simulation time 528892397888 ps
CPU time 764.45 seconds
Started Aug 09 05:38:27 PM PDT 24
Finished Aug 09 05:51:11 PM PDT 24
Peak memory 201432 kb
Host smart-f0108d21-7521-4b1e-9017-b27bf6b2874a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818421383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2818421383
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3881392983
Short name T217
Test name
Test status
Simulation time 323538058603 ps
CPU time 207.04 seconds
Started Aug 09 05:38:24 PM PDT 24
Finished Aug 09 05:41:51 PM PDT 24
Peak memory 201292 kb
Host smart-2dd5c82f-b0b6-42d1-8460-812b6e04c86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881392983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3881392983
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1001291320
Short name T336
Test name
Test status
Simulation time 328916009528 ps
CPU time 808.08 seconds
Started Aug 09 05:38:25 PM PDT 24
Finished Aug 09 05:51:53 PM PDT 24
Peak memory 201444 kb
Host smart-e647e492-b3d5-4a07-ada8-0f033a4e67fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001291320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1001291320
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3833447609
Short name T774
Test name
Test status
Simulation time 486215872034 ps
CPU time 1141.01 seconds
Started Aug 09 05:38:23 PM PDT 24
Finished Aug 09 05:57:24 PM PDT 24
Peak memory 201432 kb
Host smart-6e1ce258-5b8c-4474-9c7b-d4310191208b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833447609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3833447609
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1834764278
Short name T166
Test name
Test status
Simulation time 167916922865 ps
CPU time 353.49 seconds
Started Aug 09 05:38:24 PM PDT 24
Finished Aug 09 05:44:18 PM PDT 24
Peak memory 201348 kb
Host smart-7152457b-7378-43b6-a0fb-b9fc838b82ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834764278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1834764278
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1797560232
Short name T224
Test name
Test status
Simulation time 380162069125 ps
CPU time 886.71 seconds
Started Aug 09 05:38:23 PM PDT 24
Finished Aug 09 05:53:10 PM PDT 24
Peak memory 201392 kb
Host smart-4be1638e-ed49-48d8-ad4c-b3cdcdc4fc5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797560232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1797560232
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1276066290
Short name T675
Test name
Test status
Simulation time 401704070128 ps
CPU time 222.88 seconds
Started Aug 09 05:38:29 PM PDT 24
Finished Aug 09 05:42:12 PM PDT 24
Peak memory 201348 kb
Host smart-6181435d-d8b5-4682-8718-b74f1f1d6b30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276066290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1276066290
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1460112963
Short name T324
Test name
Test status
Simulation time 100059977219 ps
CPU time 510.91 seconds
Started Aug 09 05:38:27 PM PDT 24
Finished Aug 09 05:46:58 PM PDT 24
Peak memory 201768 kb
Host smart-76662b14-22ef-46f5-83fe-6e86afdb6eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460112963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1460112963
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1812308745
Short name T94
Test name
Test status
Simulation time 31310503420 ps
CPU time 33.02 seconds
Started Aug 09 05:38:27 PM PDT 24
Finished Aug 09 05:39:00 PM PDT 24
Peak memory 201268 kb
Host smart-5cd4be00-7b1c-42d1-8ea7-fda146aede3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812308745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1812308745
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.714751999
Short name T427
Test name
Test status
Simulation time 3051416147 ps
CPU time 2.48 seconds
Started Aug 09 05:38:27 PM PDT 24
Finished Aug 09 05:38:30 PM PDT 24
Peak memory 201244 kb
Host smart-8ec761ac-11fb-4522-a25d-dc14565d0537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714751999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.714751999
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.102485229
Short name T403
Test name
Test status
Simulation time 5693189950 ps
CPU time 6.72 seconds
Started Aug 09 05:38:23 PM PDT 24
Finished Aug 09 05:38:30 PM PDT 24
Peak memory 201316 kb
Host smart-0f178d30-c5d4-4429-8aa2-c6be742e94b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102485229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.102485229
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.617385053
Short name T25
Test name
Test status
Simulation time 211156500891 ps
CPU time 524.45 seconds
Started Aug 09 05:38:39 PM PDT 24
Finished Aug 09 05:47:23 PM PDT 24
Peak memory 201384 kb
Host smart-1898fcc4-7d3d-4c68-a8f9-40c73159e1c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617385053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
617385053
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1203235928
Short name T296
Test name
Test status
Simulation time 23149864135 ps
CPU time 52.5 seconds
Started Aug 09 05:38:28 PM PDT 24
Finished Aug 09 05:39:20 PM PDT 24
Peak memory 209712 kb
Host smart-2ee0df5b-6311-40f3-80fa-cf544b51b488
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203235928 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1203235928
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2610216788
Short name T514
Test name
Test status
Simulation time 374230191 ps
CPU time 0.79 seconds
Started Aug 09 05:35:01 PM PDT 24
Finished Aug 09 05:35:02 PM PDT 24
Peak memory 201136 kb
Host smart-eb6ece95-8b00-4321-8471-1701851d3c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610216788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2610216788
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3744049263
Short name T631
Test name
Test status
Simulation time 199503088253 ps
CPU time 93.94 seconds
Started Aug 09 05:35:03 PM PDT 24
Finished Aug 09 05:36:37 PM PDT 24
Peak memory 201316 kb
Host smart-8c21830c-18a4-4dbe-9a4a-7471bc727779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744049263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3744049263
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2045848004
Short name T306
Test name
Test status
Simulation time 323893015832 ps
CPU time 203.37 seconds
Started Aug 09 05:34:55 PM PDT 24
Finished Aug 09 05:38:19 PM PDT 24
Peak memory 201428 kb
Host smart-7267bd29-5824-459b-92bb-0effa05aff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045848004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2045848004
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2669723186
Short name T512
Test name
Test status
Simulation time 328972860546 ps
CPU time 194.18 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:38:26 PM PDT 24
Peak memory 201644 kb
Host smart-9c77482a-64e9-47fe-abe0-597f5e8931ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669723186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2669723186
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1281224631
Short name T201
Test name
Test status
Simulation time 330986256771 ps
CPU time 702.16 seconds
Started Aug 09 05:35:19 PM PDT 24
Finished Aug 09 05:47:02 PM PDT 24
Peak memory 201444 kb
Host smart-a4e1eab9-8649-477f-a129-df880597a2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281224631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1281224631
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.209158312
Short name T677
Test name
Test status
Simulation time 492385485283 ps
CPU time 203.55 seconds
Started Aug 09 05:34:51 PM PDT 24
Finished Aug 09 05:38:14 PM PDT 24
Peak memory 201352 kb
Host smart-3c077881-cd0c-4048-acbf-1cdebe5b806c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=209158312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.209158312
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1244301213
Short name T200
Test name
Test status
Simulation time 365491558225 ps
CPU time 834.68 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:48:59 PM PDT 24
Peak memory 201404 kb
Host smart-58afdf5f-d081-4c37-9a87-ae96dc33714c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244301213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1244301213
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1352874360
Short name T782
Test name
Test status
Simulation time 397850101050 ps
CPU time 736.68 seconds
Started Aug 09 05:35:10 PM PDT 24
Finished Aug 09 05:47:26 PM PDT 24
Peak memory 201400 kb
Host smart-2cecc7ed-480b-4dde-8c10-f0bfe2a42e5b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352874360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1352874360
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2269312911
Short name T499
Test name
Test status
Simulation time 102507017099 ps
CPU time 317.76 seconds
Started Aug 09 05:34:55 PM PDT 24
Finished Aug 09 05:40:13 PM PDT 24
Peak memory 201724 kb
Host smart-453f0e34-0d1a-45f2-af00-5d7000deff93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269312911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2269312911
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1387250754
Short name T383
Test name
Test status
Simulation time 28867130532 ps
CPU time 43.12 seconds
Started Aug 09 05:35:18 PM PDT 24
Finished Aug 09 05:36:02 PM PDT 24
Peak memory 201324 kb
Host smart-d8f6c94c-01f9-4464-9206-7c2d2ccd9b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387250754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1387250754
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3748107186
Short name T568
Test name
Test status
Simulation time 3008544710 ps
CPU time 7.22 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:35:19 PM PDT 24
Peak memory 201348 kb
Host smart-c79ad97f-766a-4ed4-8de2-ef219dfcfaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748107186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3748107186
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.83498993
Short name T431
Test name
Test status
Simulation time 6169899676 ps
CPU time 11.3 seconds
Started Aug 09 05:35:13 PM PDT 24
Finished Aug 09 05:35:25 PM PDT 24
Peak memory 201296 kb
Host smart-5d535a70-d6bf-4f03-982b-8c807bbf7b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83498993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.83498993
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3236206451
Short name T510
Test name
Test status
Simulation time 326293552336 ps
CPU time 967.88 seconds
Started Aug 09 05:35:03 PM PDT 24
Finished Aug 09 05:51:11 PM PDT 24
Peak memory 218072 kb
Host smart-0ed4adbe-536f-4208-a5c5-db739a57b893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236206451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3236206451
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1504436504
Short name T16
Test name
Test status
Simulation time 73944099845 ps
CPU time 278.66 seconds
Started Aug 09 05:35:06 PM PDT 24
Finished Aug 09 05:39:45 PM PDT 24
Peak memory 210212 kb
Host smart-b8045422-8d64-441f-860e-69cd37526457
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504436504 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1504436504
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2408538331
Short name T372
Test name
Test status
Simulation time 543919232 ps
CPU time 0.92 seconds
Started Aug 09 05:35:02 PM PDT 24
Finished Aug 09 05:35:03 PM PDT 24
Peak memory 201200 kb
Host smart-1fe948b2-bb5d-4000-b45e-4b7ff294c1f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408538331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2408538331
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.460379944
Short name T206
Test name
Test status
Simulation time 219575111672 ps
CPU time 121.33 seconds
Started Aug 09 05:35:25 PM PDT 24
Finished Aug 09 05:37:26 PM PDT 24
Peak memory 201516 kb
Host smart-9ac2b233-ea27-44a8-8b24-6cb2ee4abd55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460379944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.460379944
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3937841759
Short name T381
Test name
Test status
Simulation time 492938269497 ps
CPU time 587.78 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:45:02 PM PDT 24
Peak memory 201356 kb
Host smart-556b314e-4f02-424c-b4ec-c9d38f69f5e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937841759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3937841759
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.902582148
Short name T132
Test name
Test status
Simulation time 490845771456 ps
CPU time 1132.45 seconds
Started Aug 09 05:34:54 PM PDT 24
Finished Aug 09 05:53:47 PM PDT 24
Peak memory 201508 kb
Host smart-8f0342b5-7654-4300-a5e8-ce8795e18953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902582148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.902582148
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.375625496
Short name T784
Test name
Test status
Simulation time 325744328021 ps
CPU time 160.79 seconds
Started Aug 09 05:35:03 PM PDT 24
Finished Aug 09 05:37:44 PM PDT 24
Peak memory 201640 kb
Host smart-246675f0-6a1f-4e2d-aa42-5d9ecac60155
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=375625496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.375625496
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2050372112
Short name T12
Test name
Test status
Simulation time 236642809166 ps
CPU time 129.77 seconds
Started Aug 09 05:35:11 PM PDT 24
Finished Aug 09 05:37:21 PM PDT 24
Peak memory 201312 kb
Host smart-9bcfea42-3896-4024-aa15-ec7d2e73094e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050372112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2050372112
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.146819001
Short name T425
Test name
Test status
Simulation time 584724643256 ps
CPU time 225.53 seconds
Started Aug 09 05:35:19 PM PDT 24
Finished Aug 09 05:39:05 PM PDT 24
Peak memory 201392 kb
Host smart-78ec9d11-84a7-4ca4-a5d4-2fc4fb9d1348
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146819001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.146819001
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2027087829
Short name T754
Test name
Test status
Simulation time 72845282004 ps
CPU time 281.96 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:39:46 PM PDT 24
Peak memory 201696 kb
Host smart-7d32adaf-459a-4660-9c67-f0476face4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027087829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2027087829
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3937610847
Short name T550
Test name
Test status
Simulation time 39509785232 ps
CPU time 23.16 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:35:27 PM PDT 24
Peak memory 201264 kb
Host smart-b003d6e0-4696-46b3-ad83-562f9be5f91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937610847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3937610847
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2761058542
Short name T707
Test name
Test status
Simulation time 4500080838 ps
CPU time 5.98 seconds
Started Aug 09 05:35:11 PM PDT 24
Finished Aug 09 05:35:17 PM PDT 24
Peak memory 201292 kb
Host smart-432a04c3-4de1-40e8-a485-9d1b57af01a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761058542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2761058542
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.243367992
Short name T335
Test name
Test status
Simulation time 6108555868 ps
CPU time 8.05 seconds
Started Aug 09 05:34:55 PM PDT 24
Finished Aug 09 05:35:03 PM PDT 24
Peak memory 201320 kb
Host smart-1f684e08-8dec-4f1a-a460-1137fae3e8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243367992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.243367992
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3363352021
Short name T766
Test name
Test status
Simulation time 478327260764 ps
CPU time 1428.03 seconds
Started Aug 09 05:35:10 PM PDT 24
Finished Aug 09 05:58:59 PM PDT 24
Peak memory 212008 kb
Host smart-be99aa1c-51de-4d67-a97e-e86173d703d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363352021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3363352021
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3277734227
Short name T527
Test name
Test status
Simulation time 305640489631 ps
CPU time 172.15 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:38:04 PM PDT 24
Peak memory 210176 kb
Host smart-e9a0a469-cac4-4c8f-a6b2-013314026fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277734227 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3277734227
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.4003205963
Short name T691
Test name
Test status
Simulation time 459772518 ps
CPU time 0.9 seconds
Started Aug 09 05:35:10 PM PDT 24
Finished Aug 09 05:35:11 PM PDT 24
Peak memory 201236 kb
Host smart-8d95742a-98bf-42bd-9f1d-9d156ebc8d57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003205963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.4003205963
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3640813351
Short name T241
Test name
Test status
Simulation time 365152020612 ps
CPU time 273.73 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:39:46 PM PDT 24
Peak memory 201444 kb
Host smart-44fb7b9b-855d-4300-9b99-b98a63b9a4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640813351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3640813351
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1344189237
Short name T197
Test name
Test status
Simulation time 157856775042 ps
CPU time 138.9 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:37:31 PM PDT 24
Peak memory 201428 kb
Host smart-7a590b62-d055-4138-970a-96ad746221e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344189237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1344189237
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1693592996
Short name T45
Test name
Test status
Simulation time 168230836119 ps
CPU time 191.07 seconds
Started Aug 09 05:35:19 PM PDT 24
Finished Aug 09 05:38:30 PM PDT 24
Peak memory 201404 kb
Host smart-6eade4a3-aab1-49f3-8e29-3ecf182da855
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693592996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1693592996
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3884210186
Short name T591
Test name
Test status
Simulation time 483123516260 ps
CPU time 287.44 seconds
Started Aug 09 05:34:58 PM PDT 24
Finished Aug 09 05:39:45 PM PDT 24
Peak memory 201312 kb
Host smart-e897b1ba-ab85-4d71-a4a1-dd389ee502b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884210186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3884210186
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2966608302
Short name T369
Test name
Test status
Simulation time 162382720584 ps
CPU time 349.39 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:40:53 PM PDT 24
Peak memory 201328 kb
Host smart-32f0e6e8-2862-48b8-af0e-561794d2d39c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966608302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2966608302
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3731612467
Short name T793
Test name
Test status
Simulation time 396290580682 ps
CPU time 901.36 seconds
Started Aug 09 05:34:53 PM PDT 24
Finished Aug 09 05:49:55 PM PDT 24
Peak memory 201404 kb
Host smart-65e1ea5a-5d28-4c38-8691-6af8c0d55a04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731612467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3731612467
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1580734759
Short name T481
Test name
Test status
Simulation time 36712713780 ps
CPU time 79.7 seconds
Started Aug 09 05:34:56 PM PDT 24
Finished Aug 09 05:36:16 PM PDT 24
Peak memory 201304 kb
Host smart-dc6a530e-4ff3-4793-ad4f-71f574447a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580734759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1580734759
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3241593084
Short name T331
Test name
Test status
Simulation time 5298814620 ps
CPU time 5.84 seconds
Started Aug 09 05:35:01 PM PDT 24
Finished Aug 09 05:35:07 PM PDT 24
Peak memory 201340 kb
Host smart-4d2db09d-6c64-4b56-be30-1f80c9b0b723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241593084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3241593084
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3992745711
Short name T618
Test name
Test status
Simulation time 5990272373 ps
CPU time 7.95 seconds
Started Aug 09 05:35:05 PM PDT 24
Finished Aug 09 05:35:13 PM PDT 24
Peak memory 201312 kb
Host smart-8b54f331-e9b3-4c54-947e-8a947d8db57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992745711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3992745711
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1484619934
Short name T270
Test name
Test status
Simulation time 169966169335 ps
CPU time 207.72 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:38:42 PM PDT 24
Peak memory 201388 kb
Host smart-4b16a8c4-82b1-49c9-ba95-43e12b88974d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484619934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1484619934
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3722674788
Short name T524
Test name
Test status
Simulation time 332460368765 ps
CPU time 328.94 seconds
Started Aug 09 05:34:58 PM PDT 24
Finished Aug 09 05:40:27 PM PDT 24
Peak memory 210220 kb
Host smart-6fa6688d-3474-42df-bbb7-3b9f7d1d4365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722674788 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3722674788
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4238434657
Short name T769
Test name
Test status
Simulation time 524145341 ps
CPU time 1.77 seconds
Started Aug 09 05:35:04 PM PDT 24
Finished Aug 09 05:35:06 PM PDT 24
Peak memory 201212 kb
Host smart-920dfeaa-9b12-439e-a345-3f35883f726d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238434657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4238434657
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3902127346
Short name T87
Test name
Test status
Simulation time 353845027702 ps
CPU time 375.32 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:41:28 PM PDT 24
Peak memory 201412 kb
Host smart-6ba2679b-026e-461c-a167-2f9bc26b9fc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902127346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3902127346
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2150595409
Short name T260
Test name
Test status
Simulation time 325304424398 ps
CPU time 788.88 seconds
Started Aug 09 05:35:08 PM PDT 24
Finished Aug 09 05:48:17 PM PDT 24
Peak memory 201388 kb
Host smart-3850db88-d89b-4c65-b7fa-bfbc48c17054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150595409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2150595409
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.652717491
Short name T650
Test name
Test status
Simulation time 323505667350 ps
CPU time 181.7 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:38:16 PM PDT 24
Peak memory 201392 kb
Host smart-d96380e8-30e6-4ba5-8919-a079e9b4ac17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=652717491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.652717491
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3814440993
Short name T266
Test name
Test status
Simulation time 161699120626 ps
CPU time 366.88 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:41:21 PM PDT 24
Peak memory 201392 kb
Host smart-8711d996-e1c5-4c1c-b5c8-7e8447f715ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814440993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3814440993
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2513065677
Short name T608
Test name
Test status
Simulation time 496979350232 ps
CPU time 1216.94 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:55:32 PM PDT 24
Peak memory 201388 kb
Host smart-0bed8f08-d100-4b49-aa0e-cdb7058981f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513065677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2513065677
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3086800152
Short name T343
Test name
Test status
Simulation time 619150913621 ps
CPU time 1319.53 seconds
Started Aug 09 05:34:59 PM PDT 24
Finished Aug 09 05:56:59 PM PDT 24
Peak memory 201436 kb
Host smart-b1157fb0-c45c-4416-af88-a978906b21b6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086800152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3086800152
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.868093534
Short name T617
Test name
Test status
Simulation time 78137234488 ps
CPU time 307.59 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:40:20 PM PDT 24
Peak memory 201820 kb
Host smart-3ec39d51-01e8-4a9c-bf84-977ee14f2531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868093534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.868093534
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2683590664
Short name T682
Test name
Test status
Simulation time 28897017203 ps
CPU time 13.7 seconds
Started Aug 09 05:35:13 PM PDT 24
Finished Aug 09 05:35:27 PM PDT 24
Peak memory 201296 kb
Host smart-63aae0a8-bacb-4ff3-a898-946c6173cc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683590664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2683590664
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2513298078
Short name T786
Test name
Test status
Simulation time 4445654689 ps
CPU time 9.98 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:35:24 PM PDT 24
Peak memory 201352 kb
Host smart-6a3f456e-5fb8-4d81-a39d-57f21bf814d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513298078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2513298078
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2724543422
Short name T660
Test name
Test status
Simulation time 5811326930 ps
CPU time 2.68 seconds
Started Aug 09 05:35:15 PM PDT 24
Finished Aug 09 05:35:18 PM PDT 24
Peak memory 201332 kb
Host smart-df1f9eef-a57a-42b6-a4b7-5f0fb2ff79e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724543422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2724543422
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2373934647
Short name T442
Test name
Test status
Simulation time 6894333722 ps
CPU time 14.6 seconds
Started Aug 09 05:35:22 PM PDT 24
Finished Aug 09 05:35:37 PM PDT 24
Peak memory 201320 kb
Host smart-318a2473-f2bf-4936-bf83-7189f933ff2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373934647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2373934647
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3640916221
Short name T33
Test name
Test status
Simulation time 352370160645 ps
CPU time 171.96 seconds
Started Aug 09 05:35:19 PM PDT 24
Finished Aug 09 05:38:11 PM PDT 24
Peak memory 217452 kb
Host smart-685bc1ce-a11b-4cbd-9d8b-22bad238c6bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640916221 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3640916221
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.804450769
Short name T770
Test name
Test status
Simulation time 463217667 ps
CPU time 0.68 seconds
Started Aug 09 05:34:58 PM PDT 24
Finished Aug 09 05:34:59 PM PDT 24
Peak memory 201256 kb
Host smart-d0544323-e567-43f3-adce-dd75de1fac60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804450769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.804450769
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3690794256
Short name T448
Test name
Test status
Simulation time 343254678770 ps
CPU time 266.18 seconds
Started Aug 09 05:35:18 PM PDT 24
Finished Aug 09 05:39:44 PM PDT 24
Peak memory 201436 kb
Host smart-7f550b0a-3949-41a5-afec-36e57cc05e62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690794256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3690794256
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3350733288
Short name T441
Test name
Test status
Simulation time 505012399554 ps
CPU time 1147.98 seconds
Started Aug 09 05:35:15 PM PDT 24
Finished Aug 09 05:54:23 PM PDT 24
Peak memory 201372 kb
Host smart-6b736d59-b597-40f2-83fb-aad1051f8fc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350733288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3350733288
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.653784222
Short name T457
Test name
Test status
Simulation time 164499530494 ps
CPU time 369.85 seconds
Started Aug 09 05:34:58 PM PDT 24
Finished Aug 09 05:41:08 PM PDT 24
Peak memory 201488 kb
Host smart-a9543268-3cae-470a-8dfc-f205ad529364
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=653784222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.653784222
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1036851218
Short name T636
Test name
Test status
Simulation time 340409949932 ps
CPU time 117.86 seconds
Started Aug 09 05:35:22 PM PDT 24
Finished Aug 09 05:37:20 PM PDT 24
Peak memory 201360 kb
Host smart-77db9828-48dc-4eb7-8894-45bbbdcd6e1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036851218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1036851218
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.4002108048
Short name T609
Test name
Test status
Simulation time 202741156171 ps
CPU time 124.36 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:37:18 PM PDT 24
Peak memory 201480 kb
Host smart-e843959e-b3ba-4c08-b8c6-25c3405cef7b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002108048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.4002108048
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3640762076
Short name T10
Test name
Test status
Simulation time 87205707106 ps
CPU time 330.95 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:40:43 PM PDT 24
Peak memory 201836 kb
Host smart-659946e0-d32a-4fd9-ad23-99a679edeee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640762076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3640762076
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3556783154
Short name T100
Test name
Test status
Simulation time 23082932800 ps
CPU time 11.9 seconds
Started Aug 09 05:35:05 PM PDT 24
Finished Aug 09 05:35:17 PM PDT 24
Peak memory 201268 kb
Host smart-de5f80f4-c6e9-4c73-9442-e78e0c41a604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556783154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3556783154
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3889852056
Short name T165
Test name
Test status
Simulation time 3469132196 ps
CPU time 6.43 seconds
Started Aug 09 05:35:12 PM PDT 24
Finished Aug 09 05:35:18 PM PDT 24
Peak memory 201308 kb
Host smart-4ab0082a-6bdb-4072-a7b1-c0d558faf6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889852056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3889852056
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.593120740
Short name T552
Test name
Test status
Simulation time 6019857110 ps
CPU time 14.61 seconds
Started Aug 09 05:35:14 PM PDT 24
Finished Aug 09 05:35:28 PM PDT 24
Peak memory 201248 kb
Host smart-83f22be1-5c13-478d-a17d-1fd99ff43b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593120740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.593120740
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2198659741
Short name T250
Test name
Test status
Simulation time 492367724491 ps
CPU time 652.83 seconds
Started Aug 09 05:34:59 PM PDT 24
Finished Aug 09 05:45:52 PM PDT 24
Peak memory 210076 kb
Host smart-c8fb811b-741d-4db9-9151-706b93e58dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198659741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2198659741
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3024097863
Short name T253
Test name
Test status
Simulation time 30880301449 ps
CPU time 17.28 seconds
Started Aug 09 05:35:27 PM PDT 24
Finished Aug 09 05:35:44 PM PDT 24
Peak memory 209680 kb
Host smart-91115d9a-5e39-4f7f-adff-8fa039245f57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024097863 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3024097863
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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