Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1192574	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1164187

1

T4

3

T1

1411

T2

57

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2066362	1			T4	1		T1	2489		T2	81
values[0x0]	144846	1			T4	3		T1	146		T2	31
values[0x1]	145553	1			T4	1		T1	167		T2	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	955428	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1401333

1

T4

3

T1

1736

T2

75

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6911	1			T1	9		T6	35		T7	9
valid_sources[0x01]	11978	1			T1	7		T3	10		T6	51
valid_sources[0x02]	8852	1			T1	6		T6	20		T7	13
valid_sources[0x03]	11233	1			T1	4		T3	6		T6	34
valid_sources[0x04]	6711	1			T1	3		T6	31		T7	18
valid_sources[0x05]	8651	1			T3	6		T6	26		T7	17
valid_sources[0x06]	7663	1			T1	1		T3	4		T6	24
valid_sources[0x07]	6640	1			T1	16		T6	33		T7	34
valid_sources[0x08]	7034	1			T1	4		T3	1		T6	25
valid_sources[0x09]	6804	1			T1	4		T3	4		T6	23
valid_sources[0x0a]	8057	1			T1	13		T3	15		T6	51
valid_sources[0x0b]	7212	1			T1	12		T3	8		T6	45
valid_sources[0x0c]	11561	1			T1	13		T6	31		T7	9
valid_sources[0x0d]	7033	1			T1	30		T6	28		T7	4
valid_sources[0x0e]	22292	1			T1	6		T6	35		T7	11
valid_sources[0x0f]	6949	1			T1	12		T3	9		T6	36
valid_sources[0x10]	7911	1			T1	12		T6	40		T7	5
valid_sources[0x11]	6912	1			T1	4		T3	5		T6	27
valid_sources[0x12]	7561	1			T1	8		T3	5		T6	34
valid_sources[0x13]	6750	1			T1	19		T3	5		T6	31
valid_sources[0x14]	6826	1			T1	9		T6	43		T9	5
valid_sources[0x15]	19792	1			T1	2		T6	54		T7	8
valid_sources[0x16]	7575	1			T1	13		T3	2		T6	16
valid_sources[0x17]	6855	1			T1	2		T3	8		T6	17
valid_sources[0x18]	9917	1			T1	7		T3	3		T6	18
valid_sources[0x19]	8455	1			T4	5		T1	4		T6	42
valid_sources[0x1a]	7450	1			T1	10		T3	2		T6	45
valid_sources[0x1b]	6934	1			T1	8		T3	2		T6	40
valid_sources[0x1c]	9248	1			T1	5		T3	2		T6	34
valid_sources[0x1d]	7090	1			T1	7		T3	4		T6	20
valid_sources[0x1e]	7976	1			T1	3		T3	4		T6	35
valid_sources[0x1f]	7040	1			T1	2		T6	27		T7	14
valid_sources[0x20]	7196	1			T1	12		T3	8		T6	35
valid_sources[0x21]	14731	1			T1	4		T3	3		T6	32
valid_sources[0x22]	7796	1			T1	1		T6	29		T7	20
valid_sources[0x23]	6867	1			T1	11		T3	6		T6	27
valid_sources[0x24]	11580	1			T1	9		T3	5		T6	39
valid_sources[0x25]	6993	1			T1	3		T3	2		T6	48
valid_sources[0x26]	7221	1			T1	5		T3	6		T6	44
valid_sources[0x27]	8195	1			T1	11		T3	1		T6	28
valid_sources[0x28]	12106	1			T1	9		T6	38		T9	2
valid_sources[0x29]	8057	1			T1	6		T3	6		T6	40
valid_sources[0x2a]	7234	1			T1	4		T3	1		T6	50
valid_sources[0x2b]	9749	1			T1	13		T3	19		T6	28
valid_sources[0x2c]	6976	1			T1	5		T3	1		T6	45
valid_sources[0x2d]	11051	1			T1	7		T3	3		T6	32
valid_sources[0x2e]	7407	1			T1	6		T3	2		T6	39
valid_sources[0x2f]	6432	1			T1	8		T3	6		T6	26
valid_sources[0x30]	11273	1			T1	1		T3	12		T6	29
valid_sources[0x31]	7148	1			T1	6		T6	58		T16	3
valid_sources[0x32]	7317	1			T1	1		T6	21		T9	3
valid_sources[0x33]	6645	1			T1	4		T6	23		T7	10
valid_sources[0x34]	7061	1			T1	7		T3	11		T6	28
valid_sources[0x35]	19849	1			T1	2		T3	8		T6	29
valid_sources[0x36]	11340	1			T1	12		T6	31		T7	1
valid_sources[0x37]	11925	1			T1	9		T3	8		T6	27
valid_sources[0x38]	12896	1			T1	11		T3	1		T6	17
valid_sources[0x39]	16465	1			T1	21		T3	6		T6	19
valid_sources[0x3a]	11657	1			T1	3		T3	1		T6	21
valid_sources[0x3b]	7509	1			T1	10		T6	30		T7	1
valid_sources[0x3c]	8105	1			T1	17		T3	15		T6	28
valid_sources[0x3d]	11441	1			T1	3		T6	34		T7	13
valid_sources[0x3e]	9711	1			T1	11		T6	33		T7	11
valid_sources[0x3f]	9471	1			T1	8		T3	14		T6	30
valid_sources[0x40]	11237	1			T1	14		T3	1		T6	34
valid_sources[0x41]	7147	1			T1	2		T3	3		T6	42
valid_sources[0x42]	11810	1			T1	8		T6	37		T9	3
valid_sources[0x43]	6686	1			T6	32		T7	6		T9	6
valid_sources[0x44]	7257	1			T1	12		T6	28		T7	7
valid_sources[0x45]	11426	1			T1	6		T3	4		T6	35
valid_sources[0x46]	10256	1			T1	8		T6	52		T9	4
valid_sources[0x47]	9638	1			T1	2		T6	25		T9	2
valid_sources[0x48]	8104	1			T1	4		T3	2		T6	46
valid_sources[0x49]	6887	1			T1	1		T6	38		T7	7
valid_sources[0x4a]	7127	1			T1	9		T6	42		T7	8
valid_sources[0x4b]	8384	1			T1	10		T6	32		T7	7
valid_sources[0x4c]	12441	1			T1	5		T6	29		T9	3
valid_sources[0x4d]	7093	1			T1	3		T6	29		T7	7
valid_sources[0x4e]	7059	1			T1	8		T3	4		T6	29
valid_sources[0x4f]	6990	1			T1	10		T6	31		T7	8
valid_sources[0x50]	8085	1			T1	2		T3	1		T6	32
valid_sources[0x51]	7022	1			T3	4		T6	26		T7	12
valid_sources[0x52]	21610	1			T1	6		T3	10		T6	24
valid_sources[0x53]	16583	1			T1	7		T6	33		T7	13
valid_sources[0x54]	6847	1			T1	7		T6	44		T7	2
valid_sources[0x55]	24461	1			T1	11		T6	34		T7	7
valid_sources[0x56]	6933	1			T1	4		T3	10		T6	49
valid_sources[0x57]	7184	1			T1	9		T6	30		T7	11
valid_sources[0x58]	12303	1			T1	6		T6	38		T7	19
valid_sources[0x59]	6898	1			T1	11		T6	48		T7	20
valid_sources[0x5a]	8711	1			T1	11		T6	30		T9	1
valid_sources[0x5b]	7425	1			T1	29		T3	8		T6	40
valid_sources[0x5c]	7959	1			T1	3		T3	1		T6	29
valid_sources[0x5d]	7839	1			T1	13		T3	10		T6	27
valid_sources[0x5e]	7999	1			T1	13		T6	29		T7	17
valid_sources[0x5f]	20419	1			T1	11		T3	10		T6	27
valid_sources[0x60]	9110	1			T1	10		T3	7		T6	31
valid_sources[0x61]	11655	1			T1	7		T3	1		T6	46
valid_sources[0x62]	13222	1			T1	4		T3	1		T6	21
valid_sources[0x63]	6792	1			T1	5		T3	3		T6	33
valid_sources[0x64]	7313	1			T1	14		T3	4		T6	42
valid_sources[0x65]	9618	1			T1	6		T6	25		T7	11
valid_sources[0x66]	7709	1			T1	4		T3	3		T6	22
valid_sources[0x67]	7518	1			T1	8		T3	1		T6	36
valid_sources[0x68]	7202	1			T1	7		T6	30		T7	4
valid_sources[0x69]	7075	1			T1	2		T3	10		T6	28
valid_sources[0x6a]	10768	1			T1	9		T6	46		T7	8
valid_sources[0x6b]	7185	1			T1	12		T6	46		T7	15
valid_sources[0x6c]	11263	1			T1	6		T3	5		T6	25
valid_sources[0x6d]	6919	1			T1	15		T3	3		T6	19
valid_sources[0x6e]	8052	1			T1	7		T3	14		T6	13
valid_sources[0x6f]	8060	1			T1	10		T3	9		T6	22
valid_sources[0x70]	15011	1			T1	25		T3	13		T6	33
valid_sources[0x71]	7434	1			T1	14		T6	48		T9	2
valid_sources[0x72]	8897	1			T1	5		T3	3		T6	29
valid_sources[0x73]	8362	1			T1	9		T6	27		T9	5
valid_sources[0x74]	7908	1			T1	5		T3	1		T6	52
valid_sources[0x75]	15714	1			T1	9		T3	2		T6	26
valid_sources[0x76]	15555	1			T1	4		T3	5		T6	31
valid_sources[0x77]	9775	1			T1	6		T3	4		T6	45
valid_sources[0x78]	6728	1			T1	26		T3	3		T6	39
valid_sources[0x79]	8226	1			T1	3		T6	39		T7	5
valid_sources[0x7a]	14241	1			T1	4		T3	5		T6	35
valid_sources[0x7b]	6668	1			T1	6		T3	7		T6	34
valid_sources[0x7c]	7084	1			T1	11		T3	7		T6	38
valid_sources[0x7d]	7436	1			T1	9		T3	2		T6	27
valid_sources[0x7e]	7072	1			T1	4		T3	8		T6	42
valid_sources[0x7f]	6798	1			T1	14		T6	37		T7	1
valid_sources[0x80]	7251	1			T1	4		T3	2		T6	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1029751

1

T4

1

T1

1256

T2

39

values[0x0]

all_enables

biggest_size

78217

1

T4

2

T1

84

T2

9

values[0x1]

all_enables

biggest_size

56219

1

T1

71

T2

9

T3

132