Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30526	1			T1	17		T3	181		T5	23
auto[PWRUP]	104	1			T7	1		T43	1		T216	2
auto[ONEST_0]	70	1			T3	1		T32	1		T44	1
auto[ONEST_021]	24	1			T43	1		T44	1		T217	1
auto[ONEST_1]	100	1			T43	2		T44	3		T218	1
auto[ONEST_DONE]	7	1			T219	1		T220	1		T221	1
auto[LP_0]	117	1			T43	2		T44	2		T45	3
auto[LP_021]	36	1			T43	1		T34	2		T218	2
auto[LP_1]	150	1			T3	1		T43	5		T44	2
auto[LP_EVAL]	68	1			T3	1		T44	1		T34	1
auto[LP_SLP]	506	1			T3	6		T7	1		T43	13
auto[LP_PWRUP]	19	1			T3	1		T7	1		T45	1
auto[NP_0]	178	1			T3	1		T7	1		T43	2
auto[NP_021]	37	1			T3	1		T44	1		T216	1
auto[NP_1]	162	1			T3	1		T43	3		T44	2
auto[NP_EVAL]	50	1			T43	2		T218	1		T45	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T222

1

T223

1

T224

1

min

29937

1

T1

17

T3

176

T5

23

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29945	1			T1	17		T3	176		T5	23
pow[0x1]	9	1			T216	1		T175	1		T217	1
pow[0x2]	21	1			T43	1		T45	1		T225	1
pow[0x3]	33	1			T45	1		T85	1		T36	1
pow[0x4]	68	1			T3	1		T7	1		T44	2
pow[0x5]	121	1			T43	4		T44	2		T218	1
pow[0x6]	272	1			T3	2		T43	6		T44	4
pow[0x7]	592	1			T3	4		T7	1		T32	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

203

1

T3

3

T7

1

T32

1

min

29511

1

T1

17

T3

170

T5

23

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29511	1			T1	17		T3	170		T5	23
pow[0x4]	1	1			T226	1		-	-		-	-
pow[0x5]	2	1			T227	1		T226	1		-	-
pow[0x7]	4	1			T43	1		T216	1		T228	1
pow[0x8]	7	1			T44	1		T216	1		T229	1
pow[0x9]	9	1			T216	1		T217	1		T219	1
pow[0xa]	20	1			T43	1		T47	1		T85	1
pow[0xb]	50	1			T3	2		T7	1		T43	2
pow[0xc]	68	1			T218	1		T45	1		T229	1
pow[0xd]	155	1			T3	1		T43	6		T44	2
pow[0xe]	295	1			T3	1		T43	7		T44	4
pow[0xf]	634	1			T3	9		T43	7		T44	6