Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2257	1			T3	14		T6	5		T7	12
auto[PWRUP]	129	1			T3	2		T43	6		T44	2
auto[ONEST_0]	77	1			T3	1		T7	1		T43	3
auto[ONEST_021]	17	1			T43	1		T47	1		T85	1
auto[ONEST_1]	85	1			T3	1		T43	1		T44	2
auto[ONEST_DONE]	5	1			T296	1		T345	1		T346	1
auto[LP_0]	130	1			T7	1		T44	1		T34	2
auto[LP_021]	33	1			T44	1		T85	1		T46	2
auto[LP_1]	135	1			T3	1		T7	1		T32	1
auto[LP_EVAL]	56	1			T43	1		T44	1		T34	2
auto[LP_SLP]	546	1			T3	7		T7	5		T43	10
auto[LP_PWRUP]	31	1			T216	1		T47	2		T225	1
auto[NP_0]	243	1			T3	3		T32	4		T43	1
auto[NP_021]	47	1			T7	2		T32	1		T216	1
auto[NP_1]	228	1			T3	2		T7	1		T32	1
auto[NP_EVAL]	32	1			T32	2		T33	1		T229	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T217

1

T21

1

T347

1

min

1966

1

T3

9

T6

5

T7

21

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1980	1			T3	9		T6	5		T7	21
pow[0x1]	13	1			T216	1		T222	1		T296	1
pow[0x2]	24	1			T7	1		T43	1		T47	1
pow[0x3]	31	1			T32	1		T43	1		T44	1
pow[0x4]	61	1			T216	1		T47	1		T85	1
pow[0x5]	120	1			T3	1		T43	6		T44	1
pow[0x6]	261	1			T3	2		T43	7		T44	3
pow[0x7]	533	1			T3	7		T32	1		T43	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

168

1

T3

1

T43

5

T44

3

min

1345

1

T3

1

T6

5

T7

16

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1353	1			T3	1		T6	5		T7	16
pow[0x1]	15	1			T7	3		T32	1		T21	1
pow[0x2]	23	1			T32	1		T35	2		T36	2
pow[0x3]	47	1			T34	1		T17	2		T38	3
pow[0x4]	59	1			T32	5		T33	2		T34	1
pow[0x6]	1	1			T348	1		-	-		-	-
pow[0x7]	2	1			T347	1		T349	1		-	-
pow[0x8]	3	1			T43	1		T220	1		T350	1
pow[0x9]	11	1			T44	2		T175	2		T220	1
pow[0xa]	18	1			T3	1		T44	1		T216	1
pow[0xb]	42	1			T3	2		T43	1		T44	1
pow[0xc]	79	1			T3	1		T43	3		T218	1
pow[0xd]	156	1			T43	4		T44	2		T34	2
pow[0xe]	289	1			T3	1		T7	1		T43	5
pow[0xf]	576	1			T3	11		T7	1		T32	1