Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1415	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1623	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1535	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1626	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1573	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1443	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1491	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1310	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1512	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1570	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1545	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1459	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1412	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1645	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1385	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1596	0	0
adc_en_ctl_rd_A	2147483647	1406	0	0
adc_fsm_rst_rd_A	2147483647	1151	0	0
adc_intr_ctl_rd_A	2147483647	1605	0	0
adc_lp_sample_ctl_rd_A	2147483647	1339	0	0
adc_pd_ctl_rd_A	2147483647	1396	0	0
adc_sample_ctl_rd_A	2147483647	1131	0	0
adc_wakeup_ctl_rd_A	2147483647	1436	0	0
intr_enable_rd_A	2147483647	2103	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1415	0	0
T7	954623	33	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	29	0	0
T18	0	22	0	0
T19	0	23	0	0
T20	0	5	0	0
T21	0	17	0	0
T22	0	11	0	0
T23	0	21	0	0
T24	0	20	0	0
T25	0	37	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1623	0	0
T7	954623	57	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	33	0	0
T18	0	19	0	0
T19	0	32	0	0
T20	0	9	0	0
T21	0	21	0	0
T23	0	18	0	0
T24	0	15	0	0
T25	0	28	0	0
T26	572522	0	0	0
T27	162923	0	0	0
T28	0	11	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1535	0	0
T7	954623	34	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	33	0	0
T18	0	13	0	0
T19	0	27	0	0
T20	0	11	0	0
T21	0	12	0	0
T22	0	6	0	0
T23	0	18	0	0
T24	0	14	0	0
T25	0	45	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1626	0	0
T7	954623	27	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	59	0	0
T18	0	22	0	0
T19	0	21	0	0
T20	0	13	0	0
T21	0	24	0	0
T22	0	11	0	0
T23	0	18	0	0
T24	0	12	0	0
T25	0	54	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1573	0	0
T7	954623	31	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	32	0	0
T18	0	21	0	0
T19	0	36	0	0
T20	0	5	0	0
T21	0	17	0	0
T22	0	6	0	0
T23	0	20	0	0
T24	0	21	0	0
T25	0	39	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1443	0	0
T7	954623	28	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	50	0	0
T18	0	9	0	0
T19	0	19	0	0
T20	0	15	0	0
T21	0	7	0	0
T22	0	13	0	0
T23	0	20	0	0
T24	0	20	0	0
T25	0	43	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1491	0	0
T7	954623	30	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	36	0	0
T18	0	8	0	0
T19	0	12	0	0
T20	0	12	0	0
T21	0	11	0	0
T22	0	3	0	0
T23	0	25	0	0
T24	0	10	0	0
T25	0	35	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1310	0	0
T7	954623	43	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	23	0	0
T18	0	26	0	0
T19	0	26	0	0
T20	0	12	0	0
T21	0	23	0	0
T22	0	19	0	0
T23	0	14	0	0
T24	0	12	0	0
T25	0	45	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1512	0	0
T7	954623	40	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	31	0	0
T18	0	35	0	0
T19	0	24	0	0
T20	0	16	0	0
T21	0	26	0	0
T22	0	9	0	0
T23	0	14	0	0
T24	0	21	0	0
T25	0	22	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1570	0	0
T7	954623	31	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	25	0	0
T18	0	24	0	0
T19	0	14	0	0
T20	0	10	0	0
T21	0	22	0	0
T22	0	6	0	0
T23	0	16	0	0
T24	0	5	0	0
T25	0	38	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1545	0	0
T7	954623	45	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	45	0	0
T18	0	33	0	0
T19	0	25	0	0
T20	0	14	0	0
T21	0	18	0	0
T22	0	8	0	0
T23	0	6	0	0
T24	0	19	0	0
T25	0	33	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1459	0	0
T7	954623	45	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	33	0	0
T18	0	19	0	0
T19	0	19	0	0
T20	0	7	0	0
T21	0	21	0	0
T22	0	7	0	0
T23	0	17	0	0
T24	0	16	0	0
T25	0	30	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1412	0	0
T7	954623	34	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	29	0	0
T18	0	17	0	0
T19	0	19	0	0
T20	0	10	0	0
T21	0	16	0	0
T22	0	28	0	0
T23	0	15	0	0
T24	0	27	0	0
T25	0	43	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1645	0	0
T7	954623	58	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	37	0	0
T18	0	18	0	0
T19	0	39	0	0
T20	0	15	0	0
T21	0	4	0	0
T22	0	18	0	0
T23	0	19	0	0
T24	0	20	0	0
T25	0	33	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1385	0	0
T7	954623	51	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	35	0	0
T18	0	14	0	0
T19	0	17	0	0
T20	0	8	0	0
T21	0	19	0	0
T22	0	3	0	0
T23	0	10	0	0
T24	0	23	0	0
T25	0	48	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1596	0	0
T7	954623	33	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	29	0	0
T18	0	8	0	0
T19	0	24	0	0
T20	0	14	0	0
T21	0	15	0	0
T22	0	16	0	0
T23	0	26	0	0
T24	0	18	0	0
T25	0	44	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1406	0	0
T7	954623	57	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	36	0	0
T18	0	18	0	0
T19	0	18	0	0
T20	0	14	0	0
T21	0	21	0	0
T22	0	15	0	0
T23	0	11	0	0
T24	0	22	0	0
T25	0	40	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1151	0	0
T7	954623	48	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	41	0	0
T18	0	17	0	0
T19	0	29	0	0
T20	0	21	0	0
T21	0	21	0	0
T22	0	18	0	0
T23	0	9	0	0
T24	0	15	0	0
T25	0	29	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1605	0	0
T7	954623	51	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	33	0	0
T18	0	14	0	0
T19	0	18	0	0
T20	0	7	0	0
T21	0	12	0	0
T22	0	4	0	0
T23	0	8	0	0
T24	0	21	0	0
T25	0	30	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1339	0	0
T7	954623	29	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	36	0	0
T18	0	20	0	0
T19	0	24	0	0
T20	0	7	0	0
T21	0	30	0	0
T22	0	3	0	0
T23	0	13	0	0
T24	0	19	0	0
T25	0	33	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1396	0	0
T7	954623	34	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	31	0	0
T18	0	22	0	0
T19	0	10	0	0
T20	0	9	0	0
T21	0	15	0	0
T22	0	12	0	0
T23	0	25	0	0
T24	0	19	0	0
T25	0	44	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1131	0	0
T7	954623	64	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	22	0	0
T18	0	26	0	0
T19	0	13	0	0
T20	0	15	0	0
T21	0	9	0	0
T22	0	7	0	0
T23	0	17	0	0
T24	0	9	0	0
T25	0	26	0	0
T26	572522	0	0	0
T27	162923	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1436	0	0
T7	954623	46	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	35	0	0
T18	0	17	0	0
T19	0	41	0	0
T20	0	22	0	0
T21	0	17	0	0
T22	0	11	0	0
T23	0	8	0	0
T24	0	16	0	0
T25	0	45	0	0
T26	572522	0	0	0
T27	162923	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2103	0	0
T7	954623	53	0	0
T8	195449	0	0	0
T9	161933	0	0	0
T10	595988	0	0	0
T11	534214	0	0	0
T12	603474	0	0	0
T13	116170	0	0	0
T14	818314	0	0	0
T17	0	44	0	0
T18	0	15	0	0
T19	0	38	0	0
T20	0	65	0	0
T21	0	17	0	0
T22	0	12	0	0
T26	572522	0	0	0
T27	162923	0	0	0
T29	0	16	0	0
T30	0	17	0	0
T31	0	16	0	0