Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1241471	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1214641

1

T4

3

T1

2041

T2

465

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2151524	1			T4	1		T1	3894		T2	842
values[0x0]	151726	1			T4	1		T1	123		T2	49
values[0x1]	152862	1			T4	1		T1	127		T2	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	994184	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1461928

1

T4

3

T1

2446

T2

563

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8473	1			T2	4		T3	53		T6	5
valid_sources[0x01]	11112	1			T2	14		T3	65		T6	4
valid_sources[0x02]	10351	1			T2	4		T3	45		T6	5
valid_sources[0x03]	7298	1			T2	6		T3	57		T6	6
valid_sources[0x04]	7328	1			T2	7		T3	50		T6	3
valid_sources[0x05]	7452	1			T3	54		T6	1		T7	4
valid_sources[0x06]	8706	1			T2	5		T3	38		T6	3
valid_sources[0x07]	20661	1			T2	1		T3	46		T6	7
valid_sources[0x08]	11542	1			T2	6		T3	58		T6	3
valid_sources[0x09]	12146	1			T2	4		T3	51		T6	2
valid_sources[0x0a]	7297	1			T2	2		T3	57		T6	2
valid_sources[0x0b]	10201	1			T3	48		T6	8		T7	4
valid_sources[0x0c]	8290	1			T3	65		T6	10		T8	1
valid_sources[0x0d]	8499	1			T2	2		T3	57		T6	12
valid_sources[0x0e]	10192	1			T2	8		T3	53		T6	7
valid_sources[0x0f]	7416	1			T3	45		T6	3		T7	4
valid_sources[0x10]	7438	1			T2	2		T3	48		T6	2
valid_sources[0x11]	7659	1			T2	5		T3	47		T6	10
valid_sources[0x12]	9707	1			T2	11		T3	44		T6	3
valid_sources[0x13]	8621	1			T2	2		T3	43		T6	5
valid_sources[0x14]	8499	1			T2	2		T3	59		T6	1
valid_sources[0x15]	7959	1			T2	7		T3	46		T6	5
valid_sources[0x16]	7653	1			T2	4		T3	47		T6	2
valid_sources[0x17]	7410	1			T2	4		T3	42		T6	5
valid_sources[0x18]	7316	1			T2	2		T3	45		T6	2
valid_sources[0x19]	9416	1			T2	7		T3	66		T6	4
valid_sources[0x1a]	7434	1			T2	3		T3	46		T6	2
valid_sources[0x1b]	7597	1			T2	3		T3	61		T6	5
valid_sources[0x1c]	12098	1			T2	5		T3	41		T6	5
valid_sources[0x1d]	11558	1			T3	48		T6	3		T7	5
valid_sources[0x1e]	10271	1			T2	11		T3	37		T6	2
valid_sources[0x1f]	7335	1			T2	9		T3	48		T6	2
valid_sources[0x20]	7886	1			T2	3		T3	62		T6	3
valid_sources[0x21]	7776	1			T2	5		T3	45		T6	4
valid_sources[0x22]	12860	1			T2	2		T3	71		T6	5
valid_sources[0x23]	11815	1			T3	55		T6	2		T8	1
valid_sources[0x24]	11978	1			T2	6		T3	44		T6	2
valid_sources[0x25]	7468	1			T2	4		T3	38		T6	5
valid_sources[0x26]	7836	1			T2	2		T3	58		T6	4
valid_sources[0x27]	8553	1			T2	2		T3	62		T5	1047
valid_sources[0x28]	8056	1			T2	1		T3	54		T6	4
valid_sources[0x29]	11904	1			T2	7		T3	44		T6	4
valid_sources[0x2a]	11692	1			T2	3		T3	40		T6	1
valid_sources[0x2b]	9083	1			T2	3		T3	54		T6	5
valid_sources[0x2c]	8279	1			T2	4		T3	45		T6	2
valid_sources[0x2d]	7703	1			T2	1		T3	47		T6	3
valid_sources[0x2e]	7310	1			T2	5		T3	45		T6	4
valid_sources[0x2f]	7765	1			T4	1		T2	2		T3	48
valid_sources[0x30]	7696	1			T2	3		T3	51		T6	4
valid_sources[0x31]	11728	1			T3	55		T6	2		T7	3
valid_sources[0x32]	9145	1			T2	9		T3	62		T6	4
valid_sources[0x33]	8324	1			T2	3		T3	58		T6	5
valid_sources[0x34]	8954	1			T2	2		T3	33		T6	1
valid_sources[0x35]	7901	1			T2	2		T3	57		T6	2
valid_sources[0x36]	8366	1			T3	55		T6	1		T7	1
valid_sources[0x37]	7755	1			T2	8		T3	41		T6	5
valid_sources[0x38]	8412	1			T2	8		T3	51		T6	5
valid_sources[0x39]	7331	1			T2	2		T3	62		T6	5
valid_sources[0x3a]	7802	1			T2	5		T3	51		T6	5
valid_sources[0x3b]	14087	1			T2	2		T3	44		T6	11
valid_sources[0x3c]	8047	1			T2	3		T3	37		T6	7
valid_sources[0x3d]	8212	1			T2	5		T3	57		T6	3
valid_sources[0x3e]	12847	1			T2	1		T3	56		T6	5
valid_sources[0x3f]	7496	1			T2	10		T3	46		T6	7
valid_sources[0x40]	7908	1			T2	4		T3	56		T6	2
valid_sources[0x41]	7495	1			T2	2		T3	35		T6	5
valid_sources[0x42]	7718	1			T2	7		T3	45		T6	4
valid_sources[0x43]	7334	1			T2	5		T3	52		T6	4
valid_sources[0x44]	7305	1			T2	4		T3	59		T6	6
valid_sources[0x45]	12539	1			T2	2		T3	44		T6	2
valid_sources[0x46]	7714	1			T2	3		T3	46		T6	6
valid_sources[0x47]	18989	1			T3	51		T6	4		T7	5
valid_sources[0x48]	7746	1			T2	2		T3	49		T6	6
valid_sources[0x49]	11379	1			T2	5		T3	45		T6	9
valid_sources[0x4a]	8511	1			T3	49		T6	3		T7	6
valid_sources[0x4b]	10637	1			T2	2		T3	49		T6	3
valid_sources[0x4c]	14583	1			T2	2		T3	42		T6	2
valid_sources[0x4d]	7696	1			T2	6		T3	50		T6	2
valid_sources[0x4e]	7794	1			T2	7		T3	37		T6	2
valid_sources[0x4f]	7583	1			T2	7		T3	54		T6	5
valid_sources[0x50]	12836	1			T2	5		T3	42		T6	3
valid_sources[0x51]	7592	1			T2	7		T3	53		T6	6
valid_sources[0x52]	7382	1			T2	5		T3	51		T6	9
valid_sources[0x53]	10430	1			T2	5		T3	44		T6	3
valid_sources[0x54]	7628	1			T3	60		T6	10		T7	1
valid_sources[0x55]	8515	1			T2	3		T3	57		T6	5
valid_sources[0x56]	9335	1			T2	8		T3	44		T6	1
valid_sources[0x57]	17179	1			T1	4144		T2	10		T3	38
valid_sources[0x58]	11990	1			T2	6		T3	54		T6	6
valid_sources[0x59]	11469	1			T2	5		T3	53		T6	2
valid_sources[0x5a]	9041	1			T2	2		T3	60		T6	4
valid_sources[0x5b]	7344	1			T2	6		T3	51		T6	2
valid_sources[0x5c]	9504	1			T2	7		T3	48		T6	4
valid_sources[0x5d]	7145	1			T2	2		T3	57		T6	2
valid_sources[0x5e]	7828	1			T4	1		T2	7		T3	44
valid_sources[0x5f]	11868	1			T3	52		T6	4		T7	3
valid_sources[0x60]	7315	1			T2	3		T3	48		T6	9
valid_sources[0x61]	10265	1			T2	4		T3	47		T6	4
valid_sources[0x62]	8616	1			T2	2		T3	55		T6	5
valid_sources[0x63]	7030	1			T2	4		T3	49		T6	3
valid_sources[0x64]	8005	1			T2	2		T3	61		T6	1
valid_sources[0x65]	7499	1			T2	1		T3	47		T6	3
valid_sources[0x66]	10625	1			T2	1		T3	55		T6	4
valid_sources[0x67]	8572	1			T2	2		T3	52		T6	1
valid_sources[0x68]	7752	1			T2	1		T3	47		T6	4
valid_sources[0x69]	12448	1			T2	11		T3	47		T6	4
valid_sources[0x6a]	7499	1			T2	4		T3	55		T6	5
valid_sources[0x6b]	7070	1			T2	2		T3	40		T6	4
valid_sources[0x6c]	11972	1			T3	47		T6	4		T7	4
valid_sources[0x6d]	7684	1			T2	3		T3	45		T6	4
valid_sources[0x6e]	7002	1			T2	4		T3	52		T6	4
valid_sources[0x6f]	7503	1			T2	6		T3	46		T6	4
valid_sources[0x70]	9422	1			T2	4		T3	52		T6	10
valid_sources[0x71]	8117	1			T2	2		T3	52		T6	2
valid_sources[0x72]	9670	1			T2	2		T3	60		T6	5
valid_sources[0x73]	7600	1			T2	4		T3	59		T6	5
valid_sources[0x74]	10083	1			T2	5		T3	49		T6	6
valid_sources[0x75]	7890	1			T3	70		T6	8		T7	7
valid_sources[0x76]	7148	1			T3	50		T6	4		T7	6
valid_sources[0x77]	23283	1			T2	3		T3	55		T7	2
valid_sources[0x78]	8481	1			T2	5		T3	62		T6	7
valid_sources[0x79]	7854	1			T3	42		T6	8		T7	1
valid_sources[0x7a]	7459	1			T2	11		T3	54		T6	1
valid_sources[0x7b]	7742	1			T2	4		T3	57		T6	6
valid_sources[0x7c]	9164	1			T2	4		T3	48		T6	1
valid_sources[0x7d]	8061	1			T2	7		T3	64		T6	3
valid_sources[0x7e]	16902	1			T2	5		T3	53		T6	1
valid_sources[0x7f]	14392	1			T2	2		T3	52		T6	7
valid_sources[0x80]	10915	1			T3	50		T6	4		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1071971

1

T4

1

T1

1938

T2

418

values[0x0]

all_enables

biggest_size

82795

1

T4

1

T1

70

T2

32

values[0x1]

all_enables

biggest_size

59875

1

T4

1

T1

33

T2

15