Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30862	1			T1	8		T2	7		T3	18
auto[PWRUP]	122	1			T6	3		T8	2		T58	1
auto[ONEST_0]	55	1			T5	1		T8	1		T59	1
auto[ONEST_021]	25	1			T60	2		T61	3		T162	2
auto[ONEST_1]	106	1			T6	1		T59	1		T60	5
auto[ONEST_DONE]	5	1			T47	1		T225	1		T226	1
auto[LP_0]	106	1			T57	1		T59	2		T60	3
auto[LP_021]	33	1			T6	2		T58	1		T57	1
auto[LP_1]	118	1			T5	6		T8	4		T58	2
auto[LP_EVAL]	76	1			T5	3		T6	1		T8	1
auto[LP_SLP]	522	1			T5	5		T6	8		T8	3
auto[LP_PWRUP]	29	1			T8	1		T58	1		T61	1
auto[NP_0]	168	1			T5	2		T6	1		T8	3
auto[NP_021]	34	1			T8	1		T59	1		T61	1
auto[NP_1]	161	1			T5	3		T6	3		T8	1
auto[NP_EVAL]	38	1			T58	2		T61	2		T188	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T57

1

T188

1

T162

1

min

30231

1

T1

8

T2

7

T3

18

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30240	1			T1	8		T2	7		T3	18
pow[0x1]	10	1			T8	1		T58	1		T227	1
pow[0x2]	25	1			T8	1		T61	2		T211	1
pow[0x3]	37	1			T6	1		T58	1		T60	3
pow[0x4]	75	1			T5	3		T6	1		T8	3
pow[0x5]	137	1			T5	3		T6	2		T58	1
pow[0x6]	276	1			T5	5		T6	6		T8	2
pow[0x7]	586	1			T5	9		T6	6		T8	12

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

189

1

T5

7

T6

2

T8

4

min

29758

1

T1

8

T2

7

T3

18

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29758	1			T1	8		T2	7		T3	18
pow[0x2]	1	1			T228	1		-	-		-	-
pow[0x4]	1	1			T229	1		-	-		-	-
pow[0x6]	2	1			T230	1		T231	1		-	-
pow[0x7]	3	1			T232	1		T233	1		T234	1
pow[0x8]	4	1			T59	1		T60	1		T235	1
pow[0x9]	7	1			T52	1		T232	1		T235	1
pow[0xa]	12	1			T57	1		T60	1		T236	1
pow[0xb]	48	1			T6	1		T59	1		T60	2
pow[0xc]	69	1			T6	2		T59	2		T188	1
pow[0xd]	158	1			T5	1		T6	2		T59	1
pow[0xe]	292	1			T5	8		T6	6		T8	3
pow[0xf]	623	1			T5	9		T6	11		T8	10