Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2397	1			T4	10		T5	17		T6	22
auto[PWRUP]	140	1			T5	1		T8	2		T58	1
auto[ONEST_0]	84	1			T5	2		T57	1		T59	1
auto[ONEST_021]	22	1			T8	1		T61	1		T47	1
auto[ONEST_1]	97	1			T5	1		T6	3		T8	1
auto[ONEST_DONE]	2	1			T60	1		T233	1		-	-
auto[LP_0]	130	1			T5	1		T6	1		T8	1
auto[LP_021]	37	1			T8	1		T58	1		T40	1
auto[LP_1]	141	1			T5	1		T6	2		T8	2
auto[LP_EVAL]	64	1			T5	1		T57	2		T61	1
auto[LP_SLP]	570	1			T5	3		T6	3		T8	4
auto[LP_PWRUP]	28	1			T5	1		T8	1		T60	2
auto[NP_0]	239	1			T5	4		T6	3		T8	2
auto[NP_021]	51	1			T57	1		T59	1		T60	1
auto[NP_1]	251	1			T5	4		T6	3		T8	2
auto[NP_EVAL]	40	1			T59	2		T38	1		T39	4

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T61

1

T211

1

T377

1

min

2089

1

T4

10

T5

6

T6

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2107	1			T4	10		T5	6		T6	6
pow[0x1]	13	1			T58	1		T378	1		T379	1
pow[0x2]	26	1			T60	1		T47	1		T162	2
pow[0x3]	34	1			T8	2		T58	1		T188	1
pow[0x4]	71	1			T5	1		T6	2		T8	1
pow[0x5]	171	1			T5	3		T6	1		T57	4
pow[0x6]	272	1			T5	4		T6	3		T8	4
pow[0x7]	540	1			T5	8		T6	9		T8	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

198

1

T5

1

T6

5

T8

4

min

1455

1

T4

10

T5

3

T6

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1461	1			T4	10		T5	3		T6	2
pow[0x1]	5	1			T43	2		T234	1		T279	1
pow[0x2]	21	1			T39	1		T40	1		T42	1
pow[0x3]	49	1			T38	1		T39	1		T40	1
pow[0x4]	80	1			T38	2		T39	5		T40	1
pow[0x5]	1	1			T380	1		-	-		-	-
pow[0x7]	2	1			T162	1		T381	1		-	-
pow[0x8]	3	1			T187	1		T382	1		T383	1
pow[0x9]	11	1			T6	1		T384	2		T385	1
pow[0xa]	25	1			T5	1		T60	1		T162	1
pow[0xb]	43	1			T8	1		T58	1		T59	1
pow[0xc]	71	1			T5	1		T8	1		T58	2
pow[0xd]	151	1			T5	2		T6	2		T8	1
pow[0xe]	311	1			T5	5		T6	3		T8	4
pow[0xf]	635	1			T5	6		T6	5		T8	9