Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1742	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1730	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1778	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1780	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1815	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1691	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1940	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1773	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1752	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1781	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1677	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1578	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1844	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1832	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1768	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1689	0	0
adc_en_ctl_rd_A	2147483647	1509	0	0
adc_fsm_rst_rd_A	2147483647	1343	0	0
adc_intr_ctl_rd_A	2147483647	1899	0	0
adc_lp_sample_ctl_rd_A	2147483647	1292	0	0
adc_pd_ctl_rd_A	2147483647	1687	0	0
adc_sample_ctl_rd_A	2147483647	1379	0	0
adc_wakeup_ctl_rd_A	2147483647	1398	0	0
intr_enable_rd_A	2147483647	2098	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1742	0	0
T15	426452	53	0	0
T16	0	27	0	0
T17	0	34	0	0
T18	0	20	0	0
T19	0	17	0	0
T20	0	14	0	0
T21	0	33	0	0
T22	0	10	0	0
T23	0	14	0	0
T24	0	18	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1730	0	0
T15	426452	40	0	0
T16	0	27	0	0
T17	0	27	0	0
T18	0	14	0	0
T19	0	22	0	0
T20	0	15	0	0
T21	0	55	0	0
T22	0	8	0	0
T23	0	13	0	0
T24	0	21	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1778	0	0
T15	426452	31	0	0
T16	0	5	0	0
T17	0	44	0	0
T18	0	17	0	0
T19	0	42	0	0
T20	0	29	0	0
T21	0	36	0	0
T22	0	11	0	0
T23	0	20	0	0
T24	0	16	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1780	0	0
T15	426452	36	0	0
T16	0	22	0	0
T17	0	39	0	0
T18	0	9	0	0
T19	0	27	0	0
T20	0	36	0	0
T21	0	41	0	0
T22	0	8	0	0
T23	0	17	0	0
T24	0	8	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1815	0	0
T15	426452	52	0	0
T16	0	27	0	0
T17	0	27	0	0
T18	0	18	0	0
T19	0	37	0	0
T20	0	39	0	0
T21	0	37	0	0
T22	0	7	0	0
T23	0	28	0	0
T24	0	12	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1691	0	0
T15	426452	58	0	0
T16	0	8	0	0
T17	0	18	0	0
T18	0	9	0	0
T19	0	34	0	0
T20	0	22	0	0
T21	0	41	0	0
T22	0	6	0	0
T23	0	22	0	0
T24	0	5	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1940	0	0
T15	426452	43	0	0
T16	0	16	0	0
T17	0	19	0	0
T18	0	12	0	0
T19	0	21	0	0
T20	0	31	0	0
T21	0	51	0	0
T22	0	14	0	0
T23	0	13	0	0
T24	0	14	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1773	0	0
T15	426452	39	0	0
T16	0	20	0	0
T17	0	30	0	0
T18	0	20	0	0
T19	0	23	0	0
T20	0	14	0	0
T21	0	32	0	0
T22	0	5	0	0
T23	0	7	0	0
T24	0	14	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1752	0	0
T15	426452	22	0	0
T16	0	7	0	0
T17	0	22	0	0
T18	0	37	0	0
T19	0	45	0	0
T20	0	32	0	0
T21	0	47	0	0
T22	0	31	0	0
T23	0	20	0	0
T24	0	11	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1781	0	0
T15	426452	37	0	0
T16	0	21	0	0
T17	0	26	0	0
T18	0	1	0	0
T19	0	21	0	0
T20	0	15	0	0
T21	0	42	0	0
T22	0	15	0	0
T23	0	16	0	0
T24	0	18	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1677	0	0
T15	426452	24	0	0
T16	0	37	0	0
T17	0	24	0	0
T18	0	10	0	0
T19	0	15	0	0
T20	0	19	0	0
T21	0	36	0	0
T22	0	3	0	0
T23	0	22	0	0
T24	0	22	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1578	0	0
T15	426452	20	0	0
T16	0	4	0	0
T17	0	29	0	0
T18	0	18	0	0
T19	0	44	0	0
T20	0	19	0	0
T21	0	45	0	0
T22	0	4	0	0
T23	0	23	0	0
T24	0	17	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1844	0	0
T15	426452	41	0	0
T16	0	8	0	0
T17	0	37	0	0
T18	0	11	0	0
T19	0	28	0	0
T20	0	12	0	0
T21	0	48	0	0
T22	0	6	0	0
T23	0	27	0	0
T24	0	11	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1832	0	0
T15	426452	34	0	0
T16	0	21	0	0
T17	0	17	0	0
T18	0	12	0	0
T19	0	30	0	0
T20	0	26	0	0
T21	0	38	0	0
T22	0	12	0	0
T23	0	20	0	0
T24	0	12	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1768	0	0
T15	426452	31	0	0
T16	0	13	0	0
T17	0	29	0	0
T18	0	13	0	0
T19	0	16	0	0
T20	0	36	0	0
T21	0	53	0	0
T22	0	12	0	0
T23	0	18	0	0
T24	0	13	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1689	0	0
T15	426452	41	0	0
T16	0	27	0	0
T17	0	34	0	0
T18	0	15	0	0
T19	0	36	0	0
T20	0	17	0	0
T21	0	54	0	0
T22	0	7	0	0
T23	0	12	0	0
T24	0	10	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1509	0	0
T15	426452	27	0	0
T16	0	11	0	0
T17	0	41	0	0
T18	0	15	0	0
T19	0	15	0	0
T20	0	16	0	0
T21	0	36	0	0
T22	0	1	0	0
T23	0	29	0	0
T24	0	23	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1343	0	0
T15	426452	41	0	0
T16	0	27	0	0
T17	0	14	0	0
T18	0	21	0	0
T19	0	22	0	0
T20	0	14	0	0
T21	0	34	0	0
T23	0	30	0	0
T24	0	14	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0
T34	0	23	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1899	0	0
T15	426452	47	0	0
T16	0	19	0	0
T17	0	21	0	0
T18	0	16	0	0
T19	0	27	0	0
T20	0	16	0	0
T21	0	46	0	0
T22	0	5	0	0
T23	0	25	0	0
T24	0	10	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1292	0	0
T15	426452	28	0	0
T16	0	28	0	0
T17	0	22	0	0
T18	0	11	0	0
T19	0	29	0	0
T20	0	21	0	0
T21	0	38	0	0
T22	0	23	0	0
T23	0	20	0	0
T24	0	1	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1687	0	0
T15	426452	35	0	0
T16	0	23	0	0
T17	0	20	0	0
T18	0	8	0	0
T19	0	28	0	0
T20	0	32	0	0
T21	0	37	0	0
T22	0	16	0	0
T23	0	22	0	0
T24	0	18	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1379	0	0
T15	426452	49	0	0
T16	0	24	0	0
T17	0	15	0	0
T18	0	14	0	0
T19	0	32	0	0
T20	0	24	0	0
T21	0	34	0	0
T22	0	21	0	0
T23	0	21	0	0
T24	0	20	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1398	0	0
T15	426452	39	0	0
T16	0	21	0	0
T17	0	51	0	0
T18	0	12	0	0
T19	0	39	0	0
T20	0	31	0	0
T21	0	28	0	0
T22	0	3	0	0
T23	0	31	0	0
T24	0	6	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2098	0	0
T15	426452	61	0	0
T16	0	47	0	0
T17	0	45	0	0
T18	0	20	0	0
T19	0	98	0	0
T20	0	17	0	0
T21	0	40	0	0
T25	262521	0	0	0
T26	119917	0	0	0
T27	966256	0	0	0
T28	395016	0	0	0
T29	11093	0	0	0
T30	423282	0	0	0
T31	384391	0	0	0
T32	584854	0	0	0
T33	221773	0	0	0
T35	0	21	0	0
T36	0	17	0	0
T37	0	28	0	0