Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1195274	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1165549

1

T1

2183

T2

471

T3

6449

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2081665	1			T1	4047		T2	831		T3	12205
values[0x0]	139203	1			T1	198		T2	46		T3	399
values[0x1]	139955	1			T1	220		T2	48		T3	381

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	957561	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1403262

1

T1

2643

T2

556

T3

7761

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6615	1			T1	5		T2	1		T3	65
valid_sources[0x01]	6946	1			T2	5		T3	54		T4	9
valid_sources[0x02]	11898	1			T2	1		T3	62		T4	18
valid_sources[0x03]	6985	1			T1	34		T2	4		T3	53
valid_sources[0x04]	9668	1			T2	3		T3	62		T4	20
valid_sources[0x05]	19539	1			T2	5		T3	31		T4	8
valid_sources[0x06]	6364	1			T1	15		T2	5		T3	69
valid_sources[0x07]	11263	1			T1	8		T2	1		T3	32
valid_sources[0x08]	19781	1			T1	16		T2	6		T3	66
valid_sources[0x09]	8399	1			T1	41		T2	4		T3	50
valid_sources[0x0a]	7052	1			T2	5		T3	35		T4	8
valid_sources[0x0b]	15542	1			T1	18		T2	4		T3	74
valid_sources[0x0c]	6814	1			T2	1		T3	48		T4	3
valid_sources[0x0d]	6769	1			T1	78		T2	2		T3	46
valid_sources[0x0e]	9607	1			T2	4		T3	54		T4	9
valid_sources[0x0f]	21114	1			T1	20		T2	3		T3	50
valid_sources[0x10]	12082	1			T2	4		T3	58		T4	4
valid_sources[0x11]	6836	1			T1	8		T2	4		T3	59
valid_sources[0x12]	8149	1			T1	6		T2	4		T3	48
valid_sources[0x13]	6688	1			T1	4		T2	3		T3	66
valid_sources[0x14]	8716	1			T2	6		T3	43		T4	2
valid_sources[0x15]	6799	1			T2	2		T3	44		T4	6
valid_sources[0x16]	7027	1			T1	3		T2	3		T3	36
valid_sources[0x17]	8977	1			T1	10		T2	1		T3	36
valid_sources[0x18]	6554	1			T1	48		T2	8		T3	49
valid_sources[0x19]	6723	1			T1	10		T2	6		T3	63
valid_sources[0x1a]	10459	1			T1	12		T2	5		T3	49
valid_sources[0x1b]	9696	1			T1	43		T2	6		T3	65
valid_sources[0x1c]	11091	1			T2	2		T3	72		T4	15
valid_sources[0x1d]	6829	1			T1	28		T2	2		T3	41
valid_sources[0x1e]	9246	1			T2	2		T3	56		T4	9
valid_sources[0x1f]	6993	1			T1	40		T2	1		T3	73
valid_sources[0x20]	7468	1			T2	4		T3	63		T4	24
valid_sources[0x21]	6924	1			T1	6		T2	2		T3	47
valid_sources[0x22]	6638	1			T2	3		T3	48		T4	21
valid_sources[0x23]	10912	1			T2	3		T3	67		T4	12
valid_sources[0x24]	9780	1			T1	5		T2	3		T3	65
valid_sources[0x25]	6732	1			T2	7		T3	67		T4	5
valid_sources[0x26]	19326	1			T2	2		T3	57		T4	9
valid_sources[0x27]	9359	1			T2	2		T3	41		T4	15
valid_sources[0x28]	15620	1			T1	37		T2	8		T3	29
valid_sources[0x29]	14569	1			T1	3		T2	2		T3	54
valid_sources[0x2a]	7732	1			T1	20		T2	4		T3	55
valid_sources[0x2b]	15422	1			T1	2		T2	4		T3	59
valid_sources[0x2c]	6758	1			T1	2		T2	2		T3	62
valid_sources[0x2d]	6958	1			T2	4		T3	50		T4	7
valid_sources[0x2e]	11093	1			T1	7		T2	3		T3	41
valid_sources[0x2f]	8249	1			T2	5		T3	58		T4	10
valid_sources[0x30]	12505	1			T1	4		T2	4		T3	48
valid_sources[0x31]	7961	1			T2	4		T3	32		T4	5
valid_sources[0x32]	10187	1			T1	6		T2	2		T3	60
valid_sources[0x33]	7669	1			T3	51		T4	9		T5	4
valid_sources[0x34]	8912	1			T1	7		T2	3		T3	61
valid_sources[0x35]	7514	1			T2	3		T3	60		T4	6
valid_sources[0x36]	6658	1			T1	11		T3	56		T4	6
valid_sources[0x37]	11303	1			T1	4		T2	6		T3	43
valid_sources[0x38]	7375	1			T2	4		T3	56		T4	5
valid_sources[0x39]	7348	1			T2	7		T3	39		T4	37
valid_sources[0x3a]	11920	1			T2	5		T3	44		T4	21
valid_sources[0x3b]	6666	1			T1	3		T2	4		T3	53
valid_sources[0x3c]	6834	1			T1	12		T2	3		T3	41
valid_sources[0x3d]	13629	1			T1	8		T2	2		T3	46
valid_sources[0x3e]	11704	1			T1	4		T2	5		T3	45
valid_sources[0x3f]	10986	1			T2	6		T3	44		T4	23
valid_sources[0x40]	6932	1			T2	5		T3	52		T4	3
valid_sources[0x41]	11100	1			T1	6		T2	6		T3	59
valid_sources[0x42]	8434	1			T1	28		T2	2		T3	45
valid_sources[0x43]	10025	1			T1	44		T2	3		T3	67
valid_sources[0x44]	7826	1			T1	12		T2	4		T3	29
valid_sources[0x45]	15489	1			T1	16		T3	64		T4	26
valid_sources[0x46]	7032	1			T1	25		T2	1		T3	72
valid_sources[0x47]	7651	1			T2	5		T3	32		T4	16
valid_sources[0x48]	6671	1			T2	4		T3	47		T4	4
valid_sources[0x49]	7013	1			T2	3		T3	61		T4	3
valid_sources[0x4a]	7763	1			T1	10		T2	3		T3	43
valid_sources[0x4b]	15460	1			T2	2		T3	56		T4	9
valid_sources[0x4c]	6579	1			T1	45		T2	1		T3	61
valid_sources[0x4d]	7492	1			T1	12		T2	5		T3	52
valid_sources[0x4e]	6547	1			T1	36		T3	54		T4	17
valid_sources[0x4f]	11671	1			T1	10		T2	3		T3	69
valid_sources[0x50]	7604	1			T1	9		T2	4		T3	60
valid_sources[0x51]	8584	1			T1	1		T2	3		T3	53
valid_sources[0x52]	7025	1			T1	32		T2	7		T3	61
valid_sources[0x53]	6848	1			T1	21		T2	1		T3	45
valid_sources[0x54]	7291	1			T1	52		T2	1		T3	59
valid_sources[0x55]	14384	1			T1	12		T2	8		T3	37
valid_sources[0x56]	15486	1			T1	1		T2	4		T3	63
valid_sources[0x57]	12475	1			T1	3		T2	6		T3	37
valid_sources[0x58]	11724	1			T1	5		T2	5		T3	71
valid_sources[0x59]	6595	1			T2	2		T3	64		T4	25
valid_sources[0x5a]	7065	1			T2	2		T3	48		T4	2
valid_sources[0x5b]	7071	1			T1	21		T2	3		T3	53
valid_sources[0x5c]	7032	1			T1	2		T2	1		T3	64
valid_sources[0x5d]	6954	1			T1	45		T2	6		T3	68
valid_sources[0x5e]	6721	1			T1	15		T2	1		T3	60
valid_sources[0x5f]	9273	1			T2	2		T3	64		T4	6
valid_sources[0x60]	6497	1			T1	18		T2	6		T3	42
valid_sources[0x61]	6735	1			T1	14		T2	6		T3	56
valid_sources[0x62]	9293	1			T1	10		T2	2		T3	57
valid_sources[0x63]	7095	1			T2	5		T3	54		T4	7
valid_sources[0x64]	10749	1			T2	3		T3	43		T4	12
valid_sources[0x65]	9258	1			T1	4		T2	6		T3	37
valid_sources[0x66]	9818	1			T2	4		T3	53		T4	11
valid_sources[0x67]	8328	1			T2	2		T3	36		T4	6
valid_sources[0x68]	11462	1			T1	7		T2	2		T3	52
valid_sources[0x69]	7184	1			T2	2		T3	31		T4	6
valid_sources[0x6a]	10951	1			T2	3		T3	52		T4	20
valid_sources[0x6b]	7297	1			T1	31		T2	4		T3	39
valid_sources[0x6c]	6922	1			T1	15		T2	7		T3	44
valid_sources[0x6d]	9811	1			T1	19		T2	7		T3	56
valid_sources[0x6e]	6718	1			T1	5		T3	40		T4	12
valid_sources[0x6f]	15377	1			T1	8		T2	6		T3	65
valid_sources[0x70]	7001	1			T2	3		T3	60		T4	18
valid_sources[0x71]	6828	1			T1	39		T2	1		T3	51
valid_sources[0x72]	10836	1			T1	13		T3	56		T4	4
valid_sources[0x73]	10851	1			T1	26		T2	6		T3	37
valid_sources[0x74]	10845	1			T1	8		T2	2		T3	40
valid_sources[0x75]	10790	1			T1	71		T2	1		T3	55
valid_sources[0x76]	11211	1			T1	48		T2	4		T3	39
valid_sources[0x77]	15201	1			T2	6		T3	36		T4	5
valid_sources[0x78]	11226	1			T1	7		T2	1		T3	58
valid_sources[0x79]	6783	1			T1	7		T2	5		T3	39
valid_sources[0x7a]	6644	1			T1	13		T2	6		T3	42
valid_sources[0x7b]	11448	1			T1	40		T2	5		T3	44
valid_sources[0x7c]	6555	1			T2	7		T3	36		T4	16
valid_sources[0x7d]	7552	1			T1	14		T2	5		T3	52
valid_sources[0x7e]	16499	1			T1	2		T2	3		T3	44
valid_sources[0x7f]	13749	1			T1	37		T2	3		T3	54
valid_sources[0x80]	7505	1			T1	6		T3	38		T4	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1036456

1

T1

2018

T2

430

T3

6143

values[0x0]

all_enables

biggest_size

75333

1

T1

98

T2

23

T3

188

values[0x1]

all_enables

biggest_size

53760

1

T1

67

T2

18

T3

118