Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27882	1			T1	11		T2	7		T3	24
auto[PWRUP]	105	1			T48	2		T43	2		T49	1
auto[ONEST_0]	63	1			T48	2		T50	1		T49	1
auto[ONEST_021]	15	1			T139	2		T200	1		T201	1
auto[ONEST_1]	81	1			T43	2		T31	2		T51	1
auto[ONEST_DONE]	5	1			T202	1		T203	1		T204	1
auto[LP_0]	116	1			T48	3		T43	2		T31	3
auto[LP_021]	28	1			T48	1		T43	1		T139	1
auto[LP_1]	114	1			T48	3		T43	1		T50	1
auto[LP_EVAL]	61	1			T48	1		T50	2		T31	3
auto[LP_SLP]	495	1			T48	5		T43	5		T50	6
auto[LP_PWRUP]	30	1			T50	1		T49	1		T205	2
auto[NP_0]	154	1			T48	3		T50	1		T49	2
auto[NP_021]	17	1			T50	1		T49	1		T31	1
auto[NP_1]	168	1			T48	4		T43	4		T49	3
auto[NP_EVAL]	30	1			T48	1		T49	1		T53	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T206

1

T207

1

T208

1

min

27391

1

T1

11

T2

7

T3

24

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27400	1			T1	11		T2	7		T3	24
pow[0x1]	4	1			T201	1		T209	1		T210	1
pow[0x2]	11	1			T205	1		T211	1		T212	1
pow[0x3]	23	1			T48	1		T50	1		T31	1
pow[0x4]	66	1			T48	1		T43	1		T50	1
pow[0x5]	131	1			T48	3		T43	3		T50	1
pow[0x6]	242	1			T48	3		T43	2		T49	6
pow[0x7]	488	1			T48	6		T43	7		T50	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

191

1

T48

3

T43

2

T50

1

min

26915

1

T1

11

T2

7

T3

24

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26915	1			T1	11		T2	7		T3	24
pow[0x4]	1	1			T213	1		-	-		-	-
pow[0x5]	1	1			T214	1		-	-		-	-
pow[0x6]	4	1			T31	1		T202	1		T204	1
pow[0x8]	4	1			T215	1		T208	1		T216	1
pow[0x9]	10	1			T205	1		T209	1		T217	1
pow[0xa]	19	1			T139	1		T200	1		T218	1
pow[0xb]	28	1			T48	1		T50	1		T219	1
pow[0xc]	82	1			T50	3		T49	2		T31	1
pow[0xd]	141	1			T50	2		T49	2		T31	3
pow[0xe]	285	1			T48	2		T43	1		T50	4
pow[0xf]	540	1			T48	11		T43	7		T50	7