Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2143	1			T48	22		T43	16		T50	11
auto[PWRUP]	125	1			T48	2		T53	2		T139	2
auto[ONEST_0]	65	1			T48	1		T50	1		T49	1
auto[ONEST_021]	31	1			T43	1		T27	1		T53	1
auto[ONEST_1]	94	1			T48	1		T43	1		T50	1
auto[ONEST_DONE]	1	1			T290	1		-	-		-	-
auto[LP_0]	126	1			T48	3		T43	2		T49	3
auto[LP_021]	29	1			T48	1		T43	1		T49	1
auto[LP_1]	132	1			T48	2		T43	1		T50	1
auto[LP_EVAL]	47	1			T49	1		T31	2		T12	1
auto[LP_SLP]	441	1			T48	7		T43	3		T50	7
auto[LP_PWRUP]	27	1			T48	1		T49	1		T51	1
auto[NP_0]	196	1			T48	3		T43	1		T49	1
auto[NP_021]	40	1			T43	2		T49	1		T51	1
auto[NP_1]	182	1			T48	2		T43	2		T31	4
auto[NP_EVAL]	21	1			T43	1		T50	2		T31	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T49

1

T349

1

T350

1

min

1688

1

T48

11

T43

9

T50

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1700	1			T48	11		T43	9		T50	7
pow[0x1]	5	1			T351	1		T206	1		T304	1
pow[0x2]	16	1			T50	1		T49	1		T205	1
pow[0x3]	32	1			T43	1		T53	1		T352	1
pow[0x4]	64	1			T48	1		T43	3		T50	2
pow[0x5]	143	1			T48	1		T50	1		T49	2
pow[0x6]	249	1			T48	6		T43	2		T49	2
pow[0x7]	516	1			T48	7		T43	4		T50	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

192

1

T48

2

T50

3

T49

3

min

1234

1

T48

4

T43

8

T50

1

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1242	1			T48	4		T43	8		T50	1
pow[0x1]	9	1			T36	1		T16	1		T276	1
pow[0x2]	20	1			T12	1		T33	1		T350	1
pow[0x3]	19	1			T27	1		T14	1		T353	3
pow[0x4]	8	1			T12	1		T33	1		T39	1
pow[0x6]	1	1			T354	1		-	-		-	-
pow[0x7]	3	1			T139	2		T355	1		-	-
pow[0x8]	2	1			T356	1		T357	1		-	-
pow[0x9]	6	1			T358	1		T210	1		T204	1
pow[0xa]	21	1			T31	2		T139	1		T51	2
pow[0xb]	32	1			T139	2		T205	1		T200	1
pow[0xc]	47	1			T50	2		T49	1		T31	3
pow[0xd]	127	1			T48	1		T43	2		T49	1
pow[0xe]	295	1			T48	10		T43	4		T50	5
pow[0xf]	577	1			T48	13		T43	8		T50	1