Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1153582	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1124939

1

T1

140

T2

2068

T3

955

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2002388	1			T1	204		T2	4015		T3	1667
values[0x0]	137104	1			T1	29		T2	99		T3	103
values[0x1]	139029	1			T1	25		T2	127		T3	118

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	923901	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1354620

1

T1

162

T2

2501

T3

1148

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6631	1			T2	14		T3	3		T4	2
valid_sources[0x01]	6869	1			T2	13		T3	9		T4	3
valid_sources[0x02]	10924	1			T2	25		T3	5		T6	1
valid_sources[0x03]	6922	1			T2	10		T3	7		T4	2
valid_sources[0x04]	6400	1			T1	3		T2	20		T3	3
valid_sources[0x05]	8374	1			T1	1		T2	18		T3	11
valid_sources[0x06]	12158	1			T1	2		T2	22		T3	11
valid_sources[0x07]	6573	1			T1	1		T2	8		T3	8
valid_sources[0x08]	6973	1			T2	18		T3	9		T4	1
valid_sources[0x09]	6836	1			T1	1		T2	17		T3	13
valid_sources[0x0a]	7020	1			T1	4		T2	17		T3	3
valid_sources[0x0b]	7509	1			T2	19		T3	5		T4	5
valid_sources[0x0c]	6710	1			T2	19		T3	4		T4	1
valid_sources[0x0d]	7587	1			T2	17		T3	5		T4	1
valid_sources[0x0e]	11381	1			T2	23		T3	9		T6	2
valid_sources[0x0f]	11265	1			T2	14		T3	3		T7	1
valid_sources[0x10]	8588	1			T2	10		T3	7		T40	1
valid_sources[0x11]	6483	1			T2	14		T3	5		T4	4
valid_sources[0x12]	6746	1			T2	14		T3	5		T4	1
valid_sources[0x13]	6614	1			T2	18		T3	10		T7	1
valid_sources[0x14]	6556	1			T1	1		T2	20		T3	6
valid_sources[0x15]	6743	1			T2	17		T3	11		T40	1
valid_sources[0x16]	6953	1			T2	15		T3	3		T4	9
valid_sources[0x17]	6798	1			T1	3		T2	15		T3	11
valid_sources[0x18]	6870	1			T1	1		T2	13		T3	16
valid_sources[0x19]	6441	1			T2	15		T3	9		T4	4
valid_sources[0x1a]	6755	1			T1	5		T2	15		T3	7
valid_sources[0x1b]	13962	1			T2	23		T3	11		T4	7
valid_sources[0x1c]	10691	1			T1	2		T2	5		T3	5
valid_sources[0x1d]	6545	1			T1	1		T2	17		T3	11
valid_sources[0x1e]	6419	1			T2	23		T3	10		T40	3
valid_sources[0x1f]	12366	1			T1	1		T2	15		T3	3
valid_sources[0x20]	15249	1			T2	22		T3	12		T6	1
valid_sources[0x21]	8590	1			T2	11		T3	2		T4	5
valid_sources[0x22]	7415	1			T1	3		T2	15		T3	11
valid_sources[0x23]	7034	1			T2	32		T3	10		T6	4
valid_sources[0x24]	9058	1			T2	6		T3	14		T4	10
valid_sources[0x25]	10863	1			T2	19		T3	4		T4	2
valid_sources[0x26]	7223	1			T2	29		T3	12		T4	12
valid_sources[0x27]	6976	1			T1	2		T2	9		T3	9
valid_sources[0x28]	7388	1			T1	1		T2	14		T3	13
valid_sources[0x29]	7434	1			T1	1		T2	20		T3	2
valid_sources[0x2a]	7370	1			T1	3		T2	13		T3	6
valid_sources[0x2b]	12109	1			T2	18		T3	6		T4	8
valid_sources[0x2c]	11324	1			T1	1		T2	14		T3	6
valid_sources[0x2d]	6732	1			T1	2		T2	16		T3	15
valid_sources[0x2e]	12207	1			T2	19		T3	6		T7	1
valid_sources[0x2f]	19137	1			T2	17		T3	5		T6	1
valid_sources[0x30]	11621	1			T2	12		T3	4		T4	2
valid_sources[0x31]	12219	1			T2	14		T3	7		T6	1
valid_sources[0x32]	8242	1			T1	2		T2	14		T3	10
valid_sources[0x33]	6553	1			T2	14		T3	5		T4	8
valid_sources[0x34]	6872	1			T2	20		T3	6		T4	1
valid_sources[0x35]	7353	1			T2	15		T3	7		T6	1
valid_sources[0x36]	6719	1			T1	1		T2	11		T3	4
valid_sources[0x37]	6719	1			T2	17		T3	5		T4	2
valid_sources[0x38]	7880	1			T2	28		T3	10		T4	6
valid_sources[0x39]	6939	1			T1	2		T2	9		T3	4
valid_sources[0x3a]	6834	1			T1	3		T2	15		T3	10
valid_sources[0x3b]	6550	1			T1	2		T2	16		T3	2
valid_sources[0x3c]	12692	1			T2	12		T3	11		T4	6
valid_sources[0x3d]	7032	1			T2	15		T3	5		T6	1
valid_sources[0x3e]	7004	1			T1	1		T2	15		T3	10
valid_sources[0x3f]	6660	1			T2	19		T3	4		T4	7
valid_sources[0x40]	7601	1			T1	3		T2	16		T3	4
valid_sources[0x41]	9645	1			T2	13		T3	5		T4	1
valid_sources[0x42]	11013	1			T2	13		T3	10		T4	1
valid_sources[0x43]	8596	1			T1	2		T2	15		T3	3
valid_sources[0x44]	6847	1			T2	15		T3	8		T4	11
valid_sources[0x45]	6741	1			T2	15		T3	11		T6	2
valid_sources[0x46]	6696	1			T1	1		T2	10		T3	11
valid_sources[0x47]	15146	1			T1	3		T2	15		T3	4
valid_sources[0x48]	8230	1			T2	22		T3	3		T6	1
valid_sources[0x49]	6548	1			T2	18		T3	3		T4	5
valid_sources[0x4a]	6294	1			T2	26		T3	4		T11	1
valid_sources[0x4b]	7577	1			T2	20		T3	8		T6	2
valid_sources[0x4c]	8615	1			T1	2		T2	25		T3	4
valid_sources[0x4d]	6487	1			T2	18		T3	3		T6	1
valid_sources[0x4e]	11110	1			T1	5		T2	20		T3	7
valid_sources[0x4f]	6717	1			T2	13		T3	4		T4	9
valid_sources[0x50]	6536	1			T1	1		T2	17		T3	7
valid_sources[0x51]	13660	1			T1	2		T2	16		T3	6
valid_sources[0x52]	11206	1			T2	26		T3	12		T4	3
valid_sources[0x53]	6683	1			T2	26		T3	8		T4	3
valid_sources[0x54]	6791	1			T1	3		T2	14		T3	4
valid_sources[0x55]	6505	1			T2	15		T3	11		T4	1
valid_sources[0x56]	6864	1			T1	2		T2	9		T3	6
valid_sources[0x57]	7651	1			T2	14		T3	3		T11	3
valid_sources[0x58]	7686	1			T1	2		T2	11		T3	5
valid_sources[0x59]	6857	1			T1	1		T2	21		T3	6
valid_sources[0x5a]	6303	1			T1	2		T2	17		T3	7
valid_sources[0x5b]	7526	1			T2	10		T3	5		T6	1
valid_sources[0x5c]	7381	1			T1	9		T2	17		T3	10
valid_sources[0x5d]	6772	1			T2	17		T3	8		T4	3
valid_sources[0x5e]	6354	1			T2	14		T3	13		T4	10
valid_sources[0x5f]	6517	1			T1	4		T2	16		T3	9
valid_sources[0x60]	6603	1			T1	1		T2	19		T3	7
valid_sources[0x61]	9688	1			T2	18		T3	5		T11	3
valid_sources[0x62]	6721	1			T2	18		T3	6		T4	2
valid_sources[0x63]	6535	1			T2	12		T3	6		T6	2
valid_sources[0x64]	6798	1			T2	16		T3	8		T6	1
valid_sources[0x65]	6489	1			T1	2		T2	9		T3	9
valid_sources[0x66]	11237	1			T2	16		T3	13		T11	4
valid_sources[0x67]	8356	1			T2	17		T3	8		T6	2
valid_sources[0x68]	6549	1			T1	2		T2	13		T3	7
valid_sources[0x69]	17464	1			T1	1		T2	16		T3	15
valid_sources[0x6a]	10363	1			T1	3		T2	18		T3	13
valid_sources[0x6b]	7042	1			T2	21		T3	13		T4	21
valid_sources[0x6c]	9532	1			T2	21		T3	7		T4	11
valid_sources[0x6d]	6504	1			T2	18		T3	5		T4	7
valid_sources[0x6e]	11962	1			T1	3		T2	10		T3	8
valid_sources[0x6f]	6606	1			T1	1		T2	29		T3	2
valid_sources[0x70]	14860	1			T2	21		T3	8		T4	14
valid_sources[0x71]	6534	1			T2	19		T3	12		T4	2
valid_sources[0x72]	6337	1			T2	17		T3	10		T4	18
valid_sources[0x73]	8501	1			T2	11		T3	4		T4	6
valid_sources[0x74]	6416	1			T1	6		T2	21		T3	7
valid_sources[0x75]	10540	1			T2	9		T3	7		T6	2
valid_sources[0x76]	6377	1			T2	20		T3	7		T11	4
valid_sources[0x77]	6329	1			T2	10		T3	7		T4	1
valid_sources[0x78]	13889	1			T1	3		T2	10		T3	3
valid_sources[0x79]	15278	1			T1	1		T2	20		T3	6
valid_sources[0x7a]	10622	1			T2	16		T3	12		T4	1
valid_sources[0x7b]	6698	1			T1	1		T2	22		T3	11
valid_sources[0x7c]	6886	1			T2	9		T3	8		T4	17
valid_sources[0x7d]	6672	1			T1	3		T2	19		T3	12
valid_sources[0x7e]	6642	1			T2	15		T3	6		T7	1
valid_sources[0x7f]	10767	1			T1	2		T2	14		T3	11
valid_sources[0x80]	7213	1			T1	2		T2	11		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

996017

1

T1

109

T2

1985

T3

844

values[0x0]

all_enables

biggest_size

74759

1

T1

18

T2

37

T3

66

values[0x1]

all_enables

biggest_size

54163

1

T1

13

T2

46

T3

45