Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27508	1			T1	4		T2	6		T3	18
auto[PWRUP]	117	1			T34	1		T58	1		T60	3
auto[ONEST_0]	66	1			T34	3		T58	2		T60	1
auto[ONEST_021]	14	1			T59	1		T228	1		T229	1
auto[ONEST_1]	63	1			T34	1		T58	1		T59	1
auto[ONEST_DONE]	4	1			T230	1		T231	1		T232	1
auto[LP_0]	117	1			T34	1		T58	1		T60	2
auto[LP_021]	29	1			T58	1		T60	1		T62	2
auto[LP_1]	122	1			T34	6		T58	1		T60	2
auto[LP_EVAL]	58	1			T1	1		T60	4		T233	3
auto[LP_SLP]	453	1			T34	9		T58	6		T60	12
auto[LP_PWRUP]	27	1			T60	1		T62	1		T234	1
auto[NP_0]	141	1			T34	2		T58	2		T62	6
auto[NP_021]	40	1			T34	1		T63	1		T228	1
auto[NP_1]	156	1			T34	1		T58	1		T60	4
auto[NP_EVAL]	30	1			T11	1		T62	1		T233	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T34

1

T230

1

T235

1

min

27059

1

T1

4

T2

6

T3

18

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27065	1			T1	4		T2	6		T3	18
pow[0x1]	10	1			T34	1		T236	1		T65	1
pow[0x2]	16	1			T233	1		T234	1		T237	1
pow[0x3]	32	1			T58	1		T60	2		T233	1
pow[0x4]	64	1			T58	1		T60	2		T62	1
pow[0x5]	107	1			T34	1		T58	1		T60	1
pow[0x6]	252	1			T1	1		T34	9		T58	3
pow[0x7]	470	1			T34	5		T58	5		T60	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

164

1

T11

1

T34

2

T58

1

min

26629

1

T1

4

T2

6

T3

18

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26629	1			T1	4		T2	6		T3	18
pow[0x4]	1	1			T238	1		-	-		-	-
pow[0x5]	4	1			T237	1		T239	1		T65	1
pow[0x6]	3	1			T34	1		T240	1		T241	1
pow[0x7]	2	1			T242	1		T243	1		-	-
pow[0x8]	3	1			T62	1		T240	1		T244	1
pow[0x9]	4	1			T238	1		T66	1		T245	1
pow[0xa]	13	1			T246	1		T247	1		T240	1
pow[0xb]	23	1			T248	1		T234	2		T249	1
pow[0xc]	76	1			T34	1		T60	3		T233	2
pow[0xd]	132	1			T34	3		T60	5		T59	1
pow[0xe]	262	1			T34	3		T58	6		T60	7
pow[0xf]	527	1			T34	9		T58	6		T60	6