Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2154	1			T1	4		T6	3		T17	20
auto[PWRUP]	124	1			T18	1		T34	2		T58	1
auto[ONEST_0]	63	1			T34	1		T42	1		T58	2
auto[ONEST_021]	17	1			T34	3		T58	1		T19	1
auto[ONEST_1]	94	1			T42	1		T58	3		T60	1
auto[ONEST_DONE]	5	1			T246	1		T250	1		T251	1
auto[LP_0]	129	1			T58	3		T60	3		T44	1
auto[LP_021]	23	1			T34	2		T60	1		T248	1
auto[LP_1]	120	1			T34	2		T42	1		T60	1
auto[LP_EVAL]	41	1			T1	1		T58	1		T59	1
auto[LP_SLP]	482	1			T34	11		T42	1		T58	5
auto[LP_PWRUP]	22	1			T62	1		T249	1		T252	1
auto[NP_0]	192	1			T34	3		T42	1		T58	4
auto[NP_021]	42	1			T11	1		T34	1		T63	2
auto[NP_1]	186	1			T1	1		T11	3		T18	1
auto[NP_EVAL]	26	1			T58	1		T44	1		T45	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T59

1

T234

1

T237

1

min

1788

1

T1

5

T6

3

T17

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1805	1			T1	5		T6	3		T17	20
pow[0x1]	12	1			T58	1		T59	1		T233	1
pow[0x2]	12	1			T34	1		T249	1		T237	1
pow[0x3]	34	1			T34	1		T58	1		T60	1
pow[0x4]	58	1			T58	2		T60	1		T59	1
pow[0x5]	116	1			T34	1		T58	1		T60	2
pow[0x6]	218	1			T34	3		T42	1		T58	3
pow[0x7]	522	1			T1	1		T11	1		T18	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

168

1

T34

2

T58

1

T60

4

min

1289

1

T1

4

T6

3

T17

20

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1305	1			T1	4		T6	3		T17	20
pow[0x1]	15	1			T11	1		T43	3		T45	1
pow[0x2]	10	1			T46	1		T253	1		T22	1
pow[0x3]	21	1			T11	2		T44	2		T46	2
pow[0x4]	18	1			T1	1		T42	2		T44	1
pow[0x8]	5	1			T59	1		T246	1		T229	1
pow[0x9]	11	1			T58	1		T59	1		T228	1
pow[0xa]	14	1			T64	1		T234	1		T228	1
pow[0xb]	38	1			T58	2		T60	1		T59	1
pow[0xc]	64	1			T34	1		T60	1		T64	2
pow[0xd]	143	1			T34	2		T58	1		T60	2
pow[0xe]	293	1			T34	4		T58	5		T60	3
pow[0xf]	554	1			T18	1		T34	11		T42	1