Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2373	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2377	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2506	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2418	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2364	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2489	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2654	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2431	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2451	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2574	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2501	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2487	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2416	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2307	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2385	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2461	0	0
adc_en_ctl_rd_A	2147483647	2156	0	0
adc_fsm_rst_rd_A	2147483647	1803	0	0
adc_intr_ctl_rd_A	2147483647	2116	0	0
adc_lp_sample_ctl_rd_A	2147483647	1879	0	0
adc_pd_ctl_rd_A	2147483647	2237	0	0
adc_sample_ctl_rd_A	2147483647	1858	0	0
adc_wakeup_ctl_rd_A	2147483647	1897	0	0
intr_enable_rd_A	2147483647	2303	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2373	0	0
T18	297404	15	0	0
T19	0	20	0	0
T20	0	41	0	0
T21	0	9	0	0
T22	0	41	0	0
T23	0	26	0	0
T24	0	42	0	0
T25	0	45	0	0
T26	0	42	0	0
T27	0	40	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2377	0	0
T18	297404	17	0	0
T19	0	23	0	0
T20	0	27	0	0
T21	0	20	0	0
T22	0	32	0	0
T23	0	24	0	0
T24	0	32	0	0
T25	0	39	0	0
T26	0	32	0	0
T27	0	49	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2506	0	0
T18	297404	17	0	0
T19	0	12	0	0
T20	0	32	0	0
T21	0	15	0	0
T22	0	32	0	0
T23	0	26	0	0
T24	0	24	0	0
T25	0	36	0	0
T26	0	53	0	0
T27	0	41	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2418	0	0
T18	297404	14	0	0
T19	0	15	0	0
T20	0	41	0	0
T21	0	16	0	0
T22	0	39	0	0
T23	0	27	0	0
T24	0	43	0	0
T25	0	41	0	0
T26	0	19	0	0
T27	0	28	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2364	0	0
T18	297404	19	0	0
T19	0	17	0	0
T20	0	45	0	0
T21	0	20	0	0
T22	0	34	0	0
T23	0	15	0	0
T24	0	26	0	0
T25	0	44	0	0
T26	0	36	0	0
T27	0	44	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2489	0	0
T18	297404	21	0	0
T19	0	14	0	0
T20	0	19	0	0
T21	0	20	0	0
T22	0	38	0	0
T23	0	32	0	0
T24	0	33	0	0
T25	0	39	0	0
T26	0	44	0	0
T27	0	48	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2654	0	0
T18	297404	16	0	0
T19	0	21	0	0
T20	0	44	0	0
T21	0	22	0	0
T22	0	50	0	0
T23	0	27	0	0
T24	0	35	0	0
T25	0	41	0	0
T26	0	66	0	0
T27	0	31	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2431	0	0
T18	297404	23	0	0
T19	0	10	0	0
T20	0	27	0	0
T21	0	12	0	0
T22	0	27	0	0
T23	0	27	0	0
T24	0	37	0	0
T25	0	33	0	0
T26	0	42	0	0
T27	0	40	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2451	0	0
T18	297404	20	0	0
T19	0	18	0	0
T20	0	28	0	0
T21	0	8	0	0
T22	0	46	0	0
T23	0	21	0	0
T24	0	47	0	0
T25	0	32	0	0
T26	0	49	0	0
T27	0	31	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2574	0	0
T18	297404	21	0	0
T19	0	20	0	0
T20	0	28	0	0
T21	0	16	0	0
T22	0	13	0	0
T23	0	32	0	0
T24	0	34	0	0
T25	0	49	0	0
T26	0	56	0	0
T27	0	52	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2501	0	0
T18	297404	29	0	0
T19	0	11	0	0
T20	0	42	0	0
T21	0	29	0	0
T22	0	43	0	0
T23	0	21	0	0
T24	0	20	0	0
T25	0	37	0	0
T26	0	44	0	0
T27	0	43	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2487	0	0
T18	297404	14	0	0
T19	0	6	0	0
T20	0	30	0	0
T21	0	17	0	0
T22	0	20	0	0
T23	0	41	0	0
T24	0	10	0	0
T25	0	32	0	0
T26	0	24	0	0
T27	0	45	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2416	0	0
T18	297404	17	0	0
T19	0	1	0	0
T20	0	46	0	0
T21	0	19	0	0
T22	0	35	0	0
T23	0	22	0	0
T24	0	55	0	0
T25	0	39	0	0
T26	0	43	0	0
T27	0	30	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2307	0	0
T18	297404	20	0	0
T19	0	14	0	0
T20	0	46	0	0
T21	0	17	0	0
T22	0	39	0	0
T23	0	29	0	0
T24	0	37	0	0
T25	0	37	0	0
T26	0	28	0	0
T27	0	36	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2385	0	0
T18	297404	24	0	0
T19	0	12	0	0
T20	0	45	0	0
T21	0	19	0	0
T22	0	39	0	0
T23	0	19	0	0
T24	0	27	0	0
T25	0	26	0	0
T26	0	32	0	0
T27	0	27	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2461	0	0
T18	297404	21	0	0
T19	0	13	0	0
T20	0	44	0	0
T21	0	19	0	0
T22	0	28	0	0
T23	0	37	0	0
T24	0	30	0	0
T25	0	35	0	0
T26	0	26	0	0
T27	0	32	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2156	0	0
T18	297404	30	0	0
T19	0	22	0	0
T20	0	43	0	0
T21	0	11	0	0
T22	0	40	0	0
T23	0	31	0	0
T24	0	18	0	0
T25	0	37	0	0
T26	0	57	0	0
T27	0	19	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1803	0	0
T18	297404	18	0	0
T19	0	29	0	0
T20	0	48	0	0
T21	0	23	0	0
T22	0	31	0	0
T23	0	27	0	0
T24	0	37	0	0
T25	0	29	0	0
T26	0	32	0	0
T27	0	52	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2116	0	0
T18	297404	21	0	0
T19	0	3	0	0
T20	0	24	0	0
T21	0	18	0	0
T22	0	30	0	0
T23	0	34	0	0
T24	0	25	0	0
T25	0	27	0	0
T26	0	37	0	0
T27	0	25	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1879	0	0
T18	297404	25	0	0
T19	0	32	0	0
T20	0	48	0	0
T21	0	20	0	0
T22	0	41	0	0
T23	0	21	0	0
T24	0	31	0	0
T25	0	50	0	0
T26	0	45	0	0
T27	0	30	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2237	0	0
T18	297404	30	0	0
T19	0	21	0	0
T20	0	41	0	0
T21	0	22	0	0
T22	0	46	0	0
T23	0	18	0	0
T24	0	34	0	0
T25	0	39	0	0
T26	0	42	0	0
T27	0	43	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1858	0	0
T18	297404	14	0	0
T19	0	14	0	0
T20	0	29	0	0
T21	0	8	0	0
T22	0	35	0	0
T23	0	17	0	0
T24	0	20	0	0
T25	0	28	0	0
T26	0	48	0	0
T27	0	39	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1897	0	0
T18	297404	20	0	0
T19	0	20	0	0
T20	0	28	0	0
T21	0	10	0	0
T22	0	34	0	0
T23	0	26	0	0
T24	0	30	0	0
T25	0	42	0	0
T26	0	38	0	0
T27	0	36	0	0
T28	142124	0	0	0
T29	810612	0	0	0
T30	520194	0	0	0
T31	422395	0	0	0
T32	420965	0	0	0
T33	757235	0	0	0
T34	247378	0	0	0
T35	400314	0	0	0
T36	754827	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2303	0	0
T6	145952	15	0	0
T7	148226	0	0	0
T8	229113	0	0	0
T9	85032	0	0	0
T10	148532	0	0	0
T11	416694	0	0	0
T12	250297	0	0	0
T17	746772	0	0	0
T18	0	13	0	0
T19	0	4	0	0
T20	0	70	0	0
T21	0	19	0	0
T22	0	48	0	0
T23	0	40	0	0
T37	0	2	0	0
T38	0	12	0	0
T39	0	39	0	0
T40	67556	0	0	0
T41	118731	0	0	0