Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1128151	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1109080

1

T1

488

T2

31

T3

6419

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1968999	1			T1	868		T3	12118		T13	1
values[0x0]	134369	1			T1	53		T2	26		T3	387
values[0x1]	133863	1			T1	58		T2	32		T3	381

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	904164	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1333067

1

T1

588

T2

36

T3

7728

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6278	1			T1	3		T3	46		T4	31
valid_sources[0x01]	11570	1			T1	7		T3	44		T4	9
valid_sources[0x02]	10648	1			T1	2		T3	36		T4	10
valid_sources[0x03]	6995	1			T1	6		T3	37		T4	11
valid_sources[0x04]	7235	1			T1	7		T3	47		T4	35
valid_sources[0x05]	14836	1			T1	11		T3	59		T4	22
valid_sources[0x06]	6213	1			T1	1		T3	52		T4	15
valid_sources[0x07]	11192	1			T3	60		T4	28		T5	33
valid_sources[0x08]	6421	1			T1	5		T3	44		T4	27
valid_sources[0x09]	6147	1			T1	14		T3	51		T4	23
valid_sources[0x0a]	19558	1			T1	2		T3	52		T4	12
valid_sources[0x0b]	14807	1			T1	8		T3	40		T4	16
valid_sources[0x0c]	7218	1			T1	11		T3	58		T4	17
valid_sources[0x0d]	11160	1			T1	2		T3	42		T4	16
valid_sources[0x0e]	6471	1			T1	1		T3	42		T4	13
valid_sources[0x0f]	6321	1			T1	3		T3	69		T4	24
valid_sources[0x10]	6487	1			T1	3		T3	62		T4	8
valid_sources[0x11]	7112	1			T1	4		T3	45		T4	8
valid_sources[0x12]	6600	1			T1	2		T3	50		T4	17
valid_sources[0x13]	6715	1			T1	5		T3	44		T4	11
valid_sources[0x14]	6231	1			T1	8		T3	48		T4	9
valid_sources[0x15]	12028	1			T1	4		T3	38		T4	12
valid_sources[0x16]	6933	1			T1	4		T3	42		T4	16
valid_sources[0x17]	6517	1			T1	4		T3	26		T4	11
valid_sources[0x18]	10823	1			T3	51		T4	26		T5	51
valid_sources[0x19]	9956	1			T3	56		T4	25		T5	35
valid_sources[0x1a]	10752	1			T1	4		T3	51		T4	19
valid_sources[0x1b]	6159	1			T1	2		T3	41		T4	13
valid_sources[0x1c]	7511	1			T1	1		T3	44		T4	22
valid_sources[0x1d]	6077	1			T1	2		T3	48		T4	32
valid_sources[0x1e]	6696	1			T1	1		T3	45		T4	14
valid_sources[0x1f]	6637	1			T1	4		T3	59		T4	17
valid_sources[0x20]	6399	1			T1	3		T3	51		T4	15
valid_sources[0x21]	6126	1			T1	1		T3	49		T4	9
valid_sources[0x22]	8293	1			T1	6		T3	47		T4	19
valid_sources[0x23]	9463	1			T1	4		T3	65		T4	22
valid_sources[0x24]	10858	1			T1	3		T3	51		T4	9
valid_sources[0x25]	6864	1			T1	3		T3	66		T4	12
valid_sources[0x26]	7661	1			T1	1		T3	49		T4	12
valid_sources[0x27]	9827	1			T1	2		T3	62		T4	8
valid_sources[0x28]	6375	1			T1	3		T3	59		T4	27
valid_sources[0x29]	9212	1			T1	4		T3	43		T4	12
valid_sources[0x2a]	6509	1			T1	5		T3	56		T4	5
valid_sources[0x2b]	7835	1			T1	3		T3	45		T4	24
valid_sources[0x2c]	6766	1			T1	2		T3	43		T4	16
valid_sources[0x2d]	7815	1			T1	3		T3	48		T4	10
valid_sources[0x2e]	10194	1			T1	5		T3	59		T4	22
valid_sources[0x2f]	10920	1			T1	8		T3	32		T4	13
valid_sources[0x30]	6457	1			T1	3		T3	57		T4	20
valid_sources[0x31]	6129	1			T1	2		T3	56		T4	19
valid_sources[0x32]	6555	1			T1	6		T3	43		T4	13
valid_sources[0x33]	10809	1			T1	3		T3	39		T13	9
valid_sources[0x34]	6481	1			T1	5		T3	52		T4	18
valid_sources[0x35]	7428	1			T1	2		T3	47		T4	8
valid_sources[0x36]	6596	1			T1	5		T3	52		T4	15
valid_sources[0x37]	6794	1			T1	3		T3	38		T4	12
valid_sources[0x38]	6460	1			T1	1		T3	37		T4	13
valid_sources[0x39]	15865	1			T1	5		T3	65		T4	23
valid_sources[0x3a]	12730	1			T1	4		T3	48		T4	19
valid_sources[0x3b]	6932	1			T1	3		T3	54		T4	5
valid_sources[0x3c]	6700	1			T3	49		T4	6		T5	41
valid_sources[0x3d]	11070	1			T1	1		T3	51		T4	30
valid_sources[0x3e]	11728	1			T1	2		T3	59		T4	22
valid_sources[0x3f]	7102	1			T1	4		T3	42		T4	16
valid_sources[0x40]	10912	1			T1	5		T3	53		T4	14
valid_sources[0x41]	6932	1			T1	1		T3	45		T4	19
valid_sources[0x42]	11252	1			T1	5		T3	65		T4	14
valid_sources[0x43]	19575	1			T1	1		T3	50		T4	16
valid_sources[0x44]	6253	1			T1	2		T3	37		T4	13
valid_sources[0x45]	11071	1			T1	3		T3	65		T4	11
valid_sources[0x46]	21467	1			T1	5		T3	54		T4	19
valid_sources[0x47]	6575	1			T1	6		T3	59		T4	18
valid_sources[0x48]	6297	1			T1	2		T3	60		T4	18
valid_sources[0x49]	6602	1			T1	5		T3	49		T4	15
valid_sources[0x4a]	8948	1			T1	2		T3	43		T4	30
valid_sources[0x4b]	6567	1			T1	4		T3	63		T4	16
valid_sources[0x4c]	6206	1			T1	6		T3	57		T4	11
valid_sources[0x4d]	6463	1			T1	1		T3	43		T4	13
valid_sources[0x4e]	6858	1			T1	3		T3	43		T4	27
valid_sources[0x4f]	12380	1			T1	6		T3	51		T4	21
valid_sources[0x50]	6848	1			T1	2		T3	44		T4	24
valid_sources[0x51]	7609	1			T1	9		T3	46		T4	15
valid_sources[0x52]	6964	1			T1	6		T3	53		T4	23
valid_sources[0x53]	8293	1			T1	2		T3	64		T4	6
valid_sources[0x54]	6248	1			T1	2		T3	32		T4	21
valid_sources[0x55]	7224	1			T1	5		T3	54		T4	14
valid_sources[0x56]	7379	1			T1	2		T3	52		T4	25
valid_sources[0x57]	26437	1			T1	5		T3	42		T4	21
valid_sources[0x58]	7226	1			T1	1		T3	53		T4	22
valid_sources[0x59]	10343	1			T1	5		T3	66		T4	22
valid_sources[0x5a]	8811	1			T1	5		T3	56		T4	15
valid_sources[0x5b]	6679	1			T1	5		T3	38		T4	21
valid_sources[0x5c]	6681	1			T1	5		T3	39		T4	11
valid_sources[0x5d]	6433	1			T1	1		T3	51		T4	14
valid_sources[0x5e]	20788	1			T1	8		T3	51		T4	17
valid_sources[0x5f]	6611	1			T1	5		T3	52		T4	13
valid_sources[0x60]	7526	1			T1	7		T3	36		T4	22
valid_sources[0x61]	6395	1			T1	5		T3	59		T4	31
valid_sources[0x62]	6308	1			T1	4		T3	65		T4	15
valid_sources[0x63]	6213	1			T1	4		T3	46		T4	28
valid_sources[0x64]	6366	1			T1	2		T3	56		T4	20
valid_sources[0x65]	10672	1			T1	5		T3	46		T4	16
valid_sources[0x66]	8740	1			T1	4		T3	39		T4	15
valid_sources[0x67]	14489	1			T1	2		T3	48		T4	25
valid_sources[0x68]	11924	1			T1	3		T3	30		T4	15
valid_sources[0x69]	6980	1			T1	1		T3	61		T4	7
valid_sources[0x6a]	6368	1			T1	3		T3	62		T4	15
valid_sources[0x6b]	6830	1			T1	2		T3	52		T4	10
valid_sources[0x6c]	9114	1			T1	5		T3	51		T4	5
valid_sources[0x6d]	6135	1			T1	4		T3	49		T4	16
valid_sources[0x6e]	9181	1			T1	9		T3	45		T4	18
valid_sources[0x6f]	6175	1			T1	3		T3	56		T4	12
valid_sources[0x70]	6539	1			T1	6		T3	46		T4	9
valid_sources[0x71]	7487	1			T1	5		T3	39		T4	25
valid_sources[0x72]	6723	1			T1	4		T3	53		T4	15
valid_sources[0x73]	12869	1			T1	4		T3	48		T4	30
valid_sources[0x74]	7240	1			T1	6		T3	58		T4	20
valid_sources[0x75]	6897	1			T1	5		T3	48		T4	16
valid_sources[0x76]	12266	1			T1	4		T3	47		T4	13
valid_sources[0x77]	9007	1			T1	13		T3	59		T4	38
valid_sources[0x78]	19583	1			T1	4		T3	45		T4	16
valid_sources[0x79]	6369	1			T1	4		T3	54		T4	21
valid_sources[0x7a]	7450	1			T1	6		T3	47		T4	24
valid_sources[0x7b]	6283	1			T1	4		T3	46		T4	10
valid_sources[0x7c]	11365	1			T1	6		T3	58		T4	10
valid_sources[0x7d]	12948	1			T1	6		T3	50		T4	32
valid_sources[0x7e]	6088	1			T1	1		T3	63		T4	28
valid_sources[0x7f]	6830	1			T1	4		T3	53		T4	11
valid_sources[0x80]	9063	1			T1	2		T3	53		T4	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

982294

1

T1

428

T3

6116

T13

1

values[0x0]

all_enables

biggest_size

73827

1

T1

30

T2

15

T3

194

values[0x1]

all_enables

biggest_size

52959

1

T1

30

T2

16

T3

109