Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27669	1			T1	4		T3	23		T4	6
auto[PWRUP]	100	1			T9	2		T58	1		T64	3
auto[ONEST_0]	72	1			T9	2		T58	1		T31	2
auto[ONEST_021]	16	1			T58	2		T64	1		T59	1
auto[ONEST_1]	72	1			T9	4		T58	2		T31	1
auto[ONEST_DONE]	3	1			T61	1		T227	1		T228	1
auto[LP_0]	100	1			T9	3		T47	1		T31	1
auto[LP_021]	21	1			T9	1		T31	1		T59	1
auto[LP_1]	118	1			T47	2		T58	2		T31	1
auto[LP_EVAL]	56	1			T9	2		T64	1		T60	1
auto[LP_SLP]	431	1			T9	1		T47	8		T58	3
auto[LP_PWRUP]	35	1			T60	2		T39	1		T229	1
auto[NP_0]	134	1			T47	1		T31	2		T64	2
auto[NP_021]	22	1			T60	1		T39	1		T229	1
auto[NP_1]	148	1			T9	2		T47	3		T64	1
auto[NP_EVAL]	21	1			T58	1		T31	2		T61	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T230

1

T231

1

T232

1

min

27206

1

T1

4

T3

23

T4

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27210	1			T1	4		T3	23		T4	6
pow[0x1]	6	1			T58	1		T233	1		T234	1
pow[0x2]	12	1			T176	1		T235	1		T236	1
pow[0x3]	29	1			T47	2		T60	2		T39	1
pow[0x4]	46	1			T31	2		T64	1		T59	1
pow[0x5]	107	1			T9	2		T47	2		T58	1
pow[0x6]	231	1			T9	2		T47	3		T58	4
pow[0x7]	434	1			T9	4		T47	7		T58	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

186

1

T9

2

T47

3

T58

2

min

26804

1

T1

4

T3

23

T4

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26804	1			T1	4		T3	23		T4	6
pow[0x4]	1	1			T31	1		-	-		-	-
pow[0x5]	1	1			T237	1		-	-		-	-
pow[0x7]	2	1			T47	1		T233	1		-	-
pow[0x8]	5	1			T238	1		T239	1		T63	1
pow[0x9]	9	1			T58	1		T176	1		T62	1
pow[0xa]	15	1			T9	1		T60	1		T39	1
pow[0xb]	34	1			T9	1		T47	1		T64	1
pow[0xc]	54	1			T31	1		T64	1		T59	4
pow[0xd]	119	1			T47	2		T31	4		T59	2
pow[0xe]	277	1			T9	5		T47	3		T58	2
pow[0xf]	498	1			T9	7		T47	6		T58	10